dri-devel June 2016

dri-devel@lists.freedesktop.org

231 participants
1446 discussions

[PATCH v2 1/2] drm/dsi: Implement dcs set/get display brightness
by Vinay Simha BN 14 Jun '16

14 Jun '16

Provide a small convenience wrapper that set/get the display brightness value Cc: John Stultz <john.stultz(a)linaro.org> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: Archit Taneja <archit.taneja(a)gmail.com> Cc: Rob Clark <robdclark(a)gmail.com> Cc: Jani Nikula <jani.nikula(a)linux.intel.com> Signed-off-by: Vinay Simha BN <simhavcs(a)gmail.com> -- v1: *tested in nexus7 2nd gen. v2: * implemented jani review comments -functions name mapped accordingly -bl value increased from 0xff to 0xffff -backlight interface will be handled in panel driver, so it is moved from the mipi_dsi helper function --- drivers/gpu/drm/drm_mipi_dsi.c | 49 ++++++++++++++++++++++++++++++++++++++++++ include/drm/drm_mipi_dsi.h | 4 ++++ 2 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index 7938ce7..5661a00 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -1025,6 +1025,55 @@ int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format) } EXPORT_SYMBOL(mipi_dsi_dcs_set_pixel_format); +/** + * mipi_dsi_dcs_get_display_brightness() - gets the current brightness value + * of the display + * @dsi: DSI peripheral device + * @brightness: brightness value + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, + u16 *brightness) +{ + ssize_t err; + + err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_BRIGHTNESS, + brightness, sizeof(*brightness)); + if (err < 0) { + if (err == 0) + err = -ENODATA; + + return err; + } + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_get_display_brightness); + +/** + * mipi_dsi_dcs_set_display_brightness() - sets the brightness value of + * the display + * @dsi: DSI peripheral device + * @brightness: brightness value + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi, + u16 brightness) +{ + ssize_t err; + u8 bl_value[2] = { brightness & 0xff, brightness >> 8 }; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + bl_value, sizeof(bl_value)); + if (err < 0) + return err; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_set_display_brightness); + static int mipi_dsi_drv_probe(struct device *dev) { struct mipi_dsi_driver *drv = to_mipi_dsi_driver(dev->driver); diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index ec55285..4494641 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -268,6 +268,10 @@ int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi); int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi, enum mipi_dsi_dcs_tear_mode mode); int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format); +int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, + u16 *brightness); +int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi, + u16 brightness); /** * struct mipi_dsi_driver - DSI driver -- 2.1.2

3 5

[PATCH 0/5] drm/tilcdc Fixes and cleanups
by Jyri Sarha 14 Jun '16

14 Jun '16

Some fixes and cleanups that should get merged to tilcdc even if my atomic changes are still a work in progress. Jyri Sarha (5): drm/tilcdc: Restore old dmps state in pm_resume() drm/tilcdc: Write to LCDC_END_OF_INT_IND_REG at the end of IRQ function drm/tilcdc: Move waiting of LCDC_FRAME_DONE IRQ into stop() drm/tilcdc: Refer to panel.txt and tfp410.txt bindings in tilcdc.txt drm/tilcdc: Avoid error print by of_graph_get_next_endpoint() .../devicetree/bindings/display/tilcdc/tilcdc.txt | 4 ++ drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 62 +++++++++++++--------- drivers/gpu/drm/tilcdc/tilcdc_drv.c | 3 ++ drivers/gpu/drm/tilcdc/tilcdc_drv.h | 2 + drivers/gpu/drm/tilcdc/tilcdc_external.c | 11 ++++ 5 files changed, 58 insertions(+), 24 deletions(-) -- 1.9.1

3 9

[PATCH v5] drm/i915/ilk: Don't disable SSC source if it's in use
by Lyude 14 Jun '16

14 Jun '16

Thanks to Ville Syrjälä for pointing me towards the cause of this issue. Unfortunately one of the sideaffects of having the refclk for a DPLL set to SSC is that as long as it's set to SSC, the GPU will prevent us from powering down any of the pipes or transcoders using it. A couple of BIOSes enable SSC in both PCH_DREF_CONTROL and in the DPLL configurations. This causes issues on the first modeset, since we don't expect SSC to be left on and as a result, can't successfully power down the pipes or the transcoders using it. Here's an example from this Dell OptiPlex 990: [drm:intel_modeset_init] SSC enabled by BIOS, overriding VBT which says disabled [drm:intel_modeset_init] 2 display pipes available. [drm:intel_update_cdclk] Current CD clock rate: 400000 kHz [drm:intel_update_max_cdclk] Max CD clock rate: 400000 kHz [drm:intel_update_max_cdclk] Max dotclock rate: 360000 kHz vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem [drm:intel_crt_reset] crt adpa set to 0xf40000 [drm:intel_dp_init_connector] Adding DP connector on port C [drm:intel_dp_aux_init] registering DPDDC-C bus for card0-DP-1 [drm:ironlake_init_pch_refclk] has_panel 0 has_lvds 0 has_ck505 0 [drm:ironlake_init_pch_refclk] Disabling SSC entirely … later we try committing the first modeset … [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff88041b02e800 for pipe A [drm:intel_dump_pipe_config] cpu_transcoder: A … [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xc4016001, dpll_md: 0x0, fp0: 0x20e08, fp1: 0x30d07 [drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled [drm:intel_dump_pipe_config] FB:42, fb = 800x600 format = 0x34325258 [drm:intel_dump_pipe_config] scaler:0 src (0, 0) 800x600 dst (0, 0) 800x600 [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [drm:intel_get_shared_dpll] CRTC:26 allocated PCH DPLL A [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [drm:ilk_audio_codec_disable] Disable audio codec on port C, pipe A [drm:intel_disable_pipe] disabling pipe A ------------[ cut here ]------------ WARNING: CPU: 1 PID: 130 at drivers/gpu/drm/i915/intel_display.c:1146 intel_disable_pipe+0x297/0x2d0 [i915] pipe_off wait timed out … ---[ end trace 94fc8aa03ae139e8 ]--- [drm:intel_dp_link_down] [drm:ironlake_crtc_disable [i915]] *ERROR* failed to disable transcoder A Later modesets succeed since they reset the DPLL's configuration anyway, but this is enough to get stuck with a big fat warning in dmesg. A better solution would be to add refcounts for the SSC source, but for now leaving the source clock on should suffice. Changes since v4: - Fix calculation of final for systems with LVDS panels (fixes BUG() on CI test suite) Changes since v3: - Move temp variable into loop - Move checks for using_ssc_source to after we've figured out has_ck505 - Add using_ssc_source to debug output Changes since v2: - Fix debug output for when we disable the CPU source Changes since v1: - Leave the SSC source clock on instead of just shutting it off on all of the DPLL configurations. Cc: stable(a)vger.kernel.org Reviewed-by: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Signed-off-by: Lyude <cpaul(a)redhat.com> --- drivers/gpu/drm/i915/intel_display.c | 48 +++++++++++++++++++++++++----------- 1 file changed, 34 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5c2dbf8..2d7f457 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8228,12 +8228,14 @@ static void ironlake_init_pch_refclk(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_encoder *encoder; + int i; u32 val, final; bool has_lvds = false; bool has_cpu_edp = false; bool has_panel = false; bool has_ck505 = false; bool can_ssc = false; + bool using_ssc_source = false; /* We need to take the global config into account */ for_each_intel_encoder(dev, encoder) { @@ -8260,8 +8262,22 @@ static void ironlake_init_pch_refclk(struct drm_device *dev) can_ssc = true; } - DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", - has_panel, has_lvds, has_ck505); + /* Check if any DPLLs are using the SSC source */ + for (i = 0; i < dev_priv->num_shared_dpll; i++) { + u32 temp = I915_READ(PCH_DPLL(i)); + + if (!(temp & DPLL_VCO_ENABLE)) + continue; + + if ((temp & PLL_REF_INPUT_MASK) == + PLLB_REF_INPUT_SPREADSPECTRUMIN) { + using_ssc_source = true; + break; + } + } + + DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", + has_panel, has_lvds, has_ck505, using_ssc_source); /* Ironlake: try to setup display ref clock before DPLL * enabling. This is only under driver's control after @@ -8298,9 +8314,9 @@ static void ironlake_init_pch_refclk(struct drm_device *dev) final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; } else final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; - } else { - final |= DREF_SSC_SOURCE_DISABLE; - final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; + } else if (using_ssc_source) { + final |= DREF_SSC_SOURCE_ENABLE; + final |= DREF_SSC1_ENABLE; } if (final == val) @@ -8346,7 +8362,7 @@ static void ironlake_init_pch_refclk(struct drm_device *dev) POSTING_READ(PCH_DREF_CONTROL); udelay(200); } else { - DRM_DEBUG_KMS("Disabling SSC entirely\n"); + DRM_DEBUG_KMS("Disabling CPU source output\n"); val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; @@ -8357,16 +8373,20 @@ static void ironlake_init_pch_refclk(struct drm_device *dev) POSTING_READ(PCH_DREF_CONTROL); udelay(200); - /* Turn off the SSC source */ - val &= ~DREF_SSC_SOURCE_MASK; - val |= DREF_SSC_SOURCE_DISABLE; + if (!using_ssc_source) { + DRM_DEBUG_KMS("Disabling SSC source\n"); - /* Turn off SSC1 */ - val &= ~DREF_SSC1_ENABLE; + /* Turn off the SSC source */ + val &= ~DREF_SSC_SOURCE_MASK; + val |= DREF_SSC_SOURCE_DISABLE; - I915_WRITE(PCH_DREF_CONTROL, val); - POSTING_READ(PCH_DREF_CONTROL); - udelay(200); + /* Turn off SSC1 */ + val &= ~DREF_SSC1_ENABLE; + + I915_WRITE(PCH_DREF_CONTROL, val); + POSTING_READ(PCH_DREF_CONTROL); + udelay(200); + } } BUG_ON(val != final); -- 2.5.5

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[PATCH] virtio-gpu: use src not crtc
by Gerd Hoffmann 14 Jun '16

14 Jun '16

Pick up the correct source rectangle from framebuffer. Without this multihead setups are not working correctly. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- drivers/gpu/drm/virtio/virtgpu_plane.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/virtio/virtgpu_plane.c b/drivers/gpu/drm/virtio/virtgpu_plane.c index b7778a7..925ca25 100644 --- a/drivers/gpu/drm/virtio/virtgpu_plane.c +++ b/drivers/gpu/drm/virtio/virtgpu_plane.c @@ -85,27 +85,32 @@ static void virtio_gpu_primary_plane_update(struct drm_plane *plane, if (bo->dumb) { virtio_gpu_cmd_transfer_to_host_2d (vgdev, handle, 0, - cpu_to_le32(plane->state->crtc_w), - cpu_to_le32(plane->state->crtc_h), - plane->state->crtc_x, plane->state->crtc_y, NULL); + cpu_to_le32(plane->state->src_w >> 16), + cpu_to_le32(plane->state->src_h >> 16), + plane->state->src_x >> 16, + plane->state->src_y >> 16, NULL); } } else { handle = 0; } - DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d\n", handle, + DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n", handle, plane->state->crtc_w, plane->state->crtc_h, - plane->state->crtc_x, plane->state->crtc_y); + plane->state->crtc_x, plane->state->crtc_y, + plane->state->src_w >> 16, + plane->state->src_h >> 16, + plane->state->src_x >> 16, + plane->state->src_y >> 16); virtio_gpu_cmd_set_scanout(vgdev, output->index, handle, - plane->state->crtc_w, - plane->state->crtc_h, - plane->state->crtc_x, - plane->state->crtc_y); + plane->state->src_w >> 16, + plane->state->src_h >> 16, + plane->state->src_x >> 16, + plane->state->src_y >> 16); virtio_gpu_cmd_resource_flush(vgdev, handle, - plane->state->crtc_x, - plane->state->crtc_y, - plane->state->crtc_w, - plane->state->crtc_h); + plane->state->src_x >> 16, + plane->state->src_y >> 16, + plane->state->src_w >> 16, + plane->state->src_h >> 16); } static void virtio_gpu_cursor_plane_update(struct drm_plane *plane, -- 1.8.3.1

2 2

[Bug 96445] [amdgpu][tonga] display freezes soon after X start
by bugzilla-daemon＠freedesktop.org 14 Jun '16

14 Jun '16

https://bugs.freedesktop.org/show_bug.cgi?id=96445 Bug ID: 96445 Summary: [amdgpu][tonga] display freezes soon after X start Product: DRI Version: DRI git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: DRM/AMDgpu Assignee: dri-devel(a)lists.freedesktop.org Reporter: csaba.halasz(a)gmail.com Starting X and just trying to do general stuff leads to display freeze within minutes. Most of the time nothing in syslog but during bisecting I have at least once seen this message which might be unrelated: [drm:process_one_work] *ERROR* ring sdma1 timeout, last signaled seq=144370, last emitted seq=144370 Initially I got an RCU stall message: INFO: rcu_sched detected stalls on CPUs/tasks: 3-...: (13593 GPs behind) idle=561/140000000000000/0 softirq=0/0 fqs=14996 5-...: (13593 GPs behind) idle=2e7/140000000000000/0 softirq=0/0 fqs=14996 (detected by 0, t=15002 jiffies, g=13293, c=13292, q=0) Task dump for CPU 3: sdma1 R running task 0 499 2 0x00080008 ffffffff810f83fb ffff8803e02de580 ffffffffa0333d01 ffff8800b9d1c110 ffff8800b89a3c00 ffff8800b89a3cd8 0000000000000000 ffff8800b9d1c110 ffffffffa036812b ffff8800b9fd58b8 ffffffff813c66bf ffff8800b9fd58b8 Call Trace: [<ffffffff810f83fb>] ? kmem_cache_free+0xab/0xc0 [<ffffffffa0333d01>] ? amdgpu_sync_get_fence+0x51/0xc0 [amdgpu] [<ffffffffa036812b>] ? amdgpu_job_dependency+0x2b/0xb0 [amdgpu] [<ffffffff813c66bf>] ? _raw_spin_lock_irqsave+0x1f/0x30 [<ffffffffa0367643>] ? amd_sched_main+0x1a3/0x3f0 [amdgpu] [<ffffffff81077310>] ? add_wait_queue+0x60/0x60 [<ffffffffa03674a0>] ? amd_sched_process_job+0x70/0x70 [amdgpu] [<ffffffff8105fbbc>] ? kthread+0xbc/0xe0 [<ffffffff813c6b02>] ? ret_from_fork+0x22/0x40 [<ffffffff8105fb00>] ? kthread_stop+0x70/0x70 Task dump for CPU 5: kworker/5:1 R running task 0 143 2 0x00080008 Workqueue: events amd_sched_job_finish [amdgpu] ffff88043ed57900 0000000000000000 ffffffff81059ae2 0000000000000018 ffff88042b4e0000 ffff88042b982d00 ffff88043ed53420 ffff88042b982d00 ffff88042b982d00 ffff88043ed53400 ffff8800ba673d80 ffff8800ba673db0 Call Trace: [<ffffffff81059ae2>] ? process_one_work+0x132/0x350 [<ffffffff8105b3fe>] ? worker_thread+0x11e/0x430 [<ffffffff8105b2e0>] ? create_worker+0x180/0x180 [<ffffffff8105fbbc>] ? kthread+0xbc/0xe0 [<ffffffff813c6b02>] ? ret_from_fork+0x22/0x40 [<ffffffff8105fb00>] ? kthread_stop+0x70/0x70 During bisecting I probably did not wait long enough for this to show up (apparently it's configured for 1 minute). According to git bisect: 8df07daf3952b7606e2d17076198ec3fb38ab1f1 is the first bad commit commit 8df07daf3952b7606e2d17076198ec3fb38ab1f1 Date: Thu May 19 09:54:15 2016 +0200 drm/amdgpu: fix and cleanup job destruction kernel agd5f/drm-next-4.8-wip mesa git 65c2abf6fdd51b0a80a72caa0c52cf3f4578e743 llvm git ef1f2996c17c9b1480201239002b58851810e8fc xf86-video-amdgpu git 60ced5026ebc34d9f32c7618430b6a7ef7c8eb4b Xorg 1.18.0 mplayer svn r37870 gigabyte 380 (tonga) -- You are receiving this mail because: You are the assignee for the bug.

1 5

[PATCH] drm/i915: Fix missing unlock on error in i915_ppgtt_info()
by weiyj_lk＠163.com 14 Jun '16

14 Jun '16

From: Wei Yongjun <yongjun_wei(a)trendmicro.com.cn> Add the missing unlock before return from function i915_ppgtt_info() in the error handling case. Fixes: 1d2ac403ae3b(drm: Protect dev->filelist with its own mutex) Signed-off-by: Wei Yongjun <yongjun_wei(a)trendmicro.com.cn> --- drivers/gpu/drm/i915/i915_debugfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 3269033..1035468 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2365,16 +2365,16 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) task = get_pid_task(file->pid, PIDTYPE_PID); if (!task) { ret = -ESRCH; - goto out_put; + goto out_unlock; } seq_printf(m, "\nproc: %s\n", task->comm); put_task_struct(task); idr_for_each(&file_priv->context_idr, per_file_ctx, (void *)(unsigned long)m); } +out_unlock: mutex_unlock(&dev->filelist_mutex); -out_put: intel_runtime_pm_put(dev_priv); mutex_unlock(&dev->struct_mutex);

2 1

linux-next: manual merge of the drm tree with the drm-intel-fixes tree
by Stephen Rothwell 14 Jun '16

14 Jun '16

Hi Dave, Today's linux-next merge of the drm tree got a conflict in: drivers/gpu/drm/i915/intel_display.c between commit: a5aac5ab876a ("drm/i915: Check VBT for port presence in addition to the strap on VLV/CHV") from the drm-intel-fixes tree and commit: 457c52d87e5d ("drm/i915: Only ignore eDP ports that are connected") (which is also in the drm-intel-fixes tree) from the drm tree. I fixed it up (I used the version form the drm-intel-fixes tree) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. -- Cheers, Stephen Rothwell

1 0

linux-4.7-rc3/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:4836: wierd condition ?
by David Binderman 13 Jun '16

13 Jun '16

Hello there, linux-4.7-rc3/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:4836]: (style) Boolean result is used in bitwise operation. Clarify expression with parentheses. Source code is if ((ring->me == me_id) & (ring->pipe == pipe_id)) Maybe better code if ((ring->me == me_id) && (ring->pipe == pipe_id)) Also in the same file: [drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:3866]: (style) Variable 'data' is assigned a value that is never used. [drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:4321]: (style) Variable 'mc_shared_chmap' is assigned a value that is never used. [drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:4657]: (style) Variable 'tmp' is assigned a value that is never used. Regards David Binderman

2 1

[PATCH 1/3] dma-buf/sync_file: only enable fence signalling during wait
by Gustavo Padovan 13 Jun '16

13 Jun '16

From: Gustavo Padovan <gustavo.padovan(a)collabora.co.uk> Signalling doesn't need to be enabled at sync_file creation, it is only required if userspace waiting the fence to signal through poll(). Thus we delay fence_add_callback() until poll is called. It only adds the callback the first time poll() is called. This avoid re-adding the same callback multiple times. Signed-off-by: Gustavo Padovan <gustavo.padovan(a)collabora.co.uk> --- drivers/dma-buf/sync_file.c | 36 +++++++++++++++++++++++------------- include/linux/fence.h | 12 ++++++++++++ 2 files changed, 35 insertions(+), 13 deletions(-) diff --git a/drivers/dma-buf/sync_file.c b/drivers/dma-buf/sync_file.c index 00e9186..59f3445 100644 --- a/drivers/dma-buf/sync_file.c +++ b/drivers/dma-buf/sync_file.c @@ -91,9 +91,7 @@ struct sync_file *sync_file_create(struct fence *fence) sync_file->cbs[0].fence = fence; sync_file->cbs[0].sync_file = sync_file; - if (fence_add_callback(fence, &sync_file->cbs[0].cb, - fence_check_cb_func)) - atomic_dec(&sync_file->status); + INIT_LIST_HEAD(&sync_file->cbs[0].cb.node); sync_file_debug_add(sync_file); return sync_file; @@ -130,8 +128,7 @@ static void sync_file_add_pt(struct sync_file *sync_file, int *i, sync_file->cbs[*i].fence = fence; sync_file->cbs[*i].sync_file = sync_file; - if (!fence_add_callback(fence, &sync_file->cbs[*i].cb, - fence_check_cb_func)) { + if (!fence_is_signaled(fence)) { fence_get(fence); (*i)++; } @@ -212,11 +209,8 @@ static void sync_file_free(struct kref *kref) kref); int i; - for (i = 0; i < sync_file->num_fences; ++i) { - fence_remove_callback(sync_file->cbs[i].fence, - &sync_file->cbs[i].cb); + for (i = 0; i < sync_file->num_fences; ++i) fence_put(sync_file->cbs[i].fence); - } sync_file_debug_remove(sync_file); kfree(sync_file); @@ -233,17 +227,33 @@ static int sync_file_release(struct inode *inode, struct file *file) static unsigned int sync_file_poll(struct file *file, poll_table *wait) { struct sync_file *sync_file = file->private_data; - int status; + int status, i; poll_wait(file, &sync_file->wq, wait); + for (i = 0 ; i < sync_file->num_fences ; i++) { + if (fence_is_enabled(sync_file->cbs[i].fence)) + continue; + + if (fence_add_callback(sync_file->cbs[i].fence, + &sync_file->cbs[i].cb, + fence_check_cb_func)) + atomic_dec(&sync_file->status); + } + status = atomic_read(&sync_file->status); - if (!status) - return POLLIN; + if (status > 0) + return 0; + + for (i = 0 ; i < sync_file->num_fences ; i++) + fence_remove_callback(sync_file->cbs[i].fence, + &sync_file->cbs[i].cb); + if (status < 0) return POLLERR; - return 0; + + return POLLIN; } static long sync_file_ioctl_merge(struct sync_file *sync_file, diff --git a/include/linux/fence.h b/include/linux/fence.h index 523ea3f..95a70b2 100644 --- a/include/linux/fence.h +++ b/include/linux/fence.h @@ -283,6 +283,18 @@ fence_is_signaled(struct fence *fence) } /** + * fence_is_enabled - return an indication if signalling is enabled + * @fence: [in] the fence to check + * + * Returns true if signalling was already enabled, false if not. + */ +static inline bool +fence_is_enabled(struct fence *fence) +{ + return test_bit(FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags); +} + +/** * fence_is_later - return if f1 is chronologically later than f2 * @f1: [in] the first fence from the same context * @f2: [in] the second fence from the same context -- 2.5.5

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[PATCH v2] amdgpu: fix asic initialization for virtualized environments
by Andres Rodriguez 13 Jun '16

13 Jun '16

When executing in a PCI passthrough based virtuzliation environemnt, the hypervisor will usually attempt to send a PCIe bus reset signal to the ASIC when the VM reboots. In this scenario, the card is not correctly initialized, but we still consider it to be posted. Therefore, in a passthrough based environemnt we should always post the card to guarantee it is in a good state for driver initialization. However, if we are operating in SR-IOV mode it is up to the GIM driver to manage the asic state, therefore we should not post the card (and shouldn't be able to do it either). Signed-off-by: Andres Rodriguez <andres.rodriguez(a)amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +++++++++++++++- drivers/gpu/drm/amd/amdgpu/cik.c | 7 +++++++ drivers/gpu/drm/amd/amdgpu/vi.c | 15 +++++++++++++++ 4 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 26fe670..fe71dea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1835,6 +1835,8 @@ struct amdgpu_asic_funcs { /* MM block clocks */ int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); + /* query virtual capabilities */ + u32 (*get_virtual_caps)(struct amdgpu_device *adev); }; /* @@ -1932,8 +1934,12 @@ void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); /* GPU virtualization */ +#define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0) +#define AMDGPU_VIRT_CAPS_IS_VF (1 << 1) struct amdgpu_virtualization { bool supports_sr_iov; + bool is_virtual; + u32 caps; }; /* @@ -2226,6 +2232,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) +#define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev))) #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b494212..b98ebac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1392,6 +1392,14 @@ static int amdgpu_resume(struct amdgpu_device *adev) return 0; } +static bool amdgpu_device_is_virtual(void) +{ +#ifdef CONFIG_X86 + return boot_cpu_has(X86_FEATURE_HYPERVISOR); +#else + return false; +#endif +} /** * amdgpu_device_has_dal_support - check if dal is supported @@ -1560,8 +1568,14 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->virtualization.supports_sr_iov = amdgpu_atombios_has_gpu_virtualization_table(adev); + /* Check if we are executing in a virtualized environment */ + adev->virtualization.is_virtual = amdgpu_device_is_virtual(); + adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev); + /* Post card if necessary */ - if (!amdgpu_card_posted(adev)) { + if (!amdgpu_card_posted(adev) || + (adev->virtualization.is_virtual && + !adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN)) { if (!adev->bios) { dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n"); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 40f4fda..907bb28 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -963,6 +963,12 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev, return true; } +static u32 cik_get_virtual_caps(struct amdgpu_device *adev) +{ + /* CIK does not support SR-IOV */ + return 0; +} + static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { {mmGRBM_STATUS, false}, {mmGB_ADDR_CONFIG, false}, @@ -2176,6 +2182,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs = .get_xclk = &cik_get_xclk, .set_uvd_clocks = &cik_set_uvd_clocks, .set_vce_clocks = &cik_set_vce_clocks, + .get_virtual_caps = &cik_get_virtual_caps, /* these should be moved to their own ip modules */ .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle, diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 1ac0c91..6a7d531 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -422,6 +422,20 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev, return true; } +static u32 vi_get_virtual_caps(struct amdgpu_device *adev) +{ + u32 caps = 0; + u32 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); + + if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE)) + caps |= AMDGPU_VIRT_CAPS_SRIOV_EN; + + if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER)) + caps |= AMDGPU_VIRT_CAPS_IS_VF; + + return caps; +} + static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { {mmGB_MACROTILE_MODE7, true}, }; @@ -1452,6 +1466,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs = .get_xclk = &vi_get_xclk, .set_uvd_clocks = &vi_set_uvd_clocks, .set_vce_clocks = &vi_set_vce_clocks, + .get_virtual_caps = &vi_get_virtual_caps, /* these should be moved to their own ip modules */ .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter, .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle, -- 2.8.4

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dri-devel June 2016