dri-devel October 2017

dri-devel@lists.freedesktop.org

228 participants
1625 discussions

[PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
by Jani Nikula 11 Oct '17

11 Oct '17

Falling back to the lowest value is likely the only thing we can do, but doing it silently seems like a bad thing to do. Catch it early and make loud noises. Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: Thierry Reding <treding(a)nvidia.com> Cc: Rob Clark <robdclark(a)gmail.com> Cc: Sean Paul <seanpaul(a)chromium.org> Cc: Manasi Navare <manasi.d.navare(a)intel.com> Cc: dri-devel(a)lists.freedesktop.org Signed-off-by: Jani Nikula <jani.nikula(a)intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 08af8d6b844b..dca21b5a03ec 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -137,8 +137,10 @@ EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); u8 drm_dp_link_rate_to_bw_code(int link_rate) { switch (link_rate) { - case 162000: default: + WARN(1, "unknown DP link rate %d, using %x\n", link_rate, + DP_LINK_BW_1_62); + case 162000: return DP_LINK_BW_1_62; case 270000: return DP_LINK_BW_2_7; @@ -151,8 +153,9 @@ EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); int drm_dp_bw_code_to_link_rate(u8 link_bw) { switch (link_bw) { - case DP_LINK_BW_1_62: default: + WARN(1, "unknown DP link bw code %x, using 162000\n", link_bw); + case DP_LINK_BW_1_62: return 162000; case DP_LINK_BW_2_7: return 270000; -- 2.11.0

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[PATCH] drm: Add DPMS ioctl
by Alex Ivanov 11 Oct '17

11 Oct '17

Display power management should be available to user no matter whether display server implements it or not and should be made server agnostic (X.Org, Wayland compositor), without need of TTY change. Reasons: 1. User implements an own universal power management daemon. He has no interest to deal with server or switch to a free TTY, he wants to turn off the monitor in a simple way, like he controls power of other system components. 2. Some applications under X.Org like Electron-based ones like to prevent screen goning off giving user no way to fix that. 3. Many fresh new Wayland compositors don't implement DPMS at all and at the same time have TTY switch broken. Signed-off-by: Alex Ivanov <gnidorah(a)ya.ru> --- drivers/gpu/drm/drm_crtc_internal.h | 2 ++ drivers/gpu/drm/drm_ioctl.c | 1 + drivers/gpu/drm/drm_mode_object.c | 41 +++++++++++++++++++++++++++++++++++++ include/uapi/drm/drm.h | 1 + 4 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index a43582076b20..120dd40a5210 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -122,6 +122,8 @@ int drm_mode_obj_get_properties_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int drm_mode_obj_set_property_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); +int drm_mode_connector_dpms_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv); /* drm_encoder.c */ int drm_encoder_register_all(struct drm_device *dev); diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index a9ae6dd2d593..2cec1a382c7b 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -632,6 +632,7 @@ static const struct drm_ioctl_desc drm_ioctls[] = { DRM_IOCTL_DEF(DRM_IOCTL_MODE_DETACHMODE, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPERTY, drm_mode_getproperty_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPROPERTY, drm_mode_connector_property_set_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_DPMS, drm_mode_connector_dpms_ioctl, DRM_ROOT_ONLY|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPBLOB, drm_mode_getblob_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETFB, drm_mode_getfb, DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB, drm_mode_addfb, DRM_CONTROL_ALLOW|DRM_UNLOCKED), diff --git a/drivers/gpu/drm/drm_mode_object.c b/drivers/gpu/drm/drm_mode_object.c index 1055533792f3..9006cca4f7f1 100644 --- a/drivers/gpu/drm/drm_mode_object.c +++ b/drivers/gpu/drm/drm_mode_object.c @@ -500,3 +500,44 @@ int drm_mode_obj_set_property_ioctl(struct drm_device *dev, void *data, drm_mode_object_put(arg_obj); return ret; } + +int drm_mode_connector_dpms_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv) +{ + struct drm_mode_connector_set_property *conn_set_prop = data; + struct drm_mode_obj_set_property obj_set_prop = { + .value = conn_set_prop->value, + .obj_id = conn_set_prop->connector_id, + .obj_type = DRM_MODE_OBJECT_CONNECTOR + }; + + struct drm_mode_obj_set_property *arg = &obj_set_prop; + struct drm_mode_object *arg_obj; + struct drm_property *property; + int ret = -EINVAL; + + struct drm_connector *connector; + + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + return -EINVAL; + + arg_obj = drm_mode_object_find(dev, arg->obj_id, arg->obj_type); + if (!arg_obj) + return -ENOENT; + + if (!arg_obj->properties) + goto out_unref; + + /* XXX atomic */ + connector = obj_to_connector(arg_obj); + property = connector->dev->mode_config.dpms_property; + + if (drm_drv_uses_atomic_modeset(property->dev)) + ret = set_property_atomic(arg_obj, property, arg->value); + else + ret = set_property_legacy(arg_obj, property, arg->value); + +out_unref: + drm_mode_object_put(arg_obj); + return ret; +} diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index 97677cd6964d..f60c14af1bcc 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -862,6 +862,7 @@ extern "C" { #define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) #define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) #define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) +#define DRM_IOCTL_MODE_DPMS DRM_IOWR(0xC6, struct drm_mode_connector_set_property) /** * Device specific ioctls should only be in their respective headers -- 2.14.2

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[PATCH v8 0/3] Move backlight helper functions from tinydrm-helpers to linux/backlight
by Meghana Madhyastha 11 Oct '17

11 Oct '17

Move drm helper functions from tinydrm-helpers to linux/backlight for ease of use by callers in other drivers. Changes in v8: -Move backlight_enable and backlight_disable to linux/backlight.h as static inline functions. -Move drm_of_find_backlight to backlight.c and rename it to backlight_get. Meghana Madhyastha (3): drm/tinydrm: Move helper functions from tinydrm-helpers to backlight.h drm/tinydrm: Move tinydrm_of_find_backlight to backlight.c drm/tinydrm: Add devres versions of backlight_get drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c | 95 -------------------------- drivers/gpu/drm/tinydrm/mi0283qt.c | 3 +- drivers/gpu/drm/tinydrm/mipi-dbi.c | 3 +- drivers/video/backlight/backlight.c | 71 +++++++++++++++++++ include/drm/tinydrm/tinydrm-helpers.h | 5 -- include/linux/backlight.h | 55 +++++++++++++++ 6 files changed, 130 insertions(+), 102 deletions(-) -- 2.7.4

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Dynamically adding a PCI subfunction
by Ilia Mirkin 11 Oct '17

11 Oct '17

Hello, As a bit of background, all NVIDIA GPUs since GT215 have an audio subfunction for HDMI(/DP) audio to be sent to the sink. This generally works. However some, especially laptop, devices come up with that function disabled. We have a quirk to enable it when coming back from runpm, but that doesn't help the init case. Basically we have to write a bit to the PCI config space: https://github.com/torvalds/linux/blob/v4.12/drivers/gpu/drm/nouveau/nouvea… (MMIO 0x88000 is an alias for the PCI config space) This works for runtime pm resume, since the device was originally there and we just have to make sure the underlying device agrees with it, but when it's missing on boot, we have to convince linux that it exists, bind a driver, etc. What's the best way of going about doing that? Thanks, -ilia

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[PATCH] pci: Fix a possible sleep-in-atomic bug in pci_set_power_state
by Jia-Ju Bai 11 Oct '17

11 Oct '17

The drivers vt6655 and gma500 call pci_set_power_state under a spinlock, which may sleep. The function call paths are: gma_power_begin (acquire the spinlock) (drivers/gpu/drm/gma500/power.c) gma_resume_pci pci_set_power_state __pci_start_power_transition (drivers/pci/pci.c) msleep --> may sleep gma_power_begin (acquire the spinlock) (drivers/gpu/drm/gma500/power.c) gma_resume_pci pci_enable_device pci_enable_device_flags (drivers/pci/pci.c) do_pci_enable_device pci_set_power_state __pci_start_power_transition msleep --> may sleep vt6655_suspend (acquire the spinlock) (drivers/staging/vt6655/device_main.c) pci_set_power_state __pci_start_power_transition (drivers/pci/pci.c) msleep --> may sleep To fix these bugs, msleep is replaced with mdelay in __pci_start_power_transition These bugs are found by my static analysis tool and my code review. Signed-off-by: Jia-Ju Bai <baijiaju1990(a)163.com> --- drivers/pci/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 6078dfc..7b763a3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -823,7 +823,7 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) */ if (dev->runtime_d3cold) { if (dev->d3cold_delay) - msleep(dev->d3cold_delay); + mdelay(dev->d3cold_delay); /* * When powering on a bridge from D3cold, the * whole hierarchy may be powered on into -- 1.7.9.5

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[Bug 103187] [CI] igt@syncobj_wait@wait-[all|any]-interrupted - fail - Failed assertion: ret == -1 && errno == ETIME
by bugzilla-daemon＠freedesktop.org 11 Oct '17

11 Oct '17

https://bugs.freedesktop.org/show_bug.cgi?id=103187 Marta Löfstedt <marta.lofstedt(a)intel.com> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|RESOLVED |CLOSED --- Comment #3 from Marta Löfstedt <marta.lofstedt(a)intel.com> --- Fix integrated in CI_DRM_3209 the tests are passing. -- You are receiving this mail because: You are the assignee for the bug.

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[Bug 103188] [CI] igt@syncobj_wait@wait-[any|for-submit]-snapshot - fail - Failed assertion: wait.wait.first_signaled == 1
by bugzilla-daemon＠freedesktop.org 11 Oct '17

11 Oct '17

https://bugs.freedesktop.org/show_bug.cgi?id=103188 Marta Löfstedt <marta.lofstedt(a)intel.com> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|RESOLVED |CLOSED --- Comment #3 from Marta Löfstedt <marta.lofstedt(a)intel.com> --- Fix integrated in CI_DRM_3209 the tests are passing. -- You are receiving this mail because: You are the assignee for the bug.

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[drm-tip:drm-tip 899/925] drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c:54:6: error: implicit declaration of function 'regmap_field_read_poll_timeout'
by kbuild test robot 11 Oct '17

11 Oct '17

tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip head: 36e0e803d3d7fb3d74e9086ad7c749123661589e commit: 939d749ad6649c4123daf63a8bc053ea97ad2218 [899/925] drm/sun4i: hdmi: Add support for controller hardware variants config: arm-defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 939d749ad6649c4123daf63a8bc053ea97ad2218 # save the attached .config to linux build tree make.cross ARCH=arm Note: the drm-tip/drm-tip HEAD 36e0e803d3d7fb3d74e9086ad7c749123661589e builds fine. It only hurts bisectibility. All error/warnings (new ones prefixed by >>): drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c: In function 'fifo_transfer': >> drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c:54:6: error: implicit declaration of function 'regmap_field_read_poll_timeout' [-Werror=implicit-function-declaration] if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c:54:6: warning: 'reg' is used uninitialized in this function [-Wuninitialized] if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ reg & mask, len * byte_time_ns, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 100000)) ~~~~~~~ drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c: In function 'sun4i_hdmi_i2c_xfer': >> drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c:171:6: warning: 'reg' may be used uninitialized in this function [-Wmaybe-uninitialized] if (regmap_field_read_poll_timeout(hdmi->field_ddc_reset, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ reg, !reg, 100, 2000)) { ~~~~~~~~~~~~~~~~~~~~~ cc1: some warnings being treated as errors vim +/regmap_field_read_poll_timeout +54 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c 28 29 static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read) 30 { 31 /* 32 * 1 byte takes 9 clock cycles (8 bits + 1 ACK) = 90 us for 100 kHz 33 * clock. As clock rate is fixed, just round it up to 100 us. 34 */ 35 const unsigned long byte_time_ns = 100; 36 const u32 mask = SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK | 37 SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST | 38 SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE; 39 u32 reg; 40 /* 41 * If threshold is inclusive, then the FIFO may only have 42 * RX_THRESHOLD number of bytes, instead of RX_THRESHOLD + 1. 43 */ 44 int read_len = RX_THRESHOLD + 45 (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); 46 47 /* 48 * Limit transfer length by FIFO threshold or FIFO size. 49 * For TX the threshold is for an empty FIFO. 50 */ 51 len = min_t(int, len, read ? read_len : SUN4I_HDMI_DDC_FIFO_SIZE); 52 53 /* Wait until error, FIFO request bit set or transfer complete */ > 54 if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, 55 reg & mask, len * byte_time_ns, 56 100000)) 57 return -ETIMEDOUT; 58 59 if (reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) 60 return -EIO; 61 62 if (read) 63 readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); 64 else 65 writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); 66 67 /* Clear FIFO request bit by forcing a write to that bit */ 68 regmap_field_force_write(hdmi->field_ddc_int_status, 69 SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST); 70 71 return len; 72 } 73 74 static int xfer_msg(struct sun4i_hdmi *hdmi, struct i2c_msg *msg) 75 { 76 int i, len; 77 u32 reg; 78 79 /* Set FIFO direction */ 80 if (hdmi->variant->ddc_fifo_has_dir) { 81 reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); 82 reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK; 83 reg |= (msg->flags & I2C_M_RD) ? 84 SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ : 85 SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE; 86 writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); 87 } 88 89 /* Clear address register (not cleared by soft reset) */ 90 regmap_field_write(hdmi->field_ddc_addr_reg, 0); 91 92 /* Set I2C address */ 93 regmap_field_write(hdmi->field_ddc_slave_addr, msg->addr); 94 95 /* 96 * Set FIFO RX/TX thresholds and clear FIFO 97 * 98 * If threshold is inclusive, we can set the TX threshold to 99 * 0 instead of 1. 100 */ 101 regmap_field_write(hdmi->field_ddc_fifo_tx_thres, 102 hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); 103 regmap_field_write(hdmi->field_ddc_fifo_rx_thres, RX_THRESHOLD); 104 regmap_field_write(hdmi->field_ddc_fifo_clear, 1); 105 if (regmap_field_read_poll_timeout(hdmi->field_ddc_fifo_clear, 106 reg, !reg, 100, 2000)) 107 return -EIO; 108 109 /* Set transfer length */ 110 regmap_field_write(hdmi->field_ddc_byte_count, msg->len); 111 112 /* Set command */ 113 regmap_field_write(hdmi->field_ddc_cmd, 114 msg->flags & I2C_M_RD ? 115 SUN4I_HDMI_DDC_CMD_IMPLICIT_READ : 116 SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE); 117 118 /* Clear interrupt status bits by forcing a write */ 119 regmap_field_force_write(hdmi->field_ddc_int_status, 120 SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK | 121 SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST | 122 SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE); 123 124 /* Start command */ 125 regmap_field_write(hdmi->field_ddc_start, 1); 126 127 /* Transfer bytes */ 128 for (i = 0; i < msg->len; i += len) { 129 len = fifo_transfer(hdmi, msg->buf + i, msg->len - i, 130 msg->flags & I2C_M_RD); 131 if (len <= 0) 132 return len; 133 } 134 135 /* Wait for command to finish */ 136 if (regmap_field_read_poll_timeout(hdmi->field_ddc_start, 137 reg, !reg, 100, 100000)) 138 return -EIO; 139 140 /* Check for errors */ 141 regmap_field_read(hdmi->field_ddc_int_status, &reg); 142 if ((reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) || 143 !(reg & SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE)) { 144 return -EIO; 145 } 146 147 return 0; 148 } 149 150 static int sun4i_hdmi_i2c_xfer(struct i2c_adapter *adap, 151 struct i2c_msg *msgs, int num) 152 { 153 struct sun4i_hdmi *hdmi = i2c_get_adapdata(adap); 154 u32 reg; 155 int err, i, ret = num; 156 157 for (i = 0; i < num; i++) { 158 if (!msgs[i].len) 159 return -EINVAL; 160 if (msgs[i].len > SUN4I_HDMI_DDC_BYTE_COUNT_MAX) 161 return -EINVAL; 162 } 163 164 /* DDC clock needs to be enabled for the module to work */ 165 clk_prepare_enable(hdmi->ddc_clk); 166 clk_set_rate(hdmi->ddc_clk, 100000); 167 168 /* Reset I2C controller */ 169 regmap_field_write(hdmi->field_ddc_en, 1); 170 regmap_field_write(hdmi->field_ddc_reset, 1); > 171 if (regmap_field_read_poll_timeout(hdmi->field_ddc_reset, 172 reg, !reg, 100, 2000)) { 173 clk_disable_unprepare(hdmi->ddc_clk); 174 return -EIO; 175 } 176 177 regmap_field_write(hdmi->field_ddc_sck_en, 1); 178 regmap_field_write(hdmi->field_ddc_sda_en, 1); 179 180 for (i = 0; i < num; i++) { 181 err = xfer_msg(hdmi, &msgs[i]); 182 if (err) { 183 ret = err; 184 break; 185 } 186 } 187 188 clk_disable_unprepare(hdmi->ddc_clk); 189 return ret; 190 } 191 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

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[PATCH v6 1/5] drm/vc4: Move the DSI clock divider workaround closer to the clock call.
by Eric Anholt 11 Oct '17

11 Oct '17

We want the adjusted_mode->clock to be the actual clock we're expecting to program, so that consumers see the right values for clock and vrefresh. Signed-off-by: Eric Anholt <eric(a)anholt.net> --- drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c index d1e0dc908048..eb787eed8abe 100644 --- a/drivers/gpu/drm/vc4/vc4_dsi.c +++ b/drivers/gpu/drm/vc4/vc4_dsi.c @@ -859,11 +859,7 @@ static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder, pll_clock = parent_rate / divider; pixel_clock_hz = pll_clock / dsi->divider; - /* Round up the clk_set_rate() request slightly, since - * PLLD_DSI1 is an integer divider and its rate selection will - * never round up. - */ - adjusted_mode->clock = pixel_clock_hz / 1000 + 1; + adjusted_mode->clock = pixel_clock_hz / 1000; /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */ adjusted_mode->htotal = pixel_clock_hz / (mode->vrefresh * mode->vtotal); @@ -900,7 +896,11 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder) vc4_dsi_dump_regs(dsi); } - phy_clock = pixel_clock_hz * dsi->divider; + /* Round up the clk_set_rate() request slightly, since + * PLLD_DSI1 is an integer divider and its rate selection will + * never round up. + */ + phy_clock = (pixel_clock_hz + 1000) * dsi->divider; ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); if (ret) { dev_err(&dsi->pdev->dev, -- 2.14.1

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[PATCH] drm/vc4: Fix sleeps during the IRQ handler for DSI transactions.
by Eric Anholt 11 Oct '17

11 Oct '17

VC4's DSI1 has a bug where the AXI connection is broken for 32-bit writes from the CPU, so we use the DMA engine to DMA 32-bit values into registers instead. That sleeps, so we can't do it from the top half. As a solution (suggested by Arnd), we can mask the IRQ in the irqchip in the top half, and re-enable it from an irqthread. Signed-off-by: Eric Anholt <eric(a)anholt.net> --- drivers/gpu/drm/vc4/vc4_dsi.c | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c index ec1d646b3151..9556236b67d0 100644 --- a/drivers/gpu/drm/vc4/vc4_dsi.c +++ b/drivers/gpu/drm/vc4/vc4_dsi.c @@ -516,6 +516,8 @@ struct vc4_dsi { /* Whether we're on bcm2835's DSI0 or DSI1. */ int port; + int irq; + /* DSI channel for the panel we're connected to. */ u32 channel; u32 lanes; @@ -1360,6 +1362,28 @@ static void dsi_handle_error(struct vc4_dsi *dsi, *ret = IRQ_HANDLED; } +/* Initial handler for port 1 where we need the reg_dma workaround. + * The register DMA writes sleep, so we can't do it in the top half. + * Instead we just disable the interrupt in the only way we have + * available (mask it in the irqchip), and continue on to the threaded + * handler. + */ +static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data) +{ + struct vc4_dsi *dsi = data; + u32 stat = DSI_PORT_READ(INT_STAT); + + if (!stat) + return IRQ_NONE; + + disable_irq_nosync(dsi->irq); + + return IRQ_WAKE_THREAD; +} + +/* Normal IRQ handler for port 0, or the threaded IRQ handler for port + * 1 where we need the reg_dma workaround. + */ static irqreturn_t vc4_dsi_irq_handler(int irq, void *data) { struct vc4_dsi *dsi = data; @@ -1368,6 +1392,9 @@ static irqreturn_t vc4_dsi_irq_handler(int irq, void *data) DSI_PORT_WRITE(INT_STAT, stat); + if (dsi->reg_dma_mem) + enable_irq(dsi->irq); + dsi_handle_error(dsi, &ret, stat, DSI1_INT_ERR_SYNC_ESC, "LPDT sync"); dsi_handle_error(dsi, &ret, stat, @@ -1539,8 +1566,16 @@ static int vc4_dsi_bind(struct device *dev, struct device *master, void *data) /* Clear any existing interrupt state. */ DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT)); - ret = devm_request_irq(dev, platform_get_irq(pdev, 0), - vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); + dsi->irq = platform_get_irq(pdev, 0); + if (dsi->reg_dma_mem) { + ret = devm_request_threaded_irq(dev, dsi->irq, + vc4_dsi_irq_defer_to_thread_handler, + vc4_dsi_irq_handler, 0, + "vc4 dsi", dsi); + } else { + ret = devm_request_irq(dev, dsi->irq, + vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); + } if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "Failed to get interrupt: %d\n", ret); -- 2.14.1

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dri-devel October 2017