dri-devel October 2017

dri-devel@lists.freedesktop.org

228 participants
1625 discussions

[PATCH v3 0/2] drm/tinydrm: drm_of_find_backlight helper
by Meghana Madhyastha 06 Oct '17

06 Oct '17

This patchset introduces some changes such as move tinydrm_of_find_backlight to drm_of.c and rename it to drm_of_find_backlight for better organizational structure. Changes in v3: -Changed it back to a single patch for the caller in mi0283qt.c and the removal and renaming of the helper function. Meghana Madhyastha (2): drm/tinydrm: Move tinydrm_of_find_backlight into drm_of.c drm/tinydrm: Add devres versions of drm_of_find_backlight drivers/gpu/drm/drm_of.c | 92 ++++++++++++++++++++++++++ drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c | 40 ----------- drivers/gpu/drm/tinydrm/mi0283qt.c | 3 +- include/drm/drm_of.h | 3 + include/drm/tinydrm/tinydrm-helpers.h | 1 - 5 files changed, 97 insertions(+), 42 deletions(-) -- 2.7.4

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[radeon-alex:amd-staging-drm-next 2/4] drivers/gpu/drm/amd/amdgpu/../include/kgd_pp_interface.h:289:6: sparse: no newline at end of file
by kbuild test robot 06 Oct '17

06 Oct '17

tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next head: e5f6a57e350a7921e4edc30874679bdff11b13f4 commit: 082d03ab9f88d7c7a73b66f1e3540c617d009bad [2/4] drm/amdgpu: add header kgd_pp_interface.h reproduce: # apt-get install sparse git checkout 082d03ab9f88d7c7a73b66f1e3540c617d009bad make ARCH=x86_64 allmodconfig make C=1 CF=-D__CHECK_ENDIAN__ sparse warnings: (new ones prefixed by >>) vim +289 drivers/gpu/drm/amd/amdgpu/../include/kgd_pp_interface.h 288 > 289 #endif --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

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[pull] amdgpu drm-next-4.15-dc
by Alex Deucher 06 Oct '17

06 Oct '17

Hi Dave, Latest cleanups for DC from you and Harry. Note that there is some flickering on some older asics with this branch due to a regression in powerplay that has already been fixed and will be included in my next non-DC pull request next week. The following changes since commit dfbf0c14dd75d3b15f65478f10f373aa83042a50: drm/amdgpu: drop experimental flag for vega10 (2017-09-26 18:17:46 -0400) are available in the git repository at: git://people.freedesktop.org/~agd5f/linux drm-next-4.15-dc for you to fetch changes up to 8ee5702afdd48b5864c46418ad310d6a23c8e9ab: amdgpu/dc: use kref for dc_state. (2017-10-06 13:10:25 -0400) ---------------------------------------------------------------- Daniel Vetter (1): drm/amd: DC pull request review Dave Airlie (61): amdgpu/dc: add static to construct function amdgpu/dc: move filter taps to being static const data (v2) amdgpu/dc: drop display_pipe_clocks.c. amdgpu/dc: inline a bunch of float operations. amdgpu/dc: inline a bunch of the dml wrappers. amdgpu/dc: drop dml_util_is_420 amdgpu/dc: separate out some common code from bios parsers. amdgpu/dc: drop dml display_mode_support.c (v2) amdgpu/dc: don't check for 0 on register read/writes always. amdgpu/dc: remove wait_reg/wait_reg_func interfaces. amdgpu/dc: drop dc_ver char amdgpu/dc: static constify update_surface_trace_level amdgpu/dm: constify yuv_formats. amdgpu/dm: constify plane type. amdgpu/dm: constify rgb formats. amdgpu/dc: constify a bunch of dc structs. amdgpu/dc: make timing generator constructor return void. amdgpu/dc: make stream encoder constructor return void. amdgpu/dc: make link encoder construct void. amdgpu/dc: make opp construct void. amdgpu/dc: make dce transform constructor void amdgpu/dc: make dce80 timing generator construct return void. amdgpu/dc: make get_audio_clock_info return void. amdgpu/dc: make program_regamma_pwl return void amdgpu/dc: make some audio functions return void amdgpu/dc: remove pointless returns in the i2caux constructor paths. (v2) amdgpu/dc: cleanup construct returns in gpio. amdgpu/dc: another round of dce/dcn construct cleanups. amdgpu/dc: remove pointless return from build_pipe_hw_param amdgpu: fixup construct to void paths on some more dc objects. amdgpu/dc: fix construct return values on irq service. amdgpu/dc: inline some of the fixed 32_32 fns amdgpu/dc: inline a bunch of the fixed 31_32 helpers. amdgpu/dc: hide some unused aux/i2c payload apis. amdgpu/dc: move some one line dp functions to inlines. amdgpu/dc: inline some of the bw_fixed code. amdgpu/dc: allow inlining constant int to fixed a lot better. amdgpu/dc: use the builtin constant p trick on the 31/32 fixed point. amdgpu/dc: inline fixed31_32 div_int amdgpu/dc: inline all the signal_types code. amdgpu/dc: set some of the link dp code to static. amdgpu/dc: rename bios get_image symbol to something more searchable. amdgpu/dc: inline dml_round_to_multiple amdgpu/dc: inline dal grph object id functions. amdgpu/dc: don't memset after kzalloc. amdgpu/dc: use kernel ilog2 for log_2. amdgpu/dc: drop dce110_types.h amdgpu/dc: drop hw_sequencer_types.h amdgpu/dc: fix a bunch of misc whitespace. amdgpu/dc: kfree already checks for NULL. amdgpu/dm: don't use after free. amdgpu/dc: fix indentation on a couple of returns. amdgpu/dc: kill some deadcode in dc core. amdgpu/dc: set a bunch of functions to static. amdgpu/dc: kill a bunch of dead code. amdgpu/dc: convert dc_transfer to use a kref. amdgpu/dc: convert dc_gamma to kref reference counting. amdgpu/dc: use kref for dc_plane_state. amdgpu/dc: convert dc_stream_state to kref. amdgpu/dc: convert dc_sink to kref. amdgpu/dc: use kref for dc_state. Harry Wentland (4): drm/amd/display: Use kernel alloc/free drm/amd/display: DC I2C review drm/doc: Reference AMD DC todos drm/amd/display: Remove DWB Documentation/gpu/todo.rst | 10 + drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +- drivers/gpu/drm/amd/display/TODO | 54 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +- drivers/gpu/drm/amd/display/dc/basics/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/basics/conversion.c | 10 - drivers/gpu/drm/amd/display/dc/basics/conversion.h | 5 +- drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 153 +- drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c | 60 - .../gpu/drm/amd/display/dc/basics/grph_object_id.c | 61 +- drivers/gpu/drm/amd/display/dc/basics/logger.c | 18 +- .../gpu/drm/amd/display/dc/basics/signal_types.c | 80 - drivers/gpu/drm/amd/display/dc/basics/vector.c | 20 +- drivers/gpu/drm/amd/display/dc/bios/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 302 +-- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 307 +-- .../drm/amd/display/dc/bios/bios_parser_common.c | 288 +++ .../bios/bios_parser_common.h} | 10 +- .../drm/amd/display/dc/bios/bios_parser_helper.c | 2 +- .../drm/amd/display/dc/bios/bios_parser_helper.h | 4 +- drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c | 130 +- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 5 +- .../gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 29 - .../gpu/drm/amd/display/dc/calcs/dcn_calc_math.h | 36 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 8 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 273 +-- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 23 +- drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 42 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 32 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +- drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 59 +- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 42 +- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 80 +- drivers/gpu/drm/amd/display/dc/dc.h | 17 +- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 4 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 16 +- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 21 +- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 12 +- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 18 +- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 6 +- drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 2 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 6 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 6 +- drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 2 +- .../gpu/drm/amd/display/dc/dce/dce_scl_filters.c | 78 +- .../drm/amd/display/dc/dce/dce_stream_encoder.c | 74 +- .../drm/amd/display/dc/dce/dce_stream_encoder.h | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 10 +- drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 4 +- .../amd/display/dc/dce100/dce100_hw_sequencer.c | 4 +- .../amd/display/dc/dce100/dce100_hw_sequencer.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 105 +- .../drm/amd/display/dc/dce110/dce110_compressor.c | 15 +- .../drm/amd/display/dc/dce110/dce110_compressor.h | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 2 +- .../amd/display/dc/dce110/dce110_opp_regamma_v.c | 4 +- .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 4 +- .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 2 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 133 +- .../drm/amd/display/dc/dce110/dce110_resource.h | 2 +- .../display/dc/dce110/dce110_timing_generator.c | 11 +- .../display/dc/dce110/dce110_timing_generator.h | 3 +- .../display/dc/dce110/dce110_timing_generator_v.c | 7 +- .../display/dc/dce110/dce110_timing_generator_v.h | 2 +- .../drm/amd/display/dc/dce110/dce110_transform_v.c | 2 +- .../drm/amd/display/dc/dce110/dce110_transform_v.h | 2 +- .../gpu/drm/amd/display/dc/dce110/dce110_types.h | 30 - .../drm/amd/display/dc/dce112/dce112_compressor.c | 15 +- .../drm/amd/display/dc/dce112/dce112_compressor.h | 2 +- .../amd/display/dc/dce112/dce112_hw_sequencer.c | 4 +- .../amd/display/dc/dce112/dce112_hw_sequencer.h | 2 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 108 +- .../amd/display/dc/dce120/dce120_hw_sequencer.c | 4 +- .../amd/display/dc/dce120/dce120_hw_sequencer.h | 2 +- .../drm/amd/display/dc/dce120/dce120_resource.c | 98 +- .../display/dc/dce120/dce120_timing_generator.c | 9 +- .../display/dc/dce120/dce120_timing_generator.h | 3 +- .../drm/amd/display/dc/dce80/dce80_compressor.c | 15 +- .../drm/amd/display/dc/dce80/dce80_compressor.h | 2 +- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 4 +- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 116 +- .../amd/display/dc/dce80/dce80_timing_generator.c | 7 +- .../amd/display/dc/dce80/dce80_timing_generator.h | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 10 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 365 --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h | 277 --- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 50 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 162 +- .../amd/display/dc/dcn10/dcn10_timing_generator.c | 2 +- drivers/gpu/drm/amd/display/dc/dm_services.h | 55 +- drivers/gpu/drm/amd/display/dc/dml/Makefile | 6 +- .../gpu/drm/amd/display/dc/dml/display_mode_lib.h | 1 - .../drm/amd/display/dc/dml/display_mode_support.c | 2326 -------------------- .../drm/amd/display/dc/dml/display_mode_support.h | 5 - .../drm/amd/display/dc/dml/display_pipe_clocks.c | 367 --- .../drm/amd/display/dc/dml/display_pipe_clocks.h | 41 - .../drm/amd/display/dc/dml/display_rq_dlg_calc.c | 2 + .../gpu/drm/amd/display/dc/dml/display_watermark.c | 1 + .../gpu/drm/amd/display/dc/dml/dml_common_defs.c | 108 +- .../gpu/drm/amd/display/dc/dml/dml_common_defs.h | 14 - .../gpu/drm/amd/display/dc/dml/dml_inline_defs.h | 80 + .../gpu/drm/amd/display/dc/dml/soc_bounding_box.c | 1 + drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c | 4 +- drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c | 21 +- drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 35 +- drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 2 +- drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c | 4 +- drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h | 2 +- drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c | 49 +- drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c | 6 +- drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h | 2 +- .../amd/display/dc/i2caux/dce100/i2caux_dce100.c | 23 +- .../display/dc/i2caux/dce110/aux_engine_dce110.c | 24 +- .../dc/i2caux/dce110/i2c_hw_engine_dce110.c | 29 +- .../dc/i2caux/dce110/i2c_hw_engine_dce110.h | 4 - .../dc/i2caux/dce110/i2c_sw_engine_dce110.c | 25 +- .../amd/display/dc/i2caux/dce110/i2caux_dce110.c | 34 +- .../amd/display/dc/i2caux/dce110/i2caux_dce110.h | 2 +- .../amd/display/dc/i2caux/dce112/i2caux_dce112.c | 32 +- .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 23 +- .../display/dc/i2caux/dce80/i2c_hw_engine_dce80.c | 36 +- .../display/dc/i2caux/dce80/i2c_sw_engine_dce80.c | 23 +- .../drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c | 23 +- .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 23 +- .../display/dc/i2caux/diagnostics/i2caux_diag.c | 25 +- drivers/gpu/drm/amd/display/dc/i2caux/engine.h | 2 +- .../gpu/drm/amd/display/dc/i2caux/engine_base.c | 3 +- drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c | 7 +- drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h | 2 +- .../amd/display/dc/i2caux/i2c_generic_hw_engine.c | 6 +- .../amd/display/dc/i2caux/i2c_generic_hw_engine.h | 2 +- .../gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c | 6 +- .../gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h | 2 +- .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c | 21 +- .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h | 2 +- drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 +- drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h | 137 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 6 +- drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h | 10 - drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 8 - drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 193 -- .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 1 - drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 6 +- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 17 +- .../amd/display/dc/irq/dce120/irq_service_dce120.c | 17 +- .../amd/display/dc/irq/dce80/irq_service_dce80.c | 17 +- .../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 17 +- drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 11 +- drivers/gpu/drm/amd/display/dc/irq/irq_service.h | 2 +- drivers/gpu/drm/amd/display/dc/os_types.h | 2 + .../amd/display/dc/virtual/virtual_link_encoder.c | 2 +- .../display/dc/virtual/virtual_stream_encoder.c | 4 +- drivers/gpu/drm/amd/display/include/fixed31_32.h | 156 +- drivers/gpu/drm/amd/display/include/fixed32_32.h | 76 +- .../amd/display/include/grph_object_ctrl_defs.h | 20 +- .../gpu/drm/amd/display/include/grph_object_id.h | 72 +- drivers/gpu/drm/amd/display/include/signal_types.h | 59 +- .../drm/amd/display/modules/freesync/freesync.c | 14 +- 171 files changed, 1800 insertions(+), 6644 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/basics/signal_types.c create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c rename drivers/gpu/drm/amd/display/{include/hw_sequencer_types.h => dc/bios/bios_parser_common.h} (85%) delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_types.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h delete mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.h create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

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Task based virtual address spaces
by Jordan Crouse 06 Oct '17

06 Oct '17

Trying to start back up the conversation about multiple address spaces for IOMMU devices. If you will remember Jean-Philippe posted some patches back in February for SVM on arm-smmu-v3. For quite some time the downstream Snapdragon kernels have supported something we call "per-process" page tables for the GPU. As with full SVM this involves creating a virtual address space per task but unlike SVM we don't automatically share the page table from the CPU. Instead we want to create a new page table and explicitly map/unmap address ranges into it. We provide the physical address of the page table to the GPU and it goes through the mechanics of programming the TTBR0 and invalidating the TLB when starts executing a submission for a given task. As with all things IOMMU this discussion needs to be split into two parts - the API and the implementation. I want to focus on the generic API for this email. Shortly after Jean-Philippe posted his patches I sent out a rough prototype of how the downstream solution worked [1]: +-----------------+ +------------------+ | "master" domain | ---> | "dynamic" domain | +-----------------+ \ +------------------+ \ \ +------------------+ - | "dynamic" domain | +------------------+ Given a "master" domain (created in the normal way) we can create any number of "dynamic" domains which share the same configuration as the master (table format, context bank, quirks, etc). When the dynamic domain is allocated/ attached it creates a new page table - for all intents and purposes this is a "real" domain except that it doesn't actually touch the hardware. We can use this domain with iommu_map() / iommu_unmap() as usual and then pass the physical address (acquired through a IOMMU domain attribute) to the GPU and everything works. The main goal for this approach was to try to use the iommu API instead of teaching the GPU driver how to deal with several generations of page table formats and IOMMU devices. Shoehorning it into the domain struct was a path of least resistance that has served Snapdragon well but it was never really anything we considered to be a generic solution. In the SVM patches, Jean-Philippe introduces iommu_bind_task(): https://patchwork.codeaurora.org/patch/184777/. Given a struct task and a bit of other stuff it goes off and does SVM magic. My proposal would be to extend this slightly and return a iommu_task struct from iommu_bind_task: struct iommu_task *iommu_bind_task(struct device *dev, strut task_strut *task, int *pasid, int flags, void *priv); For implementations that did real SVM the rest would behave the same, but for targets with explicit map requirements the iommu_task token could then be used for map/unmap: iommu_task_map(struct iommu_task *task, unsigned long iova, phys_addr_t paddr, size_t size, int prot); iommu_task_unmap(struct iommu_task *task, unsigned long iova, size_t size); int iommu_unbind_task(struct device *dev, struct iommu_task *task, int pasid, int flags); (Note that I'm typing these up on the fly - don't take these prototypes as gospel. This is mostly just a representation of the hooks we would need). Internally this would come down into the device drivers with code similar to https://patchwork.codeaurora.org/patch/184751/. At the device level the biggest question figuring out if this is the "full SVM" or "explicit" model - we could handle that with compatible strings or dt quirks or even a flag to iommu_bind_task(). On Snapdragon we have the additional requirement to get the physical address for the page table. That could be encoded into pasid or returned in the iommu_task struct or a task attribute function. Comments welcome of course. I think that if we can focus on getting a good generic API nailed down we can drill into the specifics. Between the 410c and the 820c we have two good examples that we can rapidly prototype. I would like to get this on the radar so we can get it merged and stabilized with enough time to hit a LTS release. Thanks, Jordan [1] https://patchwork.codeaurora.org/patch/192573/ https://patchwork.codeaurora.org/patch/192571/ https://patchwork.codeaurora.org/patch/192577/ https://patchwork.codeaurora.org/patch/192579/ -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

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[ANNOUNCE] dim-tools mailing list for drm maintainer tools
by Jani Nikula 06 Oct '17

06 Oct '17

The drm maintainer tools and documentation [1][2], the dim script in particular, have expanded in use and features and especially user base beyond at least my imagination. It's time to move the maintainer tools patches and discussion away from the intel-gfx mailing list, but it seems best to not clutter dri-devel any more. Hence we're introducing a new dim-tools mailing list [3] for announcements, discussion, and development of drm maintainer tools and documentation. Please subscribe to the list if you use dim, so we can reach out to all users with announcements. Some of you have been automatically subscribed; apologies if this was not what you wanted. BR, Jani. [1] https://cgit.freedesktop.org/drm/drm-intel/log/?h=maintainer-tools [2] https://01.org/linuxgraphics/gfx-docs/maintainer-tools/index.html [3] https://lists.freedesktop.org/mailman/listinfo/dim-tools -- Jani Nikula, Intel Open Source Technology Center

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[PATCH 1/1] drm/mgag200: Expose version string
by mathieu.larouche＠matrox.com 06 Oct '17

06 Oct '17

From: Mathieu Larouche <mathieu.larouche(a)matrox.com> OEMs started distributing this module out of the box so adding the version in modinfo output for this module may be a good idea. Signed-off-by: Mathieu Larouche <mathieu.larouche(a)matrox.com> --- drivers/gpu/drm/mgag200/mgag200_drv.c | 3 +++ drivers/gpu/drm/mgag200/mgag200_drv.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c b/drivers/gpu/drm/mgag200/mgag200_drv.c index 9ac0078..ad3f193 100644 --- a/drivers/gpu/drm/mgag200/mgag200_drv.c +++ b/drivers/gpu/drm/mgag200/mgag200_drv.c @@ -134,3 +134,6 @@ static void __exit mgag200_exit(void) MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL"); +MODULE_VERSION(__stringify(DRIVER_MAJOR) "." + __stringify(DRIVER_MINOR) "." + __stringify(DRIVER_PATCHLEVEL)); diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h b/drivers/gpu/drm/mgag200/mgag200_drv.h index c88b6ec..df4833b 100644 --- a/drivers/gpu/drm/mgag200/mgag200_drv.h +++ b/drivers/gpu/drm/mgag200/mgag200_drv.h @@ -37,7 +37,7 @@ #define DRIVER_DATE "20110418" #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 0 +#define DRIVER_MINOR 1 #define DRIVER_PATCHLEVEL 0 #define MGAG200FB_CONN_LIMIT 1 -- 1.8.3.1

3 2

[drm-intel:for-linux-next 2/2] drivers/gpu//drm/i915/i915_guc_submission.c:391:25: warning: cast from pointer to integer of different size
by kbuild test robot 06 Oct '17

06 Oct '17

tree: git://anongit.freedesktop.org/drm-intel for-linux-next head: faf654864b25f4ca4efd416145d37b794c0b805f commit: faf654864b25f4ca4efd416145d37b794c0b805f [2/2] drm/i915: Unify uC variable types to avoid flooding checkpatch.pl config: i386-randconfig-x005-201740 (attached as .config) compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901 reproduce: git checkout faf654864b25f4ca4efd416145d37b794c0b805f # save the attached .config to linux build tree make ARCH=i386 All warnings (new ones prefixed by >>): drivers/gpu//drm/i915/i915_guc_submission.c: In function 'guc_stage_desc_init': >> drivers/gpu//drm/i915/i915_guc_submission.c:391:25: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] desc->db_trigger_cpu = (u64)__get_doorbell(client); ^ drivers/gpu//drm/i915/i915_guc_submission.c:397:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] desc->desc_private = (u64)client; ^ vim +391 drivers/gpu//drm/i915/i915_guc_submission.c 313 314 /* 315 * Initialise/clear the stage descriptor shared with the GuC firmware. 316 * 317 * This descriptor tells the GuC where (in GGTT space) to find the important 318 * data structures relating to this client (doorbell, process descriptor, 319 * write queue, etc). 320 */ 321 static void guc_stage_desc_init(struct intel_guc *guc, 322 struct i915_guc_client *client) 323 { 324 struct drm_i915_private *dev_priv = guc_to_i915(guc); 325 struct intel_engine_cs *engine; 326 struct i915_gem_context *ctx = client->owner; 327 struct guc_stage_desc *desc; 328 unsigned int tmp; 329 u32 gfx_addr; 330 331 desc = __get_stage_desc(client); 332 memset(desc, 0, sizeof(*desc)); 333 334 desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE | GUC_STAGE_DESC_ATTR_KERNEL; 335 desc->stage_id = client->stage_id; 336 desc->priority = client->priority; 337 desc->db_id = client->doorbell_id; 338 339 for_each_engine_masked(engine, dev_priv, client->engines, tmp) { 340 struct intel_context *ce = &ctx->engine[engine->id]; 341 u32 guc_engine_id = engine->guc_id; 342 struct guc_execlist_context *lrc = &desc->lrc[guc_engine_id]; 343 344 /* TODO: We have a design issue to be solved here. Only when we 345 * receive the first batch, we know which engine is used by the 346 * user. But here GuC expects the lrc and ring to be pinned. It 347 * is not an issue for default context, which is the only one 348 * for now who owns a GuC client. But for future owner of GuC 349 * client, need to make sure lrc is pinned prior to enter here. 350 */ 351 if (!ce->state) 352 break; /* XXX: continue? */ 353 354 /* 355 * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy 356 * submission or, in other words, not using a direct submission 357 * model) the KMD's LRCA is not used for any work submission. 358 * Instead, the GuC uses the LRCA of the user mode context (see 359 * guc_wq_item_append below). 360 */ 361 lrc->context_desc = lower_32_bits(ce->lrc_desc); 362 363 /* The state page is after PPHWSP */ 364 lrc->ring_lrca = 365 guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE; 366 367 /* XXX: In direct submission, the GuC wants the HW context id 368 * here. In proxy submission, it wants the stage id */ 369 lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) | 370 (guc_engine_id << GUC_ELC_ENGINE_OFFSET); 371 372 lrc->ring_begin = guc_ggtt_offset(ce->ring->vma); 373 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1; 374 lrc->ring_next_free_location = lrc->ring_begin; 375 lrc->ring_current_tail_pointer_value = 0; 376 377 desc->engines_used |= (1 << guc_engine_id); 378 } 379 380 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n", 381 client->engines, desc->engines_used); 382 WARN_ON(desc->engines_used == 0); 383 384 /* 385 * The doorbell, process descriptor, and workqueue are all parts 386 * of the client object, which the GuC will reference via the GGTT 387 */ 388 gfx_addr = guc_ggtt_offset(client->vma); 389 desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) + 390 client->doorbell_offset; > 391 desc->db_trigger_cpu = (u64)__get_doorbell(client); 392 desc->db_trigger_uk = gfx_addr + client->doorbell_offset; 393 desc->process_desc = gfx_addr + client->proc_desc_offset; 394 desc->wq_addr = gfx_addr + GUC_DB_SIZE; 395 desc->wq_size = GUC_WQ_SIZE; 396 397 desc->desc_private = (u64)client; 398 } 399 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

1 0

[drm-intel:for-linux-next 2/2] drivers/gpu//drm/i915/i915_guc_submission.c:391:25: error: cast from pointer to integer of different size
by kbuild test robot 06 Oct '17

06 Oct '17

tree: git://anongit.freedesktop.org/drm-intel for-linux-next head: faf654864b25f4ca4efd416145d37b794c0b805f commit: faf654864b25f4ca4efd416145d37b794c0b805f [2/2] drm/i915: Unify uC variable types to avoid flooding checkpatch.pl config: i386-randconfig-x003-201740 (attached as .config) compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901 reproduce: git checkout faf654864b25f4ca4efd416145d37b794c0b805f # save the attached .config to linux build tree make ARCH=i386 All errors (new ones prefixed by >>): drivers/gpu//drm/i915/i915_guc_submission.c: In function 'guc_stage_desc_init': >> drivers/gpu//drm/i915/i915_guc_submission.c:391:25: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] desc->db_trigger_cpu = (u64)__get_doorbell(client); ^ drivers/gpu//drm/i915/i915_guc_submission.c:397:23: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] desc->desc_private = (u64)client; ^ cc1: all warnings being treated as errors vim +391 drivers/gpu//drm/i915/i915_guc_submission.c 313 314 /* 315 * Initialise/clear the stage descriptor shared with the GuC firmware. 316 * 317 * This descriptor tells the GuC where (in GGTT space) to find the important 318 * data structures relating to this client (doorbell, process descriptor, 319 * write queue, etc). 320 */ 321 static void guc_stage_desc_init(struct intel_guc *guc, 322 struct i915_guc_client *client) 323 { 324 struct drm_i915_private *dev_priv = guc_to_i915(guc); 325 struct intel_engine_cs *engine; 326 struct i915_gem_context *ctx = client->owner; 327 struct guc_stage_desc *desc; 328 unsigned int tmp; 329 u32 gfx_addr; 330 331 desc = __get_stage_desc(client); 332 memset(desc, 0, sizeof(*desc)); 333 334 desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE | GUC_STAGE_DESC_ATTR_KERNEL; 335 desc->stage_id = client->stage_id; 336 desc->priority = client->priority; 337 desc->db_id = client->doorbell_id; 338 339 for_each_engine_masked(engine, dev_priv, client->engines, tmp) { 340 struct intel_context *ce = &ctx->engine[engine->id]; 341 u32 guc_engine_id = engine->guc_id; 342 struct guc_execlist_context *lrc = &desc->lrc[guc_engine_id]; 343 344 /* TODO: We have a design issue to be solved here. Only when we 345 * receive the first batch, we know which engine is used by the 346 * user. But here GuC expects the lrc and ring to be pinned. It 347 * is not an issue for default context, which is the only one 348 * for now who owns a GuC client. But for future owner of GuC 349 * client, need to make sure lrc is pinned prior to enter here. 350 */ 351 if (!ce->state) 352 break; /* XXX: continue? */ 353 354 /* 355 * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy 356 * submission or, in other words, not using a direct submission 357 * model) the KMD's LRCA is not used for any work submission. 358 * Instead, the GuC uses the LRCA of the user mode context (see 359 * guc_wq_item_append below). 360 */ 361 lrc->context_desc = lower_32_bits(ce->lrc_desc); 362 363 /* The state page is after PPHWSP */ 364 lrc->ring_lrca = 365 guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE; 366 367 /* XXX: In direct submission, the GuC wants the HW context id 368 * here. In proxy submission, it wants the stage id */ 369 lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) | 370 (guc_engine_id << GUC_ELC_ENGINE_OFFSET); 371 372 lrc->ring_begin = guc_ggtt_offset(ce->ring->vma); 373 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1; 374 lrc->ring_next_free_location = lrc->ring_begin; 375 lrc->ring_current_tail_pointer_value = 0; 376 377 desc->engines_used |= (1 << guc_engine_id); 378 } 379 380 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n", 381 client->engines, desc->engines_used); 382 WARN_ON(desc->engines_used == 0); 383 384 /* 385 * The doorbell, process descriptor, and workqueue are all parts 386 * of the client object, which the GuC will reference via the GGTT 387 */ 388 gfx_addr = guc_ggtt_offset(client->vma); 389 desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) + 390 client->doorbell_offset; > 391 desc->db_trigger_cpu = (u64)__get_doorbell(client); 392 desc->db_trigger_uk = gfx_addr + client->doorbell_offset; 393 desc->process_desc = gfx_addr + client->proc_desc_offset; 394 desc->wq_addr = gfx_addr + GUC_DB_SIZE; 395 desc->wq_size = GUC_WQ_SIZE; 396 397 desc->desc_private = (u64)client; 398 } 399 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

1 0

[PATCH 1/2] drm/atomic: Remove unneeded null check for private objects
by Maarten Lankhorst 06 Oct '17

06 Oct '17

It can be seen in drm_atomic_get_private_obj_state() that ptr will never be NULL, so skip the check for that case. Signed-off-by: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> --- drivers/gpu/drm/drm_atomic.c | 3 --- include/drm/drm_atomic.h | 9 +++------ 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 8bd5a1c4c7e8..29525bffdad9 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -182,9 +182,6 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state) for (i = 0; i < state->num_private_objs; i++) { struct drm_private_obj *obj = state->private_objs[i].ptr; - if (!obj) - continue; - obj->funcs->atomic_destroy_state(obj, state->private_objs[i].state); state->private_objs[i].ptr = NULL; diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index 5834580d75bc..6fae95f28e10 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -768,8 +768,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); ((obj) = (__state)->private_objs[__i].ptr, \ (old_obj_state) = (__state)->private_objs[__i].old_state, \ (new_obj_state) = (__state)->private_objs[__i].new_state, 1); \ - (__i)++) \ - for_each_if (obj) + (__i)++) /** * for_each_old_private_obj_in_state - iterate over all private objects in an atomic update @@ -787,8 +786,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); (__i) < (__state)->num_private_objs && \ ((obj) = (__state)->private_objs[__i].ptr, \ (old_obj_state) = (__state)->private_objs[__i].old_state, 1); \ - (__i)++) \ - for_each_if (obj) + (__i)++) /** * for_each_new_private_obj_in_state - iterate over all private objects in an atomic update @@ -806,8 +804,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); (__i) < (__state)->num_private_objs && \ ((obj) = (__state)->private_objs[__i].ptr, \ (new_obj_state) = (__state)->private_objs[__i].new_state, 1); \ - (__i)++) \ - for_each_if (obj) + (__i)++) /** * drm_atomic_crtc_needs_modeset - compute combined modeset need -- 2.14.1

3 6

[PATCH v6 0/3] RPi touchscreen panel resend.
by Eric Anholt 06 Oct '17

06 Oct '17

I pushed a couple of the patches from the series, so here's what's left. I figured it was time for a resend at this point. Eric Anholt (3): drm/vc4: Move the DSI clock divider workaround closer to the clock call. dt-bindings: Document the Raspberry Pi Touchscreen nodes. drm/panel: Add support for the Raspberry Pi 7" Touchscreen. .../panel/raspberrypi,7inch-touchscreen.txt | 49 ++ drivers/gpu/drm/panel/Kconfig | 8 + drivers/gpu/drm/panel/Makefile | 1 + .../gpu/drm/panel/panel-raspberrypi-touchscreen.c | 517 +++++++++++++++++++++ drivers/gpu/drm/vc4/vc4_dsi.c | 12 +- 5 files changed, 581 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt create mode 100644 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c -- 2.14.1

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dri-devel October 2017