dri-devel January 2018

dri-devel@lists.freedesktop.org

226 participants
1677 discussions

[RFC 0/4] drm/msm: GPU crash state
by Jordan Crouse 05 Jan '18

05 Jan '18

This is a request for comment on code to store and dump a GPU state a hang with inspiration from the very good i915 GPU error state and the binary GPU snapshot in the downstream kernel. The goal is to store and provide enough information to debug software and hardware issues on the Adreno hardware in a semi human-readable format that can also be parsed by scripts. The goal for this request for comment is to get some consensus about the format and work through some of the technical issues. The first patch is a bit of a standalone - it finally consolidates the 'show' and 'dump' code (where show goes to a seq_file and 'dump' goes to the kernel log) through judicious use of drm_printer. The next patch captures the ringbuffer and register information the same way that 'show' does - most of the code is generic but eventually will get more platform specific as we add new chunks of data (especially for a5xx and beyond). The third patch converts the existing show function to use the state instead of reading the data directly. This gets a little big ugly because due to the first patch, if we don't capture a state here then nothing gets printed out. The final patch prints the crash state through its own debugfs node. Only one crash state is captured at a time and it persists until the state is cleared by a write to the debugfs node. After we mostly agree on the behavior and design of the code the next step will be to pull over more state for 5xx including ringbuffer contents, active commands and buffers, shader caches and other debug information. Jordan Crouse (4): drm/msm: gpu: Use drm_printer to consolidate the show/dump code drm/msm: gpu: Capture the state of the GPU drm/msm: gpu: Convert the GPU show functions to use the GPU state drm/msm: gpu: Capture the GPU state on a GPU hang drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 43 +++++----- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 39 ++++----- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 44 +++++----- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 138 +++++++++++++++++++------------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++- drivers/gpu/drm/msm/msm_debugfs.c | 78 ++++++++++++++++-- drivers/gpu/drm/msm/msm_gpu.h | 64 ++++++++++++++- 7 files changed, 296 insertions(+), 120 deletions(-) -- 1.9.1

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[PATCH v2] drm: clean up comments in drm_crtc.c
by Randy Dunlap 05 Jan '18

05 Jan '18

From: Randy Dunlap <rdunlap(a)infradead.org> Fix typos, punctuation, and one function reference (change atomic_check two times to be atomic_check and atomic_commit). Signed-off-by: Randy Dunlap <rdunlap(a)infradead.org> Cc: David Airlie <airlied(a)linux.ie> Cc: dri-devel(a)lists.freedesktop.org --- v2: s/instances/instance/ (thanks, Alex) I was looking for what CRTC means, but I still haven't found it. :( drivers/gpu/drm/drm_crtc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) --- lnx-415-rc6.orig/drivers/gpu/drm/drm_crtc.c +++ lnx-415-rc6/drivers/gpu/drm/drm_crtc.c @@ -55,16 +55,16 @@ * to one or more &drm_encoder, which are then each connected to one * &drm_connector. * - * To create a CRTC, a KMS drivers allocates and zeroes an instances of + * To create a CRTC, a KMS driver allocates and zeroes an instance of * &struct drm_crtc (possibly as part of a larger structure) and registers it * with a call to drm_crtc_init_with_planes(). * - * The CRTC is also the entry point for legacy modeset operations, see - * &drm_crtc_funcs.set_config, legacy plane operations, see - * &drm_crtc_funcs.page_flip and &drm_crtc_funcs.cursor_set2, and other legacy + * The CRTC is also the entry point for legacy modeset operations (see + * &drm_crtc_funcs.set_config), legacy plane operations (see + * &drm_crtc_funcs.page_flip and &drm_crtc_funcs.cursor_set2), and other legacy * operations like &drm_crtc_funcs.gamma_set. For atomic drivers all these * features are controlled through &drm_property and - * &drm_mode_config_funcs.atomic_check and &drm_mode_config_funcs.atomic_check. + * &drm_mode_config_funcs.atomic_check and &drm_mode_config_funcs.atomic_commit. */ /**

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[pull] amdgpu and ttm drm-next-4.16
by Alex Deucher 05 Jan '18

05 Jan '18

Hi Dave, Last few updates for 4.16: - Misc fixes for amdgpu - Enable swapout for reserved BOs during allocation for ttm - Misc cleanups for ttm The following changes since commit df2869abd92b740af141ee2eb081bfc69bd80877: Merge branch 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux into drm-next (2017-12-21 11:17:45 +1000) are available in the git repository at: git://people.freedesktop.org/~agd5f/linux drm-next-4.16 for you to fetch changes up to 104bd2ca1124dfd9aa904d5f5a96253ef2b580f6: drm/amdgpu: Correct the IB size of bo update mapping. (2017-12-30 22:24:20 -0500) ---------------------------------------------------------------- Christian König (5): drm/amdgpu: separate VMID and PASID handling drm/amdgpu: rename vm_id to vmid drm/amdgpu: drop client_id from VM drm/ttm: drop the spin in delayed delete if the trylock doesn't work drm/amdgpu: fix VM faults with per VM BOs Emily Deng (1): drm/amdgpu: Correct the IB size of bo update mapping. Rex Zhu (1): drm/amd/pp: Get and save CZ/ST smu version Roger He (7): drm/ttm: call ttm_bo_swapout directly when ttm shrink drm/ttm: use an operation ctx for ttm_mem_global_alloc drm/ttm: use an operation ctx for ttm_mem_global_alloc_page drm/ttm: use an operation ctx for ttm_tt_populate in ttm_bo_driver (v2) drm/ttm: use an operation ctx for ttm_tt_bind drm/ttm: add new function to check if bo is allowable to evict or swapout drm/ttm: enable swapout for reserved BOs during allocation Tan Xiaojun (10): drm/ttm: add ttm_bo_io_mem_pfn to check io_mem_pfn drm/ast: remove the default io_mem_pfn set drm/bochs: remove the default io_mem_pfn set drm/cirrus: remove the default io_mem_pfn set drm/mgag200: remove the default io_mem_pfn set drm/nouveau: remove the default io_mem_pfn set drm/qxl: remove the default io_mem_pfn set drm/radeon: remove the default io_mem_pfn set drm/virtio: remove the default io_mem_pfn set drm/vmwgfx: remove the default io_mem_pfn set drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 459 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 91 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 28 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 468 +++------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 48 +-- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 14 +- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 14 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 18 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 18 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 18 +- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16 +- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 16 +- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 16 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 18 +- drivers/gpu/drm/amd/amdgpu/si_dma.c | 16 +- drivers/gpu/drm/amd/amdgpu/si_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 26 +- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 36 +- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 18 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 36 +- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 +- drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 13 + drivers/gpu/drm/ast/ast_ttm.c | 6 +- drivers/gpu/drm/bochs/bochs_mm.c | 1 - drivers/gpu/drm/cirrus/cirrus_ttm.c | 6 +- drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c | 5 +- drivers/gpu/drm/mgag200/mgag200_ttm.c | 6 +- drivers/gpu/drm/nouveau/nouveau_bo.c | 11 +- drivers/gpu/drm/qxl/qxl_ttm.c | 6 +- drivers/gpu/drm/radeon/radeon_ttm.c | 12 +- drivers/gpu/drm/ttm/ttm_agp_backend.c | 4 +- drivers/gpu/drm/ttm/ttm_bo.c | 78 ++-- drivers/gpu/drm/ttm/ttm_bo_util.c | 13 +- drivers/gpu/drm/ttm/ttm_bo_vm.c | 20 +- drivers/gpu/drm/ttm/ttm_memory.c | 37 +- drivers/gpu/drm/ttm/ttm_object.c | 13 +- drivers/gpu/drm/ttm/ttm_page_alloc.c | 9 +- drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 7 +- drivers/gpu/drm/ttm/ttm_tt.c | 5 +- drivers/gpu/drm/virtio/virtgpu_object.c | 6 +- drivers/gpu/drm/virtio/virtgpu_ttm.c | 6 +- drivers/gpu/drm/vmwgfx/vmwgfx_binding.c | 6 +- drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c | 17 +- drivers/gpu/drm/vmwgfx/vmwgfx_context.c | 6 +- drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c | 6 +- drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 6 +- drivers/gpu/drm/vmwgfx/vmwgfx_mob.c | 13 +- drivers/gpu/drm/vmwgfx/vmwgfx_shader.c | 18 +- drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c | 6 +- drivers/gpu/drm/vmwgfx/vmwgfx_so.c | 6 +- drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 12 +- drivers/staging/vboxvideo/vbox_ttm.c | 5 +- include/drm/ttm/ttm_bo_api.h | 2 + include/drm/ttm/ttm_bo_driver.h | 9 +- include/drm/ttm/ttm_memory.h | 75 +--- include/drm/ttm/ttm_page_alloc.h | 11 +- 78 files changed, 1057 insertions(+), 870 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h

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[PATCH 1/3] drm/amdgpu: allow framebuffer in GART memory as well
by Samuel Li 05 Jan '18

05 Jan '18

From: Christian König <christian.koenig(a)amd.com> On CZ and newer APUs we can pin the fb into GART as well as VRAM. v2: Don't enable gpu_vm_support for Raven yet since it leads to a black screen. Need to debug this further before enabling. Change-Id: Id0f8af3110e54a3aabf7a258871867bc121cc1a2 Signed-off-by: Christian König <christian.koenig(a)amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky(a)amd.com> Acked-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Samuel Li <samuel.li(a)amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 10 ++++++---- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++++-- 4 files changed, 29 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index d704a45..d9fdc19 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -29,6 +29,7 @@ #include "amdgpu_i2c.h" #include "atom.h" #include "amdgpu_connectors.h" +#include "amdgpu_display.h" #include <asm/div64.h> #include <linux/pm_runtime.h> @@ -188,7 +189,7 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc, goto cleanup; } - r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM, &base); + r = amdgpu_bo_pin(new_abo, amdgpu_framebuffer_domains(adev), &base); if (unlikely(r != 0)) { DRM_ERROR("failed to pin new abo buffer before flip\n"); goto unreserve; @@ -501,6 +502,17 @@ static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { .create_handle = amdgpu_user_framebuffer_create_handle, }; +uint32_t amdgpu_framebuffer_domains(struct amdgpu_device *adev) +{ + uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; + + if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && + adev->flags & AMD_IS_APU) + domain |= AMDGPU_GEM_DOMAIN_GTT; + + return domain; +} + int amdgpu_framebuffer_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 11ae4ab..f241949 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -23,6 +23,7 @@ #ifndef __AMDGPU_DISPLAY_H__ #define __AMDGPU_DISPLAY_H__ +uint32_t amdgpu_framebuffer_domains(struct amdgpu_device *adev); struct drm_framebuffer * amdgpu_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 90fa8e8..9be3228 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -38,6 +38,8 @@ #include <linux/vga_switcheroo.h> +#include "amdgpu_display.h" + /* object hierarchy - this contains a helper + a amdgpu fb the helper contains a pointer to amdgpu framebuffer baseclass. @@ -124,7 +126,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, struct drm_gem_object *gobj = NULL; struct amdgpu_bo *abo = NULL; bool fb_tiled = false; /* useful for testing */ - u32 tiling_flags = 0; + u32 tiling_flags = 0, domain; int ret; int aligned_size, size; int height = mode_cmd->height; @@ -135,12 +137,12 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, /* need to align pitch with crtc limits */ mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, fb_tiled); + domain = amdgpu_framebuffer_domains(adev); height = ALIGN(mode_cmd->height, 8); size = mode_cmd->pitches[0] * height; aligned_size = ALIGN(size, PAGE_SIZE); - ret = amdgpu_gem_object_create(adev, aligned_size, 0, - AMDGPU_GEM_DOMAIN_VRAM, + ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | AMDGPU_GEM_CREATE_VRAM_CLEARED, @@ -166,7 +168,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, } - ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL); + ret = amdgpu_bo_pin(abo, domain, NULL); if (ret) { amdgpu_bo_unreserve(abo); goto out_unref; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a3bf021..9b05abd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2982,11 +2982,13 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, { struct amdgpu_framebuffer *afb; struct drm_gem_object *obj; + struct amdgpu_device *adev; struct amdgpu_bo *rbo; uint64_t chroma_addr = 0; - int r; struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; unsigned int awidth; + uint32_t domain; + int r; dm_plane_state_old = to_dm_plane_state(plane->state); dm_plane_state_new = to_dm_plane_state(new_state); @@ -3000,12 +3002,17 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, obj = afb->obj; rbo = gem_to_amdgpu_bo(obj); + adev = amdgpu_ttm_adev(rbo->tbo.bdev); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r != 0)) return r; - r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address); + if (plane->type != DRM_PLANE_TYPE_CURSOR) + domain = amdgpu_framebuffer_domains(adev); + else + domain = AMDGPU_GEM_DOMAIN_VRAM; + r = amdgpu_bo_pin(rbo, domain, &afb->address); amdgpu_bo_unreserve(rbo); -- 2.7.4

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[PATCH v2 0/3] drm/omap: Make omapdss API more generic + related patches
by Jyri Sarha 05 Jan '18

05 Jan '18

This the v2 rouns of a this RFC patch: https://patchwork.kernel.org/patch/10066245/ The first patch is a simple fix that should be applied in any case. I did not split the mgr_has_framedone() callback as a separate patch. It quite literally replaces the mgr_get_framedone_irq() and makes no sense without the "drm/omap: Make omapdss API more generic"-patch. The patches have been rebased on top of the latest drm-next (350877626faba5d60cbb8cef2bdeb524212c780b). Best regards, Jyri Jyri Sarha (3): drm/omap: Fail probe if irq registration fails drm/omap: Add get_ovl_name() and get_mgr_name() to dispc_ops drm/omap: Make omapdss API more generic drivers/gpu/drm/omapdrm/dss/dispc.c | 159 +++++++++++++++++++++++++++++----- drivers/gpu/drm/omapdrm/dss/dispc.h | 33 +++++++ drivers/gpu/drm/omapdrm/dss/omapdss.h | 67 +++++++------- drivers/gpu/drm/omapdrm/omap_crtc.c | 27 +++--- drivers/gpu/drm/omapdrm/omap_crtc.h | 2 +- drivers/gpu/drm/omapdrm/omap_drv.c | 4 +- drivers/gpu/drm/omapdrm/omap_drv.h | 3 +- drivers/gpu/drm/omapdrm/omap_irq.c | 141 ++++++++++++++---------------- drivers/gpu/drm/omapdrm/omap_irq.h | 2 +- drivers/gpu/drm/omapdrm/omap_plane.c | 18 ++-- drivers/gpu/drm/omapdrm/omap_plane.h | 1 + 11 files changed, 292 insertions(+), 165 deletions(-) -- 1.9.1 Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

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[PATCH v2 0/3] drm/sun4i: hdmi: Fix sun4i_tmds_determine_rate
by Jonathan Liu 05 Jan '18

05 Jan '18

This patchset fixes several issues in sun4i_tmds_determine_rate that I discovered while trying to get a projector connected to an Olimex A20-OLinuXino-LIME using HDMI with a native resolution of 1280x800 and pixel clock of 83.5 MHz to display at its native resolution. Changes for v2: - Split into separate patches for each issue - Add details to commit message for reproducing issue Jonathan Liu (3): drm/sun4i: hdmi: Check for unset best_parent in sun4i_tmds_determine_rate drm/sun4i: hdmi: Fix incorrect assignment in sun4i_tmds_determine_rate drm/sun4i: hdmi: Add missing rate halving check in sun4i_tmds_determine_rate drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.15.0

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[PATCH v3] drm/omap: plane zpos/zorder management improvements
by Peter Ujfalusi 05 Jan '18

05 Jan '18

Use the plane index as default zpos for all planes. Even if the application is not setting zpos/zorder explicitly we will have unique zpos for each plane. Enforce that all planes must have unique zpos on the given crtc. Signed-off-by: Peter Ujfalusi <peter.ujfalusi(a)ti.com> --- Hi, Changes since v2: - The check for duplicate zpos is moved to omap_crtc Changes since v1: - Dropped the zpos normalization related patches - New patch based on the discussion, see commit message. Regards, Peter drivers/gpu/drm/omapdrm/omap_crtc.c | 24 +++++++++++++++++++++++- drivers/gpu/drm/omapdrm/omap_plane.c | 10 +++++----- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 1b8154e58d18..ff0b17f8bb76 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -486,6 +486,28 @@ static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc) } } +static int omap_crtc_validate_zpos(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct drm_plane *p1, *p2; + const struct drm_plane_state *pstate1, *pstate2; + + drm_atomic_crtc_state_for_each_plane_state(p1, pstate1, state) { + drm_atomic_crtc_state_for_each_plane_state(p2, pstate2, state) { + if (drm_plane_index(p1) == drm_plane_index(p2)) + continue; + + if (pstate1->zpos == pstate2->zpos) { + DBG("crtc%u: zpos must be unique (zpos: %u)", + crtc->index, pstate1->zpos); + return -EINVAL; + } + } + } + + return 0; +} + static int omap_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { @@ -509,7 +531,7 @@ static int omap_crtc_atomic_check(struct drm_crtc *crtc, omap_crtc_state->rotation = pri_state->rotation; } - return 0; + return omap_crtc_validate_zpos(crtc, state); } static void omap_crtc_atomic_begin(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 7d789d1551a1..c1f93bfae7a5 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -31,6 +31,7 @@ struct omap_plane { struct drm_plane base; enum omap_plane_id id; + int idx; const char *name; }; @@ -97,8 +98,7 @@ static void omap_plane_atomic_disable(struct drm_plane *plane, struct omap_plane *omap_plane = to_omap_plane(plane); plane->state->rotation = DRM_MODE_ROTATE_0; - plane->state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY - ? 0 : omap_plane->id; + plane->state->zpos = omap_plane->idx; priv->dispc_ops->ovl_enable(omap_plane->id, false); } @@ -194,8 +194,7 @@ static void omap_plane_reset(struct drm_plane *plane) * Set the zpos default depending on whether we are a primary or overlay * plane. */ - plane->state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY - ? 0 : omap_plane->id; + plane->state->zpos = omap_plane->idx; } static int omap_plane_atomic_set_property(struct drm_plane *plane, @@ -282,6 +281,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, for (nformats = 0; formats[nformats]; ++nformats) ; omap_plane->id = id; + omap_plane->idx = idx; omap_plane->name = plane_id_to_name[id]; plane = &omap_plane->base; @@ -295,7 +295,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, drm_plane_helper_add(plane, &omap_plane_helper_funcs); omap_plane_install_properties(plane, &plane->base); - drm_plane_create_zpos_property(plane, 0, 0, num_planes - 1); + drm_plane_create_zpos_property(plane, idx, 0, num_planes - 1); return plane; -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

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[PATCH v5 00/12] drm/sun4i: Add A83t LVDS support
by Maxime Ripard 05 Jan '18

05 Jan '18

Hi, Here is an attempt at supporting the LVDS output in our DRM driver. This has been tested on the A83T (with DE2), but since everything is basically in the TCON, it should also be usable on the older SoCs with minor modifications. This was the occasion to refactor a bunch of things. The most notable ones would be the documentation, and split of the UI layers in the mixer code, and the switch to kfifo for our endpoint parsing code in the driver that fixes an issue introduced by the switch to BFS. Let me know what you think, Maxime Changes from v4: - Changed the order of the clk_prepare_enable and clk_set_rate for the mixer module clock - Squash the two DT PWM patches - Removed the output pins muxing - Changed the flag to tell if you have an LVDS alternate clock to has_lvds_alt - Used SPDX headers Changes from v3: - Collect the tags - Use SPDX headers when possible - Added the new mixer configuration options - Changed the LVDS clock for lvds-alt instead of lvds-pll - Removed the MIPI PLL from the A31s - Changed the LVDS_ANA0 macros name to reflect the generation they were introduced in, and added a comment to mention the changes needed to support the older SoCs Changes from v2: - Move the module clock rate to the mixer structure - Adjusted the simple-panel documentation for power-supply - Changed the compatible for the first A83t mixer to mixer 0 - Rebased on top of current drm-misc - Split out the A83t bindings in its separate patch Changes from v1: - Added a fix for the error path handling in the TCON - Enable the TCON by default - Removed the patch that changes the channels offset but kept most of the modifications as a cleanup - Deal with the LVDS clock being able to have another PLL parent on some SoCs - Renamed the TCON compatible to TCON-TV, following the convention used on newer SoCs - Removed the hardcoded timings - Moved LVDS enable quirks to a separate function - Used clock indices define in the DT - Removed the hardcoded clock rate in the DT and moved it to the driver - Changed sun8i_mixer_planes to sun8i_mixer_ui_planes to be consistent - Added the various tags collected - Rebased on top of 4.15 Maxime Ripard (12): dt-bindings: panel: lvds: Document power-supply property drm/panel: lvds: Add support for the power-supply property dt-bindings: display: sun4i-drm: Add LVDS properties dt-bindings: display: sun4i-drm: Add A83T pipeline drm/sun4i: Force the mixer rate at 150MHz drm/sun4i: Create minimal multipliers and dividers drm/sun4i: Add LVDS support drm/sun4i: Add A83T support ARM: dts: sun8i: a83t: Add display pipeline ARM: dts: sun8i: a83t: Enable the PWM ARM: dts: sun8i: a83t: Add LVDS pins group ARM: dts: sun8i: a711: Enable the LCD Documentation/devicetree/bindings/display/panel/panel-common.txt | 6 ++- Documentation/devicetree/bindings/display/panel/panel-lvds.txt | 1 +- Documentation/devicetree/bindings/display/panel/simple-panel.txt | 2 +- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 12 ++++- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 61 ++++++++++++++++++- arch/arm/boot/dts/sun8i-a83t.dtsi | 99 +++++++++++++++++++++++++++++- drivers/gpu/drm/panel/panel-lvds.c | 23 +++++++- drivers/gpu/drm/sun4i/Makefile | 1 +- drivers/gpu/drm/sun4i/sun4i_dotclock.c | 10 ++- drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +- drivers/gpu/drm/sun4i/sun4i_lvds.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/sun4i/sun4i_lvds.h | 12 ++++- drivers/gpu/drm/sun4i/sun4i_tcon.c | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/sun4i/sun4i_tcon.h | 31 +++++++++- drivers/gpu/drm/sun4i/sun8i_mixer.c | 21 ++++++- drivers/gpu/drm/sun4i/sun8i_mixer.h | 3 +- 16 files changed, 699 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/sun4i/sun4i_lvds.c create mode 100644 drivers/gpu/drm/sun4i/sun4i_lvds.h base-commit: 99239c7ba0214ec99011378a6ca1bcd589c3dc98 -- git-series 0.9.1

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[Bug 104490] [radeonsi/290x] Dota2 fails to start (can't create opengl context)
by bugzilla-daemon＠freedesktop.org 05 Jan '18

05 Jan '18

https://bugs.freedesktop.org/show_bug.cgi?id=104490 Bug ID: 104490 Summary: [radeonsi/290x] Dota2 fails to start (can't create opengl context) Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/Gallium/radeonsi Assignee: dri-devel(a)lists.freedesktop.org Reporter: darkdefende(a)gmail.com QA Contact: dri-devel(a)lists.freedesktop.org Created attachment 136546 --> https://bugs.freedesktop.org/attachment.cgi?id=136546&action=edit glxinfo I've been trying to figure out the cause for this bug for quite some time now. Here is the bug ticket on the dota2 github page: https://github.com/ValveSoftware/Dota-2/issues/1368 Since about one week ago, I have been unable to start dota2 on my machine. This happened after I updated my llvm and mesa git version. If I downgrade to mesa 17.3.1 it works again (without reboot). But it seems to be really hard to track down the commit that broke it as there seems to be some kind of cached behaviour (not the mesa shader cache as I removed the directory and rebooted several times). For example I downgraded mesa to a commit from 2017-11-17 and it worked. The next day I tried to figure out the commit that broke it. But I could then use the git master version and it seemed to work fine again. Then the next day I'm back to the same problem and I downgraded again and now it won't start again even if I use mesa from 11-17 (and rebooted). But 17.3.1 still works if I downgrade to that... (no reboot) I really do not know how to debug this further as I don't know when I'm on the commit that broke it or not. However it seems to always break if I'm on a commit that is newer than 1-2 weeks (after a reboot that is). However it will not fix itself with reboots with commits older than that either... -- You are receiving this mail because: You are the assignee for the bug.

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[gabbayo:amdkfd-next 10/53] drivers/gpu/drm/amd/amdkfd/kfd_process.c:289:37: sparse: constant 0x2000000000000 is so big it is long
by kbuild test robot 05 Jan '18

05 Jan '18

tree: git://people.freedesktop.org/~gabbayo/linux amdkfd-next head: 9f0a0b41ffccf9a76b19ea263ae16d2d5888093e commit: 373d7080896a3cb3b28ae3a2abdafb7bb87552b1 [10/53] drm/amdkfd: Add CWSR support reproduce: # apt-get install sparse git checkout 373d7080896a3cb3b28ae3a2abdafb7bb87552b1 make ARCH=x86_64 allmodconfig make C=1 CF=-D__CHECK_ENDIAN__ sparse warnings: (new ones prefixed by >>) vim +289 drivers/gpu/drm/amd/amdkfd/kfd_process.c 273 274 static int kfd_process_init_cwsr(struct kfd_process *p, struct file *filep) 275 { 276 int err = 0; 277 unsigned long offset; 278 struct kfd_process_device *temp, *pdd = NULL; 279 struct kfd_dev *dev = NULL; 280 struct qcm_process_device *qpd = NULL; 281 282 mutex_lock(&p->mutex); 283 list_for_each_entry_safe(pdd, temp, &p->per_device_data, 284 per_device_list) { 285 dev = pdd->dev; 286 qpd = &pdd->qpd; 287 if (!dev->cwsr_enabled || qpd->cwsr_kaddr) 288 continue; > 289 offset = (dev->id | KFD_MMAP_RESERVED_MEM_MASK) << PAGE_SHIFT; 290 qpd->tba_addr = (int64_t)vm_mmap(filep, 0, 291 KFD_CWSR_TBA_TMA_SIZE, PROT_READ | PROT_EXEC, 292 MAP_SHARED, offset); 293 294 if (IS_ERR_VALUE(qpd->tba_addr)) { 295 pr_err("Failure to set tba address. error -%d.\n", 296 (int)qpd->tba_addr); 297 err = qpd->tba_addr; 298 qpd->tba_addr = 0; 299 qpd->cwsr_kaddr = NULL; 300 goto out; 301 } 302 303 memcpy(qpd->cwsr_kaddr, dev->cwsr_isa, dev->cwsr_isa_size); 304 305 qpd->tma_addr = qpd->tba_addr + KFD_CWSR_TMA_OFFSET; 306 pr_debug("set tba :0x%llx, tma:0x%llx, cwsr_kaddr:%p for pqm.\n", 307 qpd->tba_addr, qpd->tma_addr, qpd->cwsr_kaddr); 308 } 309 out: 310 mutex_unlock(&p->mutex); 311 return err; 312 } 313 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

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dri-devel January 2018