dri-devel January 2018

dri-devel@lists.freedesktop.org

226 participants
1677 discussions

[PATCH v2] drm/omap: plane zpos/zorder management improvements
by Peter Ujfalusi 04 Jan '18

04 Jan '18

Use the plane index as default zpos for all planes. Even if the application is not setting zpos/zorder explicitly we will have unique zpos for each plane. Enforce that all planes must have unique zpos by refusing atomic update for planes with already used zpos. Signed-off-by: Peter Ujfalusi <peter.ujfalusi(a)ti.com> --- Hi, changes since v1: - Dropped the zpos normalization related patches - New patch based on the discussion, see commit message. Regards, Peter drivers/gpu/drm/omapdrm/omap_plane.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 15e5d5d325c6..6aeda3cc2f8b 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -33,6 +33,7 @@ struct omap_plane { struct drm_plane base; enum omap_plane_id id; + int idx; const char *name; }; @@ -99,8 +100,7 @@ static void omap_plane_atomic_disable(struct drm_plane *plane, struct omap_plane *omap_plane = to_omap_plane(plane); plane->state->rotation = DRM_MODE_ROTATE_0; - plane->state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY - ? 0 : omap_plane->id; + plane->state->zpos = omap_plane->idx; priv->dispc_ops->ovl_enable(omap_plane->id, false); } @@ -109,15 +109,17 @@ static int omap_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { struct drm_crtc_state *crtc_state; + struct drm_crtc *crtc = state->crtc; + struct drm_plane *p; if (!state->fb) return 0; /* crtc should only be NULL when disabling (i.e., !state->fb) */ - if (WARN_ON(!state->crtc)) + if (WARN_ON(!crtc)) return 0; - crtc_state = drm_atomic_get_existing_crtc_state(state->state, state->crtc); + crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); /* we should have a crtc state if the plane is attached to a crtc */ if (WARN_ON(!crtc_state)) return 0; @@ -125,6 +127,16 @@ static int omap_plane_atomic_check(struct drm_plane *plane, if (!crtc_state->enable) return 0; + drm_for_each_plane_mask(p, crtc->dev, crtc->state->plane_mask) { + if (plane->base.id == p->base.id) + continue; + + if (p->state->zpos == state->zpos) { + DBG("zpos must be unique (zpos: %u)", state->zpos); + return -EINVAL; + } + } + if (state->crtc_x < 0 || state->crtc_y < 0) return -EINVAL; @@ -196,8 +208,7 @@ static void omap_plane_reset(struct drm_plane *plane) * Set the zpos default depending on whether we are a primary or overlay * plane. */ - plane->state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY - ? 0 : omap_plane->id; + plane->state->zpos = omap_plane->idx; } static int omap_plane_atomic_set_property(struct drm_plane *plane, @@ -284,6 +295,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, for (nformats = 0; formats[nformats]; ++nformats) ; omap_plane->id = id; + omap_plane->idx = idx; omap_plane->name = plane_id_to_name[id]; plane = &omap_plane->base; @@ -297,7 +309,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, drm_plane_helper_add(plane, &omap_plane_helper_funcs); omap_plane_install_properties(plane, &plane->base); - drm_plane_create_zpos_property(plane, 0, 0, num_planes - 1); + drm_plane_create_zpos_property(plane, idx, 0, num_planes - 1); return plane; -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

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[Bug 104216] Firefox quirks (black and/or white squares)
by bugzilla-daemon＠freedesktop.org 04 Jan '18

04 Jan '18

https://bugs.freedesktop.org/show_bug.cgi?id=104216 --- Comment #6 from Marek Olšák <maraeo(a)gmail.com> --- Have you tested the patch you linked? -- You are receiving this mail because: You are the assignee for the bug.

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[Bug 104216] Firefox quirks (black and/or white squares)
by bugzilla-daemon＠freedesktop.org 04 Jan '18

04 Jan '18

https://bugs.freedesktop.org/show_bug.cgi?id=104216 --- Comment #5 from Marek Olšák <maraeo(a)gmail.com> --- The patch is not for Intel only. It's for all Mesa drivers. -- You are receiving this mail because: You are the assignee for the bug.

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[PATCH] drm/vc4: Move IRQ enable to PM path
by Stefan Schake 04 Jan '18

04 Jan '18

We were calling enable_irq on bind, where it was already enabled previously by the IRQ helper. Additionally, dev->irq is not set correctly until after postinstall and so was always zero here, triggering a warning in 4.15. Fix both by moving the enable to the power management resume path, where we know there was a previous disable invocation during suspend. Fixes: 253696ccd613 ("drm/vc4: Account for interrupts in flight") Signed-off-by: Stefan Schake <stschake(a)gmail.com> --- I tested replacing the enable/disable dance with just synchronize_irq, but that only made the original kernel OOPS more sporadic. drivers/gpu/drm/vc4/vc4_irq.c | 3 --- drivers/gpu/drm/vc4/vc4_v3d.c | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_irq.c b/drivers/gpu/drm/vc4/vc4_irq.c index 26eddbb..3dd62d7 100644 --- a/drivers/gpu/drm/vc4/vc4_irq.c +++ b/drivers/gpu/drm/vc4/vc4_irq.c @@ -209,9 +209,6 @@ { struct vc4_dev *vc4 = to_vc4_dev(dev); - /* Undo the effects of a previous vc4_irq_uninstall. */ - enable_irq(dev->irq); - /* Enable both the render done and out of memory interrupts. */ V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS); diff --git a/drivers/gpu/drm/vc4/vc4_v3d.c b/drivers/gpu/drm/vc4/vc4_v3d.c index 622cd43..493f392b 100644 --- a/drivers/gpu/drm/vc4/vc4_v3d.c +++ b/drivers/gpu/drm/vc4/vc4_v3d.c @@ -327,6 +327,9 @@ static int vc4_v3d_runtime_resume(struct device *dev) return ret; vc4_v3d_init_hw(vc4->dev); + + /* We disabled the IRQ as part of vc4_irq_uninstall in suspend. */ + enable_irq(vc4->dev->irq); vc4_irq_postinstall(vc4->dev); return 0; -- 1.9.1

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[radeon-alex:amd-staging-drm-next 875/881] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:55: note: in expansion of macro 'TEMP_RANGE_MAX'
by kbuild test robot 03 Jan '18

03 Jan '18

tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next head: b52e33cc86142a1143ed41806d9caf631cf16b21 commit: d78fd342a085cbce6b7919651d1005e44dc0d973 [875/881] drm/amd/powerplay: remove unused parameter of phm_start_thermal_controller config: x86_64-allmodconfig (attached as .config) compiler: gcc-7 (Debian 7.2.0-12) 7.2.1 20171025 reproduce: git checkout d78fd342a085cbce6b7919651d1005e44dc0d973 # save the attached .config to linux build tree make ARCH=x86_64 All warnings (new ones prefixed by >>): drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:45: sparse: bogus scalar initializer drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c: In function 'phm_start_thermal_controller': >> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:9: warning: braces around scalar initializer struct PP_TemperatureRange range = {{TEMP_RANGE_MIN, TEMP_RANGE_MAX}}; ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:9: note: (near initialization for 'range.min') >> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:31:24: warning: excess elements in scalar initializer #define TEMP_RANGE_MAX (80 * 1000) ^ >> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:55: note: in expansion of macro 'TEMP_RANGE_MAX' struct PP_TemperatureRange range = {{TEMP_RANGE_MIN, TEMP_RANGE_MAX}}; ^~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:31:24: note: (near initialization for 'range.min') #define TEMP_RANGE_MAX (80 * 1000) ^ >> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:55: note: in expansion of macro 'TEMP_RANGE_MAX' struct PP_TemperatureRange range = {{TEMP_RANGE_MIN, TEMP_RANGE_MAX}}; ^~~~~~~~~~~~~~ sparse warnings: (new ones prefixed by >>) vim +/TEMP_RANGE_MAX +230 drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c 28 29 30 #define TEMP_RANGE_MIN (0) > 31 #define TEMP_RANGE_MAX (80 * 1000) 32 33 #define PHM_FUNC_CHECK(hw) \ 34 do { \ 35 if ((hw) == NULL || (hw)->hwmgr_func == NULL) \ 36 return -EINVAL; \ 37 } while (0) 38 39 int phm_setup_asic(struct pp_hwmgr *hwmgr) 40 { 41 PHM_FUNC_CHECK(hwmgr); 42 43 if (NULL != hwmgr->hwmgr_func->asic_setup) 44 return hwmgr->hwmgr_func->asic_setup(hwmgr); 45 46 return 0; 47 } 48 49 int phm_power_down_asic(struct pp_hwmgr *hwmgr) 50 { 51 PHM_FUNC_CHECK(hwmgr); 52 53 if (NULL != hwmgr->hwmgr_func->power_off_asic) 54 return hwmgr->hwmgr_func->power_off_asic(hwmgr); 55 56 return 0; 57 } 58 59 int phm_set_power_state(struct pp_hwmgr *hwmgr, 60 const struct pp_hw_power_state *pcurrent_state, 61 const struct pp_hw_power_state *pnew_power_state) 62 { 63 struct phm_set_power_state_input states; 64 65 PHM_FUNC_CHECK(hwmgr); 66 67 states.pcurrent_state = pcurrent_state; 68 states.pnew_state = pnew_power_state; 69 70 if (NULL != hwmgr->hwmgr_func->power_state_set) 71 return hwmgr->hwmgr_func->power_state_set(hwmgr, &states); 72 73 return 0; 74 } 75 76 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) 77 { 78 int ret = 1; 79 bool enabled; 80 PHM_FUNC_CHECK(hwmgr); 81 82 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) 83 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); 84 85 enabled = ret == 0; 86 87 cgs_notify_dpm_enabled(hwmgr->device, enabled); 88 89 return ret; 90 } 91 92 int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr) 93 { 94 int ret = -1; 95 bool enabled; 96 97 PHM_FUNC_CHECK(hwmgr); 98 99 if (hwmgr->hwmgr_func->dynamic_state_management_disable) 100 ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); 101 102 enabled = ret == 0 ? false : true; 103 104 cgs_notify_dpm_enabled(hwmgr->device, enabled); 105 106 return ret; 107 } 108 109 int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level) 110 { 111 int ret = 0; 112 113 PHM_FUNC_CHECK(hwmgr); 114 115 if (hwmgr->hwmgr_func->force_dpm_level != NULL) 116 ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); 117 118 return ret; 119 } 120 121 int phm_reset_power_profile_state(struct pp_hwmgr *hwmgr) 122 { 123 int ret = 0; 124 125 if (hwmgr->hwmgr_func->set_power_profile_state) { 126 if (hwmgr->current_power_profile == AMD_PP_GFX_PROFILE) 127 ret = hwmgr->hwmgr_func->set_power_profile_state( 128 hwmgr, 129 &hwmgr->gfx_power_profile); 130 else if (hwmgr->current_power_profile == AMD_PP_COMPUTE_PROFILE) 131 ret = hwmgr->hwmgr_func->set_power_profile_state( 132 hwmgr, 133 &hwmgr->compute_power_profile); 134 } 135 return ret; 136 } 137 138 int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 139 struct pp_power_state *adjusted_ps, 140 const struct pp_power_state *current_ps) 141 { 142 PHM_FUNC_CHECK(hwmgr); 143 144 if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL) 145 return hwmgr->hwmgr_func->apply_state_adjust_rules( 146 hwmgr, 147 adjusted_ps, 148 current_ps); 149 return 0; 150 } 151 152 int phm_powerdown_uvd(struct pp_hwmgr *hwmgr) 153 { 154 PHM_FUNC_CHECK(hwmgr); 155 156 if (hwmgr->hwmgr_func->powerdown_uvd != NULL) 157 return hwmgr->hwmgr_func->powerdown_uvd(hwmgr); 158 return 0; 159 } 160 161 int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr) 162 { 163 PHM_FUNC_CHECK(hwmgr); 164 165 if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating) 166 return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr); 167 168 return 0; 169 } 170 171 int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr) 172 { 173 PHM_FUNC_CHECK(hwmgr); 174 175 if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) 176 return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); 177 178 return 0; 179 } 180 181 182 int phm_display_configuration_changed(struct pp_hwmgr *hwmgr) 183 { 184 PHM_FUNC_CHECK(hwmgr); 185 186 if (NULL != hwmgr->hwmgr_func->display_config_changed) 187 hwmgr->hwmgr_func->display_config_changed(hwmgr); 188 189 return 0; 190 } 191 192 int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) 193 { 194 PHM_FUNC_CHECK(hwmgr); 195 196 if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment) 197 hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr); 198 199 return 0; 200 } 201 202 int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr) 203 { 204 PHM_FUNC_CHECK(hwmgr); 205 206 if (hwmgr->hwmgr_func->stop_thermal_controller == NULL) 207 return -EINVAL; 208 209 return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr); 210 } 211 212 int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info) 213 { 214 PHM_FUNC_CHECK(hwmgr); 215 216 if (hwmgr->hwmgr_func->register_internal_thermal_interrupt != NULL) 217 return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info); 218 219 return 0; 220 } 221 222 /** 223 * Initializes the thermal controller subsystem. 224 * 225 * @param pHwMgr the address of the powerplay hardware manager. 226 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher. 227 */ 228 int phm_start_thermal_controller(struct pp_hwmgr *hwmgr) 229 { > 230 struct PP_TemperatureRange range = {{TEMP_RANGE_MIN, TEMP_RANGE_MAX}}; 231 232 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 233 PHM_PlatformCaps_ThermalController) 234 && hwmgr->hwmgr_func->start_thermal_controller != NULL) 235 return hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range); 236 237 return 0; 238 } 239 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

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[GIT PULL] etnaviv-next for 4.16
by Lucas Stach 03 Jan '18

03 Jan '18

Hi Dave, sorry for getting this to you a bit late, but things didn't align before the holidays. As 4.15 seems to go to -rc8 I hope we are still in time to land this. Highlights this time: 1. Fix for a nasty Kconfig dependency chain issue from Philipp. 2. Occlusion query buffer address added to the cmdstream validator by Christian. 3. Fixes and cleanups to the job handling from me. This allows us to turn on the GPU performance profiling added in the last cycle. It is also prep work for hooking in the DRM GPU scheduler, which I hope to land for the next cycle. Regards, Lucas The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323: Linux 4.15-rc1 (2017-11-26 16:01:47 -0800) are available in the Git repository at: https://git.pengutronix.de/git/lst/linux etnaviv/next for you to fetch changes up to 2f20fc4fc9db236dc3806a93e78c7575c9561590: drm/etnaviv: use memset32 to init pagetable (2018-01-02 17:36:53 +0100) ---------------------------------------------------------------- Christian Gmeiner (1): drm/etnaviv: add sensitive state for occlusion query address Lucas Stach (29): drm/etnaviv: fix GPU vs sync point race drm/etnaviv: split obj locks in different classes depending on the obj type drm/etnaviv: add lockdep annotation for userptr object population drm/etnaviv: fold __etnaviv_gem_new into caller drm/etnaviv: change return type of etnaviv_gem_obj_add to void drm/etnaviv: get rid of userptr worker drm/etnaviv: remove -EAGAIN handling from submit path drm/etnaviv: remove stale TODO in etnaviv_gpu_submit drm/etnaviv: don't flush workqueue in etnaviv_gpu_wait_obj_inactive drm/etnaviv: remove switch_context member from etnaviv_gpu drm/etnaviv: move workqueue to be per GPU drm/etnaviv: hold GPU lock while inserting END command drm/etnaviv: add lockdep annotations to buffer manipulation functions drm/etnaviv: simplify submit_create drm/etnaviv: move object fence attachment to gem_submit path drm/etnaviv: rename submit fence to out_fence drm/etnaviv: attach in fence to submit and move fence wait to fence_sync drm/etnaviv: move object unpinning to submit cleanup drm/etnaviv: move ww_acquire_ctx out of submit object drm/etnaviv: refcount the submit object drm/etnaviv: move PMRs to submit object drm/etnaviv: move exec_state to submit object drm/etnaviv: use submit exec_state for perfmon sampling drm/etnaviv: move cmdbuf into submit object drm/etnaviv: move GPU active handling to bo pin/unpin drm/etnaviv: couple runtime PM management to submit object lifetime drm/etnaviv: re-enable perfmon support drm/etnaviv: move submit free out of critical section drm/etnaviv: use memset32 to init pagetable Markus Elfring (1): drm/etnaviv: Improve unlocking of a mutex in etnaviv_iommu_map_gem() Philipp Zabel (1): drm/etnaviv: make THERMAL selectable drivers/gpu/drm/etnaviv/Kconfig | 9 ++ drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 40 ++++++--- drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c | 1 + drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c | 29 +----- drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.h | 18 +--- drivers/gpu/drm/etnaviv/etnaviv_drv.c | 22 +---- drivers/gpu/drm/etnaviv/etnaviv_drv.h | 14 +-- drivers/gpu/drm/etnaviv/etnaviv_dump.c | 23 ++--- drivers/gpu/drm/etnaviv/etnaviv_gem.c | 197 +++++++++-------------------------------- drivers/gpu/drm/etnaviv/etnaviv_gem.h | 22 +++-- drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 7 +- drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 199 ++++++++++++++++++++++------------------- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 215 ++++++++++++++++----------------------------- drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 11 +-- drivers/gpu/drm/etnaviv/etnaviv_iommu.c | 5 +- drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c | 2 +- drivers/gpu/drm/etnaviv/etnaviv_mmu.c | 14 ++- drivers/gpu/drm/etnaviv/etnaviv_perfmon.c | 4 +- drivers/gpu/drm/etnaviv/etnaviv_perfmon.h | 2 +- 19 files changed, 323 insertions(+), 511 deletions(-)

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[PATCH v2 0/8] Fix PSR-vblank-DMC interaction
by Dhinakaran Pandiyan 03 Jan '18

03 Jan '18

The first 3 patches are minor PSR improvements. The last 5 introduce a new power domain to disable DC states when vblanks are required. The tricky part is to enable and disable the DC_OFF power well in atomic context. I have addressed the locking issues that CI caught in the last revision. Dhinakaran Pandiyan (8): drm/i915/psr: Kill psr.source_ok flag. drm/i915/psr: CAN_PSR() macro to check for PSR source and sink support. drm/i915/psr: Avoid initializing PSR if there is no sink support. drm/vblank: Do not update vblank counts if vblanks are already disabled. drm/vblank: Restoring vblank counts after device runtime PM events. drm/i915: Use an atomic_t array to track power domain use count. drm/i915: Introduce a non-blocking power domain for vblank interrupts drm/i915: Use the vblank power domain disallow or disable DC states. drivers/gpu/drm/drm_vblank.c | 56 ++++++--- drivers/gpu/drm/i915/i915_debugfs.c | 10 +- drivers/gpu/drm/i915/i915_drv.h | 21 +++- drivers/gpu/drm/i915/i915_irq.c | 6 + drivers/gpu/drm/i915/intel_drv.h | 4 + drivers/gpu/drm/i915/intel_psr.c | 30 +++-- drivers/gpu/drm/i915/intel_runtime_pm.c | 195 ++++++++++++++++++++++++++++---- include/drm/drm_vblank.h | 1 + 8 files changed, 268 insertions(+), 55 deletions(-) -- 2.11.0

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Radeon rv250 GPU acceleration broken in 4.15-rc6
by Meelis Roos 03 Jan '18

03 Jan '18

Beacuse of PTI, I decided to test 4.15-rc6 on most of my test machines. And I happened to notice a radeon problem on RV250 era card with no monitor attached. 4.15-rc1 and earlier kernels did not show these errors, not kernels between rc1 and rc6 have been tested yet. The messages in dmes are strange, like 2 threads trying to poke the card instead of one? Or is it just rrying AGP mode and then PCI mode and this double output is OK? [ 4.777185] [drm] radeon kernel modesetting enabled. [ 4.779418] [drm] initializing kernel modesetting (RV250 0x1002:0x4966 0x1458:0x4010 0x01). [ 4.779888] agpgart-amdk7 0000:00:00.0: AGP 2.0 bridge [ 4.779963] agpgart-amdk7 0000:00:00.0: putting AGP V2 device into 4x mode [ 4.780106] radeon 0000:01:05.0: putting AGP V2 device into 4x mode [ 4.780179] radeon 0000:01:05.0: GTT: 512M 0xC0000000 - 0xDFFFFFFF [ 4.780249] radeon 0000:01:05.0: VRAM: 128M 0x00000000E0000000 - 0x00000000E7FFFFFF (64M used) [ 4.780344] [drm] Detected VRAM RAM=128M, BAR=128M [ 4.780405] [drm] RAM width 128bits DDR [ 4.780622] [TTM] Zone kernel: Available graphics memory: 439294 kiB [ 4.780686] [TTM] Zone highmem: Available graphics memory: 1032930 kiB [ 4.780749] [TTM] Initializing pool allocator [ 4.780898] [drm] radeon: 64M of VRAM memory ready [ 4.780961] [drm] radeon: 512M of GTT memory ready. [ 4.783068] radeon 0000:01:05.0: WB disabled [ 4.783166] radeon 0000:01:05.0: fence driver on ring 0 use gpu addr 0x00000000c0000000 and cpu addr 0xf6a59461 [ 4.783261] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 4.783323] [drm] Driver supports precise vblank timestamp query. [ 4.783447] [drm] radeon: irq initialized. [ 4.783509] [drm] Loading R200 Microcode [ 4.819844] [drm] radeon: ring at 0x00000000C0001000 [ 4.923034] [drm:r100_ring_test [radeon]] *ERROR* radeon: ring test failed (scratch(0x15E4)=0xCAFEDEAD) [ 4.923181] [drm:r100_cp_init [radeon]] *ERROR* radeon: cp isn't working (-22). [ 4.923271] radeon 0000:01:05.0: failed initializing CP (-22). [ 4.923332] radeon 0000:01:05.0: Disabling GPU acceleration [ 5.025789] [drm:r100_cp_fini [radeon]] *ERROR* Wait for CP idle timeout, shutting down CP. [ 5.026022] [drm] radeon: cp finalized [ 5.026128] [drm] radeon: cp finalized [ 5.026223] [TTM] Finalizing pool allocator [ 5.027245] [TTM] Zone kernel: Used memory at exit: 0 kiB [ 5.027331] [TTM] Zone highmem: Used memory at exit: 0 kiB [ 5.027397] [drm] radeon: ttm finalized [ 5.027468] [drm] Forcing AGP to PCI mode [ 5.027886] radeon 0000:01:05.0: VRAM: 128M 0x00000000E0000000 - 0x00000000E7FFFFFF (64M used) [ 5.028577] radeon 0000:01:05.0: GTT: 512M 0x00000000C0000000 - 0x00000000DFFFFFFF [ 5.028671] [drm] Detected VRAM RAM=128M, BAR=128M [ 5.028730] [drm] RAM width 128bits DDR [ 5.028942] [TTM] Zone kernel: Available graphics memory: 439294 kiB [ 5.029005] [TTM] Zone highmem: Available graphics memory: 1032930 kiB [ 5.029066] [TTM] Initializing pool allocator [ 5.029216] [drm] radeon: 64M of VRAM memory ready [ 5.029277] [drm] radeon: 512M of GTT memory ready. [ 5.029342] [drm] GART: num cpu pages 131072, num gpu pages 131072 [ 5.034222] [drm] PCI GART of 512M enabled (table at 0x0000000035600000). [ 5.034393] radeon 0000:01:05.0: WB disabled [ 5.034465] radeon 0000:01:05.0: fence driver on ring 0 use gpu addr 0x00000000c0000000 and cpu addr 0x516b4fc4 [ 5.034557] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 5.034618] [drm] Driver supports precise vblank timestamp query. [ 5.034729] [drm] radeon: irq initialized. [ 5.034984] [drm] radeon: ring at 0x00000000C0001000 [ 5.138470] [drm:r100_ring_test [radeon]] *ERROR* radeon: ring test failed (scratch(0x15E4)=0xCAFEDEAD) [ 5.138618] [drm:r100_cp_init [radeon]] *ERROR* radeon: cp isn't working (-22). [ 5.138704] radeon 0000:01:05.0: failed initializing CP (-22). [ 5.138764] radeon 0000:01:05.0: Disabling GPU acceleration [ 5.241223] [drm:r100_cp_fini [radeon]] *ERROR* Wait for CP idle timeout, shutting down CP. [ 5.241408] [drm] radeon: cp finalized [ 5.243484] [drm] No TV DAC info found in BIOS [ 5.243659] [drm] Radeon Display Connectors [ 5.243719] [drm] Connector 0: [ 5.243776] [drm] VGA-1 [ 5.243833] [drm] DDC: 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 [ 5.243894] [drm] Encoders: [ 5.243951] [drm] CRT1: INTERNAL_DAC1 [ 5.244064] [drm] Connector 1: [ 5.244120] [drm] DVI-I-1 [ 5.244176] [drm] HPD1 [ 5.244231] [drm] DDC: 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 [ 5.244291] [drm] Encoders: [ 5.244346] [drm] CRT2: INTERNAL_DAC2 [ 5.244404] [drm] DFP1: INTERNAL_TMDS1 [ 5.244460] [drm] Connector 2: [ 5.244516] [drm] SVIDEO-1 [ 5.244571] [drm] Encoders: [ 5.244626] [drm] TV1: INTERNAL_DAC2 [ 5.262348] [drm] Cannot find any crtc or sizes [ 5.262491] [drm] Initialized radeon 2.50.0 20080528 for 0000:01:05.0 on minor 0 [ 6.290422] [drm] Cannot find any crtc or sizes -- Meelis Roos (mroos(a)linux.ee)

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[pull] amdgpu and ttm drm-fixes-4.15
by Alex Deucher 03 Jan '18

03 Jan '18

Hi Dave, Just two small fixes for 4.15: - backport of a DC change which fixes a greenish tint on some RV hw - properly handle kzalloc fail in ttm The following changes since commit 03bfd4e19b935adb8be4f7342f13395fb7f11096: Merge tag 'drm-intel-fixes-2017-12-22-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes (2017-12-28 05:20:07 +1000) are available in the git repository at: git://people.freedesktop.org/~agd5f/linux drm-fixes-4.15 for you to fetch changes up to 19d859a7205bc59ffc38303eb25ae394f61d21dc: drm/ttm: check the return value of kzalloc (2018-01-02 14:54:05 -0500) ---------------------------------------------------------------- Xiongwei Song (1): drm/ttm: check the return value of kzalloc Yue Hin Lau (1): drm/amd/display: call set csc_default if enable adjustment is false drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 6 ++---- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++ drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 2 +- drivers/gpu/drm/ttm/ttm_page_alloc.c | 2 ++ 5 files changed, 8 insertions(+), 6 deletions(-)

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[RFC PATCH v2 00/13] Kernel based bootsplash
by Max Staudt 03 Jan '18

03 Jan '18

Dear fbdev and fbcon developers, Thank you very much for your input for the first patch series. I've included your feedback into this second roll, and kindly ask for your opinion on the new patch series. Changes from v1 to v2: + Added a user space tool to create splash theme files + Bumped the file format version: - Larger structs for easy future expansion - 2-byte corner offset - Offset either from corner or from center - Fixed padding before header->frame_ms + Moved bootsplash_file.h to uapi/linux + Merged several patches + Theme files are now loaded via request_firmware() + sysfs hook to allow loading of theme files via request_firmware() + Dropped the .enable cmdline option and the default file name. The splash will be shown as soon as a file is specified. + Dropped custom workqueue in favor of the kernel queue and cancel_delayed_work_sync() + Marked loaded data as const, and load/enable it atomically + Reduced global state by moving data into other structures + EXPORT_SYMBOL_GPL for fbcon_set_dummyops() + Atomic and barrier for splash enabled state instead of spinlock + Reduced warnings to infos + Rate limited printk + Changed the multi-line comment layout to kernel style + Simplified the file headers + reST-ed the documentation Max

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dri-devel January 2018