dri-devel October 2018

dri-devel@lists.freedesktop.org

277 participants
1898 discussions

[Bug 108262] Unable to open intel_gpu_top (sudo): Test assertion failure function init_instdone_definitions, file instdone.c:599
by bugzilla-daemon＠freedesktop.org 08 Oct '18

08 Oct '18

https://bugs.freedesktop.org/show_bug.cgi?id=108262 Petri Latvala <petri.latvala(a)intel.com> changed: What |Removed |Added ---------------------------------------------------------------------------- Resolution|--- |FIXED Status|NEW |RESOLVED -- You are receiving this mail because: You are the assignee for the bug.

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[Bug 108262] Unable to open intel_gpu_top (sudo): Test assertion failure function init_instdone_definitions, file instdone.c:599
by bugzilla-daemon＠freedesktop.org 08 Oct '18

08 Oct '18

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[PATCH 2/2] drm/exynos: fimd: Make pixel blend mode configurable
by Christoph Manszewski 08 Oct '18

08 Oct '18

Currently blend mode is set accordingly to pixel format. Add pixel blend mode property and make that configurable. Fimd hardware doesn't support premultiplied mode, choose coverage as default. Tested on TRATS2 with Exynos 4412 CPU, on top of exynos-drm-next using modetest. Signed-off-by: Christoph Manszewski <c.manszewski(a)samsung.com> --- Similar to exynos5433_drm_decon, the driver exposes the "premultiplied" option for pixel blend mode property, although hardware doesn't support it, and it's hanlded by the driver as "coverage". Again, that's because the premultiplied mode is required and used as default. drivers/gpu/drm/exynos/exynos_drm_fimd.c | 28 ++++++++++++++++++++++------ include/video/samsung_fimd.h | 1 + 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 06d5d2422246..c4b0fb05a19b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -231,10 +231,10 @@ static const uint32_t fimd_formats[] = { static const unsigned int capabilities[WINDOWS_NR] = { 0, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, }; static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, @@ -576,6 +576,23 @@ static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win, unsigned int alpha = state->base.alpha; u32 win_alpha = alpha >> 8; u32 val = 0; + unsigned int pixel_alpha; + + if (fb->format->has_alpha) + pixel_alpha = state->base.pixel_blend_mode; + else + pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; + + switch (pixel_alpha) { + case DRM_MODE_BLEND_PIXEL_NONE: + break; + case DRM_MODE_BLEND_COVERAGE: + default: + val |= WINCON1_ALPHA_SEL; + val |= WINCON1_BLD_PIX; + val |= WINCON1_ALPHA_MUL; + } + fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val); /* OSD alpha */ val = VIDISD14C_ALPHA0_R(alpha >> 4) | @@ -639,7 +656,6 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; val |= WINCONx_WSWP; val |= WINCONx_BURSTLEN_16WORD; - val |= WINCON1_ALPHA_MUL; break; } @@ -656,7 +672,7 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, val |= WINCONx_BURSTLEN_4WORD; } - writel(val, ctx->regs + WINCON(win)); + fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val); /* hardware window 0 doesn't support alpha channel. */ if (win != 0) diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index f070b7c0d2cf..bb1d5baa74d6 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -198,6 +198,7 @@ #define WINCONx_BURSTLEN_8WORD (0x1 << 9) #define WINCONx_BURSTLEN_4WORD (0x2 << 9) #define WINCONx_ENWIN (1 << 0) +#define WINCONx_BLEND_MODE_MASK (0xc2) #define WINCON0_BPPMODE_MASK (0xf << 2) #define WINCON0_BPPMODE_SHIFT 2 -- 2.7.4

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[PATCH 1/2] drm/exynos: fimd: Make plane alpha configurable
by Christoph Manszewski 08 Oct '18

08 Oct '18

The fimd hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on TRATS2 with Exynos 4412 CPU, on top of exynos-drm-next. Signed-off-by: Christoph Manszewski <c.manszewski(a)samsung.com> --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 69 +++++++++++++++++++++++--------- include/video/samsung_fimd.h | 1 + 2 files changed, 51 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index b7f56935a46b..06d5d2422246 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -229,6 +229,21 @@ static const uint32_t fimd_formats[] = { DRM_FORMAT_ARGB8888, }; +static const unsigned int capabilities[WINDOWS_NR] = { + 0, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, +}; + +static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, + u32 val) +{ + val = (val & mask) | (readl(ctx->regs + reg) & ~mask); + writel(val, ctx->regs + reg); +} + static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) { struct fimd_context *ctx = crtc->ctx; @@ -552,10 +567,38 @@ static void fimd_commit(struct exynos_drm_crtc *crtc) writel(val, ctx->regs + VIDCON0); } +static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win, + struct drm_framebuffer *fb) +{ + struct exynos_drm_plane plane = ctx->planes[win]; + struct exynos_drm_plane_state *state = + to_exynos_plane_state(plane.base.state); + unsigned int alpha = state->base.alpha; + u32 win_alpha = alpha >> 8; + u32 val = 0; + + /* OSD alpha */ + val = VIDISD14C_ALPHA0_R(alpha >> 4) | + VIDISD14C_ALPHA0_G(win_alpha >> 4) | + VIDISD14C_ALPHA0_B(win_alpha >> 4) | + VIDISD14C_ALPHA1_R(win_alpha >> 4) | + VIDISD14C_ALPHA1_G(win_alpha >> 4) | + VIDISD14C_ALPHA1_B(win_alpha >> 4); + + writel(val, ctx->regs + VIDOSD_C(win)); + + val = VIDW_ALPHA_R(win_alpha & 0xf) | VIDW_ALPHA_G(win_alpha & 0xf) | + VIDW_ALPHA_G(win_alpha & 0xf); + writel(val, ctx->regs + VIDWnALPHA0(win)); + writel(val, ctx->regs + VIDWnALPHA1(win)); + fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK, + BLENDCON_NEW_8BIT_ALPHA_VALUE); +} static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, - uint32_t pixel_format, int width) + struct drm_framebuffer *fb, int width) { + uint32_t pixel_format = fb->format->format; unsigned long val; val = WINCONx_ENWIN; @@ -596,6 +639,7 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; val |= WINCONx_WSWP; val |= WINCONx_BURSTLEN_16WORD; + val |= WINCON1_ALPHA_MUL; break; } @@ -607,7 +651,7 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, * still better to change dma-burst than displaying garbage. */ - if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) { + if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { val &= ~WINCONx_BURSTLEN_MASK; val |= WINCONx_BURSTLEN_4WORD; } @@ -615,22 +659,8 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, writel(val, ctx->regs + WINCON(win)); /* hardware window 0 doesn't support alpha channel. */ - if (win != 0) { - /* OSD alpha */ - val = VIDISD14C_ALPHA0_R(0xf) | - VIDISD14C_ALPHA0_G(0xf) | - VIDISD14C_ALPHA0_B(0xf) | - VIDISD14C_ALPHA1_R(0xf) | - VIDISD14C_ALPHA1_G(0xf) | - VIDISD14C_ALPHA1_B(0xf); - - writel(val, ctx->regs + VIDOSD_C(win)); - - val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | - VIDW_ALPHA_G(0xf); - writel(val, ctx->regs + VIDWnALPHA0(win)); - writel(val, ctx->regs + VIDWnALPHA1(win)); - } + if (win != 0) + fimd_win_set_bldmod(ctx, win, fb); } static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) @@ -786,7 +816,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc, DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); } - fimd_win_set_pixfmt(ctx, win, fb->format->format, state->src.w); + fimd_win_set_pixfmt(ctx, win, fb, state->src.w); /* hardware window 0 doesn't support color key. */ if (win != 0) @@ -988,6 +1018,7 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); ctx->configs[i].zpos = i; ctx->configs[i].type = fimd_win_types[i]; + ctx->configs[i].capabilities = capabilities[i]; ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, &ctx->configs[i]); if (ret) diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index d8fc96ed11e9..f070b7c0d2cf 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -211,6 +211,7 @@ #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) #define WINCON1_LOCALSEL_CAMIF (1 << 23) +#define WINCON1_ALPHA_MUL (1 << 7) #define WINCON1_BLD_PIX (1 << 6) #define WINCON1_BPPMODE_MASK (0xf << 2) #define WINCON1_BPPMODE_SHIFT 2 -- 2.7.4

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[PATCH 0/2] drm/exynos: decon: Add properties
by Christoph Manszewski 08 Oct '18

08 Oct '18

Hello, This patch series adds two new configurable properties to exynos5433_drm_decon. Patch 1 add window alpha property. Patch 2 add pixel blend mode property. Regards, Chris Christoph Manszewski (2): drm/exynos: decon: Make plane alpha configurable drm/exynos: decon: Make pixel blend mode configurable drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 51 ++++++++++++++++++++++++++- drivers/gpu/drm/exynos/regs-decon5433.h | 5 +++ 2 files changed, 55 insertions(+), 1 deletion(-) -- 2.7.4

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[PATCH 0/3] ARM: dts: imx6sx: Add DISPLAY power domain support
by Leonard Crestez 08 Oct '18

08 Oct '18

Now that mxsfb has functional runtime_pm support we can enable power gating for the DISPLAY power domain on imx6sx. Since pci-imx doesn't support runtime power gating this is still always-on unless PCI is disabled/unused. But it's reasonable for an imx board to not have PCI. The current pd_pcie is actually only for PCIE_PHY, the PCIE ip block is actually inside the DISPLAY domain. This is handled by adding the pcie node in both power domains, using multi-pd support. Series is against linux-next. The last patch needs runtime PM in all drivers or it will cause hangs. This means Shawn should hold back on it until the PCI and mxsfb dependencies get merged (both might take a long time). So you can just review that patch and I will resend it later, perhaps in another cycle. Link to mxsfb thread: https://lkml.org/lkml/2018/9/26/1185 Leonard Crestez (3): soc: imx: gpc: Increase GPC_CLK_MAX to 7 PCI: imx: Add multi-pd support ARM: dts: imx6sx: Add DISPLAY power domain support arch/arm/boot/dts/imx6sx.dtsi | 19 ++++++++++- drivers/pci/controller/dwc/pci-imx6.c | 48 +++++++++++++++++++++++++++ drivers/soc/imx/gpc.c | 2 +- 3 files changed, 67 insertions(+), 2 deletions(-) -- 2.17.1

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[pull] drm/msm: msm-next for 4.20
by Rob Clark 07 Oct '18

07 Oct '18

Hi Dave, This time mostly further refinement of dpu1+a6xx for sdm845 and beyond.. and hurray for more negative diffstat :-) - Misc cleanups and fixes - GPU preemption optimization - a6xx perf improvements and clock fixes (ie. lets actually not run at minimum clks) - a6xx devfreq/DCVS - Lots of code cleanup across dpu (Bruce, Jeykumar, Sean) - Fixed a few crashes on startup relating to dsi (Sean) - Add cursor support (Sravanthi, Sean) - Properly free mdss irq on destroy (Jordan) - Use correct encoder_type when initializing, fixes crash on boot (Stephen) ----------------- The following changes since commit 87c2ee740c07f1edae9eec8bc45cb9b32a68f323: Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-next (2018-09-28 09:48:40 +1000) are available in the Git repository at: git://people.freedesktop.org/~robclark/linux drm-msm-next-2018-10-07 for you to fetch changes up to d21cc8e340ee88890122c1080fc78781a1870746: drm/msm/a6xx: Remove CP perfcounter selects from the protected list (2018-10-05 16:18:09 -0400) ---------------------------------------------------------------- Anders Roxell (1): drm/msm/gpu: fix parameters in function msm_gpu_crashstate_capture Bruce Wang (7): drm/msm/dpu: Remove unneeded checks in dpu_plane.c drm/msm/dpu: Clean up plane atomic disable/update drm/msm/dpu: Remove unneeded checks in dpu_crtc.c drm/msm/dpu: Remove _dpu_crtc_power_enable drm/msm/dpu: Change _dpu_crtc_vblank_enable_no_lock to void drm/msm/dpu: Make dpu_plane_danger_signal_ctrl void drm/msm/dpu: Revise _dpu_plane_get_aspace Colin Ian King (1): drm/msm: fix unsigned comparison with less than zero Jeykumar Sankaran (22): drm/msm/dpu: remove stale display port programming drm/msm/dpu: remove unwanted encoder type mapping drm/msm/dpu: use encoder type to identify display type drm/msm/dpu: remove debugfs support for misr drm/msm/dpu: squash power handle event types drm/msm/dpu: remove scalar config definitions drm/msm/dpu: remove resource pool manager drm/msm/dpu: remove ping pong split topology variables drm/msm/dpu: enable master-slave encoders explicitly drm/msm/dpu: use kms stored hw mdp block drm/msm/dpu: iterate for assigned hw ctl in virtual encoder drm/msm/dpu: avoid querying for hw intf before assignment drm/msm/dpu: make crtc get_mixer_width helper static drm/msm/dpu: move hw resource tracking to crtc state drm/msm/dpu: rename hw_ctl to lm_ctl drm/msm/dpu: clean up destination scaler residue drm/msm/dpu: remove cdm block support from resource manager drm/msm/dpu: remove LOCK/CLEAR support in RM drm/msm/dpu: remove display H_TILE from encoder drm/msm/dpu: remove RM dependency on connector state drm/msm/dpu: relax parameter validation in encoders drm/msm/dpu: remove RM topology definition Jordan Crouse (8): drm/msm/dpu: Remove dpu_mdss_isr when dpu_mdss_destroy is called drm/msm/dpu: Remove an unused enum drm/msm/a6xx: Rename gmu phandle to qcom,gmu drm/msm/a6xx: Fix PDC register overlap msm/gpu/a6xx: Force of_dma_configure to setup DMA for GMU drm/msm/a6xx: Poll for HFI responses drm/msm/a6xx: Add inactive_period for a6xx drm/msm/a6xx: Remove CP perfcounter selects from the protected list Rob Clark (2): drm/msm/rd: fix crash with long process cmdlines drm/msm: update generated headers Sean Paul (17): drm/msm: dsi: Initialize msm_dsi->id to -1 drm/msm: dsi: Return errors whan dt parsing fails drm/msm: Don't fail bind if nothing connected to dsi drm/msm: dpu: Allow planes to extend past active display drm/msm: dpu: Remove impossible checks drm/msm: dpu: Move atomic_check_plane_state() call to atomic_check drm/msm: dpu: Consolidate atomic_check functions() drm/msm: dpu: Remove dpu_plane_sspp_enabled() drm/msm: dpu: Remove dpu_plane_enabled() drm/msm: dpu: Make dpu_plane_sspp_atomic_update() void drm/msm: dpu: Don't continue after error in atomic_check drm/msm: dpu: Clear frame_busy_mask bit after trace drm/msm: dpu: Add extra_flush_bits to trigger_flush trace drm/msm: dpu: Don't store/deref pointers in trace ringbuffer drm/msm: dpu: Don't reset dpu_enc->cur_master on .disable() drm/msm: a5xx: Fix improper u64 division drm/msm: dpu: Fix memory leak caused by dropped reference Sharat Masetty (6): drm/msm/a6xx: Send the right perf index value to GMU drm/msm/a5xx: Skip hardware preemption init if no preemption drm/msm: suspend devfreq on init drm/msm/a6xx: Add gmu_read64() register read op drm/msm: re-factor devfreq code drm/msm/a6xx: Add devfreq support for a6xx Sravanthi Kollukuduru (2): drm/msm/dpu: enable cursor plane on dpu drm/msm/dpu: fix for cursor blend issue Stephen Boyd (1): drm/msm/disp/dpu: Use proper define for drm_encoder_init() 'encoder_type' Thomas Zimmermann (3): drm/msm: Replace drm_framebuffer_{un/reference} with put, get functions drm/msm: Replace drm_gem_object_{un/reference} with put, get functions drm/msm: Replace drm_dev_unref with drm_dev_put drivers/gpu/drm/msm/Makefile | 1 - drivers/gpu/drm/msm/adreno/a2xx.xml.h | 8 +- drivers/gpu/drm/msm/adreno/a3xx.xml.h | 8 +- drivers/gpu/drm/msm/adreno/a4xx.xml.h | 8 +- drivers/gpu/drm/msm/adreno/a5xx.xml.h | 8 +- drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 20 +- drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 12 +- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 1413 +++++++++++++++----- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 144 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 21 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 12 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 35 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 3 +- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 161 +-- drivers/gpu/drm/msm/adreno/adreno_common.xml.h | 8 +- drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 26 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 737 ++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 115 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 257 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 23 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 48 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 125 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 109 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 56 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 323 ----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h | 139 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 16 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 29 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 7 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 29 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 7 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 39 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 18 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 17 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 16 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 45 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 499 ++----- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 15 +- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 14 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 285 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 44 - drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 116 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 5 +- drivers/gpu/drm/msm/dsi/dsi.c | 10 +- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 + drivers/gpu/drm/msm/dsi/dsi_manager.c | 4 +- drivers/gpu/drm/msm/msm_drv.c | 8 +- drivers/gpu/drm/msm/msm_drv.h | 2 + drivers/gpu/drm/msm/msm_gem_submit.c | 4 +- drivers/gpu/drm/msm/msm_gpu.c | 49 +- drivers/gpu/drm/msm/msm_gpu.h | 5 +- drivers/gpu/drm/msm/msm_rd.c | 6 +- 60 files changed, 1903 insertions(+), 3240 deletions(-) delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h

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[Bug 107045] [4.18rc2] RX470 dGPU on hybrid laptop freezes screen after use
by bugzilla-daemon＠freedesktop.org 06 Oct '18

06 Oct '18

https://bugs.freedesktop.org/show_bug.cgi?id=107045 Bug ID: 107045 Summary: [4.18rc2] RX470 dGPU on hybrid laptop freezes screen after use Product: DRI Version: DRI git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: critical Priority: medium Component: DRM/AMDgpu Assignee: dri-devel(a)lists.freedesktop.org Reporter: taijian(a)posteo.de Created attachment 140343 --> https://bugs.freedesktop.org/attachment.cgi?id=140343&action=edit full dmesg output via 'journalctl -kb -1' With kernel 4.18rc dpm on my hybrid laptop is finally working (thanks again to everyone who helped out getting it this far - see bug #104064, bug #106597 and bug #105760). However, it is still not actually usable, because any activation of the dGPU leads to a system freeze shortly thereafter. It does not really matter HOW the dGPU is triggered - be it running a graphical application via DRI_PRIME=1 or just querying #lshw. The dGPU activates and then tries to power down again, but that seems to be problematic as the (graphical) system will invariable freeze and become unresponsive. The best I have been able to reconstruct from the journal is that whenever the dGPU is called, it will first do this: [drm] PCIE GART of 256M enabled (table at 0x000000F400000000). followed by a bunch of this: amdgpu: [powerplay] failed to send message 62 ret is 0 amdgpu: [powerplay] last message was failed ret is 0 amdgpu: [powerplay] failed to send message 18f ret is 0 and then finally: [drm] UVD and UVD ENC initialized successfully. [drm] VCE initialized successfully. [drm] Cannot find any crtc or sizes amdgpu 0000:01:00.0: GPU pci config reset Sometimes, this will work more than once, sometimes the first invocation after boot will crash. This seems to be somewhat random. However, the crash will always come in the "[powerplay] ...failed to send message 18f ret is 0" phase. Any ideas how to tackle that or extract some more usable error message from my system? -- You are receiving this mail because: You are the assignee for the bug.

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[PATCH 00/27] Allwinner H6 DE3 and HDMI support
by Jernej Skrabec 06 Oct '18

06 Oct '18

This series adds support for Display Engine 3.0 and HDMI 2.0a, which can be found on H6 SoC. Display Engine 3.0 in comparison to 2.0 mostly adds features needed for displaying and processing 10-bit and AFBC formats, which are not yet supported by this series. This series is based on linux-next at next-20180828, which has working R40 display pipeline support. I'll rebase series on later linux-next, if needed, once R40 display pipeline support is reintroduced. I suggest all patches go through allwinner tree, except DRM patches, which should go through drm-misc tree. Last detail, PineH64 model A schematic has DDC_EN signal, which enables DDC voltage level shifter. TL Lim, PINE64 founder, said that this signal is not actually present on PineH64 model A board. It is, however present on PineH64 model B engineering samples, but it will be removed in production version. Because of that, I didn't include any code for it. Please take a look. Best regards, Jernej Icenowy Zheng (7): dt-bindings: sunxi-sram: add binding for Allwinner H6 SRAM C arm64: allwinner: h6: add system controller device tree node dt-bindings: bus: add H6 DE3 bus binding dt-bindings: display: sunxi: add DT binding for Allwinner H6 DW HDMI drm: sun4i: add quirks for TCON TOP dt-bindings: display: sun4i-drm: document H6 TCON TOP drm: sun4i: add support for H6 TCON TOP Jernej Skrabec (20): clk: sunxi-ng: Adjust MP clock parent rate when allowed clk: sunxi-ng: Use u64 for calculation of NM rate clk: sunxi-ng: h6: Set video PLLs limits dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description clk: sunxi-ng: Add support for H6 DE3 clocks dt-bindings: display: sun4i-drm: Add H6 display engine compatibles drm/sun4i: Add compatible for H6 display engine drm/sun4i: Rework DE2 register defines drm/sun4i: Add basic support for DE3 drm/sun4i: Add support for H6 DE3 mixer 0 drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a drm/sun4i: Not all DW HDMI controllers has scrambled addresses drm/sun4i: dw-hdmi: Make mode_valid function configurable drm/sun4i: dw-hdmi: Add quirk for setting TMDS clock drm/sun4i: Add support for H6 DW HDMI controller drm/sun4i: Add support for Synopsys HDMI PHY drm/sun4i: Add support for H6 HDMI PHY drm/sun4i: Initialize registers in tcon-top driver arm64: dts: sun50i: h6: Add HDMI pipeline arm64: dts: sun50i: h6: Enable HDMI output on Pine H64 board .../bindings/bus/sun50i-de2-bus.txt | 9 +- .../devicetree/bindings/clock/sun8i-de2.txt | 5 +- .../bindings/display/sunxi/sun4i-drm.txt | 30 ++- .../devicetree/bindings/sram/sunxi-sram.txt | 4 + .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 25 ++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 224 ++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 4 + drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 65 +++++ drivers/clk/sunxi-ng/ccu-sun8i-de2.h | 1 + drivers/clk/sunxi-ng/ccu_mp.c | 64 ++++- drivers/clk/sunxi-ng/ccu_nm.c | 18 +- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 + drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + drivers/gpu/drm/sun4i/sun8i_csc.c | 96 +++++++- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 45 +++- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 14 +- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 178 +++++++++++++- drivers/gpu/drm/sun4i/sun8i_mixer.c | 44 +++- drivers/gpu/drm/sun4i/sun8i_mixer.h | 61 +++-- drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 58 ++++- drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 47 ++-- drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 37 +-- drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 45 ++-- drivers/gpu/drm/sun4i/sun8i_ui_scaler.h | 28 +-- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 55 +++-- drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 25 +- drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 85 +++++-- drivers/gpu/drm/sun4i/sun8i_vi_scaler.h | 68 ++++-- include/dt-bindings/clock/sun8i-de2.h | 3 + include/dt-bindings/reset/sun8i-de2.h | 1 + 30 files changed, 1127 insertions(+), 214 deletions(-) -- 2.18.0

7 71

[PATCH resend 00/15] staging: vboxvideo: Convert to atomic modesetting API
by Hans de Goede 06 Oct '18

06 Oct '18

Hi All, This series converts the vboxvideo driver to the modesetting API, once this is merged I will submit a patch to move the driver out of staging and into drivers/gpu/drm. This series consists of 3 parts: 1) More cleanups / prep work for atomic conversion 2) The actual atomic conversion, this is modelled after the atomic conversion of the qxl driver done by Gabriel Krisman Bertazi. Gabriel if you are reading this, thank you for providing a roadmap how to go about this. 3) Restore some features which were lost by the atomic conversion + more cleanups Regards, Hans

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dri-devel October 2018