dri-devel December 2018

dri-devel@lists.freedesktop.org

283 participants
2020 discussions

[PATCH v3 1/4] drm/msm/mdp4: add lcdc-align-lsb flag to control lane alignment
by Jonathan Marek 03 Dec '18

03 Dec '18

This allows controlling which of the 8 lanes are used for 6 bit color. Signed-off-by: Jonathan Marek <jonathan(a)marek.ca> --- v3: removed empty line and added documentation .../devicetree/bindings/display/msm/mdp4.txt | 2 ++ .../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 21 ++++++++++++------- 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.txt b/Documentation/devicetree/bindings/display/msm/mdp4.txt index 3c341a15c..b07eeb38f 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp4.txt +++ b/Documentation/devicetree/bindings/display/msm/mdp4.txt @@ -38,6 +38,8 @@ Required properties: Optional properties: - clock-names: the following clocks are optional: * "lut_clk" +- qcom,lcdc-align-lsb: Boolean value indicating that LSB alignment should be + used for LCDC. This is only valid for 18bpp panels. Example: diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c index 9e08c2efa..c9e34501a 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c @@ -377,20 +377,25 @@ static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder) unsigned long pc = mdp4_lcdc_encoder->pixclock; struct mdp4_kms *mdp4_kms = get_kms(encoder); struct drm_panel *panel; + uint32_t config; int i, ret; if (WARN_ON(mdp4_lcdc_encoder->enabled)) return; /* TODO: hard-coded for 18bpp: */ - mdp4_crtc_set_config(encoder->crtc, - MDP4_DMA_CONFIG_R_BPC(BPC6) | - MDP4_DMA_CONFIG_G_BPC(BPC6) | - MDP4_DMA_CONFIG_B_BPC(BPC6) | - MDP4_DMA_CONFIG_PACK_ALIGN_MSB | - MDP4_DMA_CONFIG_PACK(0x21) | - MDP4_DMA_CONFIG_DEFLKR_EN | - MDP4_DMA_CONFIG_DITHER_EN); + config = + MDP4_DMA_CONFIG_R_BPC(BPC6) | + MDP4_DMA_CONFIG_G_BPC(BPC6) | + MDP4_DMA_CONFIG_B_BPC(BPC6) | + MDP4_DMA_CONFIG_PACK(0x21) | + MDP4_DMA_CONFIG_DEFLKR_EN | + MDP4_DMA_CONFIG_DITHER_EN; + + if (!of_property_read_bool(dev->dev->of_node, "qcom,lcdc-align-lsb")) + config |= MDP4_DMA_CONFIG_PACK_ALIGN_MSB; + + mdp4_crtc_set_config(encoder->crtc, config); mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 0); bs_set(mdp4_lcdc_encoder, 1); -- 2.17.1

1 2

[PATCH 1/6] drm/v3d: Document cache flushing ABI.
by Eric Anholt 03 Dec '18

03 Dec '18

Right now, userspace doesn't do any L2T writes, but we should lay out our expectations for how it works. Signed-off-by: Eric Anholt <eric(a)anholt.net> --- include/uapi/drm/v3d_drm.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/uapi/drm/v3d_drm.h b/include/uapi/drm/v3d_drm.h index 35c7d813c66e..95b8f8e82ea5 100644 --- a/include/uapi/drm/v3d_drm.h +++ b/include/uapi/drm/v3d_drm.h @@ -52,6 +52,13 @@ extern "C" { * * This asks the kernel to have the GPU execute an optional binner * command list, and a render command list. + * + * The caches (L1T, slice, and L2T) will be flushed before the job + * executes. The TLB writes are guaranteed to have been flushed by + * the time the render done IRQ happens, which is the trigger for + * out_sync. Any dirtying of cachelines by the job (only possible + * using TMU writes) must be flushed by the caller using the CL's + * cache flush commands. */ struct drm_v3d_submit_cl { /* Pointer to the binner command list. -- 2.20.0.rc1

2 13

[PATCH] drm/msm/a6xx: Remove unwanted regulator code
by Jordan Crouse 03 Dec '18

03 Dec '18

The GMU code currently has some misguided code to try to work around a hardware quirk that requires the power domains on the GPU be collapsed in a certain order. Future changes will do this the right way so get rid of the unused and unwanted regulator code. Signed-off-by: Jordan Crouse <jcrouse(a)codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ---- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 -- 2 files changed, 6 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index c58e953fefa3..4a989d4e65f9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -671,9 +671,6 @@ int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu) gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, (val & 1), 100, 1000); - /* Force off the GX GSDC */ - regulator_force_disable(gmu->gx); - /* Disable the resources */ clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); pm_runtime_put_sync(gmu->dev); @@ -1214,7 +1211,6 @@ int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node) gmu->idle_level = GMU_IDLE_STATE_ACTIVE; pm_runtime_enable(gmu->dev); - gmu->gx = devm_regulator_get(gmu->dev, "vdd"); /* Get the list of clocks */ ret = a6xx_gmu_clocks_probe(gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index c721d9165d8e..8081083cd062 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -52,8 +52,6 @@ struct a6xx_gmu { int hfi_irq; int gmu_irq; - struct regulator *gx; - struct iommu_domain *domain; u64 uncached_iova_base; -- 2.18.0

1 0

[PATCH] drm/msm/a6xx: Add a name for the crashdumper buffer
by Jordan Crouse 03 Dec '18

03 Dec '18

Add a buffer object name for the a6xx crashdumper so it can be seen with the changes introduced by 7799a98edd ("drm/msm: Add a name field for gem objects"). Signed-off-by: Jordan Crouse <jcrouse(a)codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index 716595b664dd..e686331fa089 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -116,7 +116,10 @@ static int a6xx_crashdumper_init(struct msm_gpu *gpu, SZ_1M, MSM_BO_UNCACHED, gpu->aspace, &dumper->bo, &dumper->iova); - return IS_ERR(dumper->ptr) ? PTR_ERR(dumper->ptr) : 0; + if (!IS_ERR(dumper->ptr)) + msm_gem_object_set_name(dumper->bo, "crashdump"); + + return PTR_ERR_OR_ZERO(dumper->ptr); } static int a6xx_crashdumper_run(struct msm_gpu *gpu, -- 2.18.0

1 0

[PATCH] drm/msm/a6xx: Use new kernel API free function for gpu state
by Jordan Crouse 03 Dec '18

03 Dec '18

dadb36b7ec42 ("drm/msm: Add a common function to free kernel buffer objects") missed freeing the crashdumper state for a6xx. Signed-off-by: Jordan Crouse <jcrouse(a)codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index df6308e7ea67..716595b664dd 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -149,15 +149,6 @@ static int a6xx_crashdumper_run(struct msm_gpu *gpu, return ret; } -static void a6xx_crashdumper_free(struct msm_gpu *gpu, - struct a6xx_crashdumper *dumper) -{ - msm_gem_unpin_iova(dumper->bo, gpu->aspace); - msm_gem_put_vaddr(dumper->bo); - - drm_gem_object_unreference(dumper->bo); -} - /* read a value from the GX debug bus */ static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, u32 *data) @@ -900,7 +891,7 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) a6xx_get_clusters(gpu, a6xx_state, &dumper); a6xx_get_dbgahb_clusters(gpu, a6xx_state, &dumper); - a6xx_crashdumper_free(gpu, &dumper); + msm_gem_kernel_put(dumper.bo, gpu->aspace, true); } a6xx_get_debugbus(gpu, a6xx_state); -- 2.18.0

1 0

[PATCH 1/3] dma-buf: add dma_fence_get_stub
by Christian König 03 Dec '18

03 Dec '18

Extract of useful code from the timeline work. This provides a function to return a stub or dummy fence which is always signaled. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/dma-buf/dma-fence.c | 36 +++++++++++++++++++++++++++++++++++- include/linux/dma-fence.h | 1 + 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 1551ca7df394..136ec04d683f 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -30,13 +30,16 @@ EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit); EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal); +static DEFINE_SPINLOCK(dma_fence_stub_lock); +static struct dma_fence dma_fence_stub; + /* * fence context counter: each execution context should have its own * fence context, this allows checking if fences belong to the same * context or not. One device can have multiple separate contexts, * and they're used if some engine can run independently of another. */ -static atomic64_t dma_fence_context_counter = ATOMIC64_INIT(0); +static atomic64_t dma_fence_context_counter = ATOMIC64_INIT(1); /** * DOC: DMA fences overview @@ -68,6 +71,37 @@ static atomic64_t dma_fence_context_counter = ATOMIC64_INIT(0); * &dma_buf.resv pointer. */ +static const char *dma_fence_stub_get_name(struct dma_fence *fence) +{ + return "stub"; +} + +static const struct dma_fence_ops dma_fence_stub_ops = { + .get_driver_name = dma_fence_stub_get_name, + .get_timeline_name = dma_fence_stub_get_name, +}; + +/** + * dma_fence_get_stub - return a signaled fence + * + * Return a stub fence which is already signaled. + */ +struct dma_fence *dma_fence_get_stub(void) +{ + spin_lock(&dma_fence_stub_lock); + if (!dma_fence_stub.ops) { + dma_fence_init(&dma_fence_stub, + &dma_fence_stub_ops, + &dma_fence_stub_lock, + 0, 0); + dma_fence_signal_locked(&dma_fence_stub); + } + spin_unlock(&dma_fence_stub_lock); + + return dma_fence_get(&dma_fence_stub); +} +EXPORT_SYMBOL(dma_fence_get_stub); + /** * dma_fence_context_alloc - allocate an array of fence contexts * @num: amount of contexts to allocate diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h index 02dba8cd033d..999e4b104410 100644 --- a/include/linux/dma-fence.h +++ b/include/linux/dma-fence.h @@ -541,6 +541,7 @@ static inline signed long dma_fence_wait(struct dma_fence *fence, bool intr) return ret < 0 ? ret : 0; } +struct dma_fence *dma_fence_get_stub(void); u64 dma_fence_context_alloc(unsigned num); #define DMA_FENCE_TRACE(f, fmt, args...) \ -- 2.14.1

5 14

[PATCH] drm/vc4: Add support for X/Y reflection
by Boris Brezillon 03 Dec '18

03 Dec '18

Add support for X/Y reflection when the plane is using linear or T-tiled formats. X/Y reflection hasn't been tested on SAND formats, so we reject them until proper testing/debugging has been done. Signed-off-by: Boris Brezillon <boris.brezillon(a)bootlin.com> --- drivers/gpu/drm/vc4/vc4_plane.c | 55 ++++++++++++++++++++++++++------- 1 file changed, 44 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c index 75db62cbe468..bdcccf65cde0 100644 --- a/drivers/gpu/drm/vc4/vc4_plane.c +++ b/drivers/gpu/drm/vc4/vc4_plane.c @@ -492,7 +492,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane, bool mix_plane_alpha; bool covers_screen; u32 scl0, scl1, pitch0; - u32 tiling; + u32 tiling, src_y; u32 hvs_format = format->hvs; int ret, i; @@ -520,6 +520,11 @@ static int vc4_plane_mode_set(struct drm_plane *plane, h_subsample = drm_format_horz_chroma_subsampling(format->drm); v_subsample = drm_format_vert_chroma_subsampling(format->drm); + /* We must point to the last line when Y reflection is enabled. */ + src_y = vc4_state->src_y; + if (state->rotation & DRM_MODE_REFLECT_Y) + src_y += vc4_state->src_h[0] - 1; + switch (base_format_mod) { case DRM_FORMAT_MOD_LINEAR: tiling = SCALER_CTL0_TILING_LINEAR; @@ -529,9 +534,10 @@ static int vc4_plane_mode_set(struct drm_plane *plane, * out. */ for (i = 0; i < num_planes; i++) { - vc4_state->offsets[i] += vc4_state->src_y / + vc4_state->offsets[i] += src_y / (i ? v_subsample : 1) * fb->pitches[i]; + vc4_state->offsets[i] += vc4_state->src_x / (i ? h_subsample : 1) * fb->format->cpp[i]; @@ -557,22 +563,38 @@ static int vc4_plane_mode_set(struct drm_plane *plane, u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift); u32 tiles_l = vc4_state->src_x >> tile_w_shift; u32 tiles_r = tiles_w - tiles_l; - u32 tiles_t = vc4_state->src_y >> tile_h_shift; + u32 tiles_t = src_y >> tile_h_shift; /* Intra-tile offsets, which modify the base address (the * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that * base address). */ - u32 tile_y = (vc4_state->src_y >> 4) & 1; - u32 subtile_y = (vc4_state->src_y >> 2) & 3; - u32 utile_y = vc4_state->src_y & 3; + u32 tile_y = (src_y >> 4) & 1; + u32 subtile_y = (src_y >> 2) & 3; + u32 utile_y = src_y & 3; u32 x_off = vc4_state->src_x & tile_w_mask; - u32 y_off = vc4_state->src_y & tile_h_mask; + u32 y_off = src_y & tile_h_mask; + + /* When Y reflection is requested we must set the + * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines + * after the initial one should be fetched in descending order, + * which makes sense since we start from the last line and go + * backward. + * Don't know why we need y_off = max_y_off - y_off, but it's + * definitely required (I guess it's also related to the "going + * backward" situation). + */ + if (state->rotation & DRM_MODE_REFLECT_Y) { + y_off = tile_h_mask - y_off; + pitch0 = SCALER_PITCH0_TILE_LINE_DIR; + } else { + pitch0 = 0; + } tiling = SCALER_CTL0_TILING_256B_OR_T; - pitch0 = (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) | - VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) | - VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) | - VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R)); + pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) | + VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) | + VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) | + VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R)); vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift); vc4_state->offsets[0] += subtile_y << 8; vc4_state->offsets[0] += utile_y << 4; @@ -611,6 +633,11 @@ static int vc4_plane_mode_set(struct drm_plane *plane, } } + if (state->rotation & DRM_MODE_REFLECT_MASK) { + DRM_DEBUG_KMS("X/Y reflection not supported on SAND formats\n"); + return -ENOTSUPP; + } + switch (base_format_mod) { case DRM_FORMAT_MOD_BROADCOM_SAND64: tiling = SCALER_CTL0_TILING_64B; @@ -643,6 +670,8 @@ static int vc4_plane_mode_set(struct drm_plane *plane, /* Control word */ vc4_dlist_write(vc4_state, SCALER_CTL0_VALID | + (state->rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) | + (state->rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) | VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) | (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) | (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) | @@ -1123,6 +1152,10 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev, drm_plane_helper_add(plane, &vc4_plane_helper_funcs); drm_plane_create_alpha_property(plane); + drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, + DRM_MODE_ROTATE_0 | + DRM_MODE_REFLECT_X | + DRM_MODE_REFLECT_Y); return plane; } -- 2.17.1

3 3

[PATCH v2] drm/vc4: Add a debugfs entry to disable/enable the load tracker
by Paul Kocialkowski 03 Dec '18

03 Dec '18

In order to test whether the load tracker is working as expected, we need the ability to compare the commit result with the underrun indication. With the load tracker always enabled, commits that are expected to trigger an underrun are always rejected, so userspace cannot get the actual underrun indication from the hardware. Add a debugfs entry to disable/enable the load tracker, so that a DRM commit expected to trigger an underrun can go through with the load tracker disabled. The underrun indication is then available to userspace and can be checked against the commit result with the load tracker enabled. Signed-off-by: Paul Kocialkowski <paul.kocialkowski(a)bootlin.com> --- Changes since v1: * Moved all the debugfs-related functions and structure to vc4_debugfs.c. drivers/gpu/drm/vc4/vc4_debugfs.c | 58 +++++++++++++++++++++++++++++++ drivers/gpu/drm/vc4/vc4_drv.c | 2 ++ drivers/gpu/drm/vc4/vc4_drv.h | 2 ++ drivers/gpu/drm/vc4/vc4_kms.c | 6 +++- 4 files changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_debugfs.c b/drivers/gpu/drm/vc4/vc4_debugfs.c index 7a0003de71ab..8f4d7fadb226 100644 --- a/drivers/gpu/drm/vc4/vc4_debugfs.c +++ b/drivers/gpu/drm/vc4/vc4_debugfs.c @@ -32,9 +32,67 @@ static const struct drm_info_list vc4_debugfs_list[] = { #define VC4_DEBUGFS_ENTRIES ARRAY_SIZE(vc4_debugfs_list) +static int vc4_debugfs_load_tracker_get(struct seq_file *m, void *data) +{ + struct drm_device *dev = m->private; + struct vc4_dev *vc4 = to_vc4_dev(dev); + + if (vc4->load_tracker_enabled) + seq_printf(m, "enabled\n"); + else + seq_printf(m, "disabled\n"); + + return 0; +} + +static ssize_t vc4_debugfs_load_tracker_set(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_device *dev = m->private; + struct vc4_dev *vc4 = to_vc4_dev(dev); + char buf[32] = {}; + + if (len >= sizeof(buf)) + return -EINVAL; + + if (copy_from_user(buf, ubuf, len)) + return -EFAULT; + + if (!strncasecmp(buf, "enable", 6)) + vc4->load_tracker_enabled = true; + else if (!strncasecmp(buf, "disable", 7)) + vc4->load_tracker_enabled = false; + else + return -EINVAL; + + return len; +} + +static int vc4_debugfs_load_tracker_open(struct inode *inode, struct file *file) +{ + return single_open(file, vc4_debugfs_load_tracker_get, inode->i_private); +} + +static const struct file_operations vc4_debugfs_load_tracker_fops = { + .owner = THIS_MODULE, + .open = vc4_debugfs_load_tracker_open, + .read = seq_read, + .write = vc4_debugfs_load_tracker_set, +}; + int vc4_debugfs_init(struct drm_minor *minor) { + struct dentry *dentry; + + dentry = debugfs_create_file("load_tracker", S_IRUGO | S_IWUSR, + minor->debugfs_root, minor->dev, + &vc4_debugfs_load_tracker_fops); + if (!dentry) + return -ENOMEM; + return drm_debugfs_create_files(vc4_debugfs_list, VC4_DEBUGFS_ENTRIES, minor->debugfs_root, minor); } diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c index 7195a0bcceb3..12ac971d24d6 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.c +++ b/drivers/gpu/drm/vc4/vc4_drv.c @@ -290,6 +290,8 @@ static int vc4_drm_bind(struct device *dev) drm_fbdev_generic_setup(drm, 32); + vc4->load_tracker_enabled = true; + return 0; unbind_all: diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index 11369da944b6..8d0f2f16a9e8 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -188,6 +188,8 @@ struct vc4_dev { int power_refcount; + bool load_tracker_enabled; + /* Mutex controlling the power refcount. */ struct mutex power_lock; diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c index b905a19c1470..4b2509b1b8ed 100644 --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -473,6 +473,7 @@ static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = { static int vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) { + struct vc4_dev *vc4 = to_vc4_dev(dev); int ret; ret = vc4_ctm_atomic_check(dev, state); @@ -483,7 +484,10 @@ vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) if (ret) return ret; - return vc4_load_tracker_atomic_check(state); + if (vc4->load_tracker_enabled) + return vc4_load_tracker_atomic_check(state); + + return 0; } static const struct drm_mode_config_funcs vc4_mode_funcs = { -- 2.19.1

3 6

[Bug 85791] New: nouveau: errors on boot, can't use discrete gpu
by bugzilla-daemon＠bugzilla.kernel.org 03 Dec '18

03 Dec '18

https://bugzilla.kernel.org/show_bug.cgi?id=85791 Bug ID: 85791 Summary: nouveau: errors on boot, can't use discrete gpu Product: Drivers Version: 2.5 Kernel Version: 3.16.4, 3.14.20 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: mezin.alexander(a)gmail.com Regression: No Created attachment 152791 --> https://bugzilla.kernel.org/attachment.cgi?id=152791&action=edit dmesg On boot I see these errors: [ 18.929898] nouveau E[ PBUS][0000:01:00.0] MMIO write of 0x00000002 FAULT at 0x4188ac [ IBUS ] [ 18.931250] nouveau E[ DRM] Pointer to TMDS table invalid [ 18.932395] nouveau E[ DRM] Pointer to flat panel table invalid [ 22.798349] nouveau E[ PGRAPH][0000:01:00.0] HUB_INIT timed out [ 22.798360] nouveau E[ PGRAPH][0000:01:00.0] 409000 - done 0x00000220 [ 22.798373] nouveau E[ PGRAPH][0000:01:00.0] 409000 - stat 0x00000000 0x00000000 0x00000000 0x00000000 [ 22.798384] nouveau E[ PGRAPH][0000:01:00.0] 409000 - stat 0x00000000 0x00000000 0x00000006 0x00000001 [ 22.798389] nouveau E[ PGRAPH][0000:01:00.0] 502000 - done 0x00000300 [ 22.798397] nouveau E[ PGRAPH][0000:01:00.0] 502000 - stat 0x00000000 0x00008c00 0x00000000 0x00000000 [ 22.798404] nouveau E[ PGRAPH][0000:01:00.0] 502000 - stat 0x00000000 0x00000000 0x00000000 0x00000000 [ 22.798406] nouveau E[ PGRAPH][0000:01:00.0] init failed, -16 Full dmesg is attached. When I try to use discrete gpu with DRI_PRIME=1 (after xrandr --setprovideroffloadsink), X crashes. Hardware: 00:02.0 VGA compatible controller: Intel Corporation Haswell-ULT Integrated Graphics Controller (rev 09) 01:00.0 3D controller: NVIDIA Corporation GK107M [GeForce GT 750M] (rev a1) Acer Aspire V5-573G If I remember correctly, some time ago everything worked. -- You are receiving this mail because: You are watching the assignee of the bug.

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[PATCH 0/4] HDCP1.4 fixes
by Ramalingam C 03 Dec '18

03 Dec '18

Couple of more HDCP1.4 fixes on - Key load process for CFL - Encryption status change time - debug log addition - active platform coverage Ramalingam C (4): drm/i915: Fix GEN9 HDCP1.4 key load process drm/i915: Fix platform coverage for HDCP1.4 drm/i915: debug log for REPLY_ACK missing drm/i915: Increase timeout for Encrypt status change drivers/gpu/drm/i915/intel_dp.c | 6 +++++- drivers/gpu/drm/i915/intel_hdcp.c | 17 ++++++++++------- 2 files changed, 15 insertions(+), 8 deletions(-) -- 2.7.4

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dri-devel December 2018