dri-devel March 2018

dri-devel@lists.freedesktop.org

263 participants
1856 discussions

[PATCH] drm/meson: Add support for DMT modes on HDMI
by Neil Armstrong 08 Mar '18

08 Mar '18

This patch adds support for DMT display modes over HDMI. The modes timings configurations are from the Amlogic Vendor linux tree and tested over multiples monitors. Previously only a selected number of CEA modes were supported. Only these following modes are supported with these changes: - 640x480@60Hz - 800x600@60Hz - 1024x768@60Hz - 1152x864@75Hz - 1280x1024@60Hz - 1600x1200@60Hz - 1920x1080@60Hz The associated code to handle the clock rates is also added. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 21 +- drivers/gpu/drm/meson/meson_vclk.c | 219 ++++++++++++++++++++- drivers/gpu/drm/meson/meson_venc.c | 347 +++++++++++++++++++++++++++++++++- drivers/gpu/drm/meson/meson_venc.h | 1 + 4 files changed, 570 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index 17de3af..fd1d365 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -554,12 +554,12 @@ dw_hdmi_mode_valid(struct drm_connector *connector, mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal, mode->type, mode->flags); - /* For now, only accept VIC modes */ - if (!vic) - return MODE_BAD; - - /* For now, filter by supported VIC modes */ - if (!meson_venc_hdmi_supported_vic(vic)) + /* Check against non-VIC supported modes */ + if (!vic) { + if (!meson_venc_hdmi_supported_mode(mode)) + return MODE_BAD; + /* Check against supported VIC modes */ + } else if (meson_venc_hdmi_supported_vic(vic)) return MODE_BAD; vclk_freq = mode->clock; @@ -585,9 +585,14 @@ dw_hdmi_mode_valid(struct drm_connector *connector, /* Finally filter by configurable vclk frequencies */ switch (vclk_freq) { + case 25175: + case 40000: case 54000: + case 65000: case 74250: + case 108000: case 148500: + case 162000: case 297000: case 594000: return MODE_OK; @@ -652,10 +657,6 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder, DRM_DEBUG_DRIVER("%d:\"%s\" vic %d\n", mode->base.id, mode->name, vic); - /* Should have been filtered */ - if (!vic) - return; - /* VENC + VENC-DVI Mode setup */ meson_venc_hdmi_mode_set(priv, vic, mode); diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index 4767704..f051122 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -328,14 +328,24 @@ static void meson_venci_cvbs_clock_config(struct meson_drm *priv) #define MESON_VCLK_HDMI_DDR_54000 2 /* 2970 /4 /1 /1 /5 /1 => /1 /2 */ #define MESON_VCLK_HDMI_DDR_148500 3 +/* 4028 /4 /4 /1 /5 /2 => /1 /1 */ +#define MESON_VCLK_HDMI_25175 4 +/* 3200 /4 /2 /1 /5 /2 => /1 /1 */ +#define MESON_VCLK_HDMI_40000 5 +/* 5200 /4 /2 /1 /5 /2 => /1 /1 */ +#define MESON_VCLK_HDMI_65000 6 /* 2970 /2 /2 /2 /5 /1 => /1 /1 */ -#define MESON_VCLK_HDMI_74250 4 +#define MESON_VCLK_HDMI_74250 7 +/* 4320 /4 /1 /1 /5 /2 => /1 /1 */ +#define MESON_VCLK_HDMI_108000 8 /* 2970 /1 /2 /2 /5 /1 => /1 /1 */ -#define MESON_VCLK_HDMI_148500 5 +#define MESON_VCLK_HDMI_148500 9 +/* 3240 /2 /1 /1 /5 /2 => /1 /1 */ +#define MESON_VCLK_HDMI_162000 10 /* 2970 /1 /1 /1 /5 /2 => /1 /1 */ -#define MESON_VCLK_HDMI_297000 6 +#define MESON_VCLK_HDMI_297000 11 /* 5940 /1 /1 /2 /5 /1 => /1 /1 */ -#define MESON_VCLK_HDMI_594000 7 +#define MESON_VCLK_HDMI_594000 12 struct meson_vclk_params { unsigned int pll_base_freq; @@ -401,6 +411,46 @@ struct meson_vclk_params { .vid_pll_div = VID_PLL_DIV_5, .vclk_div = 1, }, + [MESON_VCLK_HDMI_25175] = { + .pll_base_freq = 4028000, + .pll_od1 = 4, + .pll_od2 = 4, + .pll_od3 = 1, + .vid_pll_div = VID_PLL_DIV_5, + .vclk_div = 2, + }, + [MESON_VCLK_HDMI_40000] = { + .pll_base_freq = 3200000, + .pll_od1 = 4, + .pll_od2 = 2, + .pll_od3 = 1, + .vid_pll_div = VID_PLL_DIV_5, + .vclk_div = 2, + }, + [MESON_VCLK_HDMI_65000] = { + .pll_base_freq = 5200000, + .pll_od1 = 4, + .pll_od2 = 2, + .pll_od3 = 1, + .vid_pll_div = VID_PLL_DIV_5, + .vclk_div = 2, + }, + [MESON_VCLK_HDMI_108000] = { + .pll_base_freq = 4320000, + .pll_od1 = 4, + .pll_od2 = 1, + .pll_od3 = 1, + .vid_pll_div = VID_PLL_DIV_5, + .vclk_div = 2, + }, + [MESON_VCLK_HDMI_162000] = { + .pll_base_freq = 3240000, + .pll_od1 = 2, + .pll_od2 = 1, + .pll_od3 = 1, + .vid_pll_div = VID_PLL_DIV_5, + .vclk_div = 2, + }, }; static inline unsigned int pll_od_to_reg(unsigned int od) @@ -451,6 +501,90 @@ void meson_hdmi_pll_set(struct meson_drm *priv, 0xFFFF, 0x4e00); break; + case 3200000: + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000242); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); + + /* unreset */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + BIT(28), 0); + + /* Poll for lock bit */ + regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, + val, (val & HDMI_PLL_LOCK), 10, 0); + + /* div_frac */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, + 0xFFFF, 0x4aab); + break; + + case 3240000: + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000243); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); + + /* unreset */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + BIT(28), 0); + + /* Poll for lock bit */ + regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, + val, (val & HDMI_PLL_LOCK), 10, 0); + + /* div_frac */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, + 0xFFFF, 0x4800); + break; + + case 3865000: + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000250); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); + + /* unreset */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + BIT(28), 0); + + /* Poll for lock bit */ + regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, + val, (val & HDMI_PLL_LOCK), 10, 0); + + /* div_frac */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, + 0xFFFF, 0x4855); + break; + + case 4028000: + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000253); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); + + /* unreset */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + BIT(28), 0); + + /* Poll for lock bit */ + regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, + val, (val & HDMI_PLL_LOCK), 10, 0); + + /* div_frac */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, + 0xFFFF, 0x4eab); + break; + case 4320000: regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800025a); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000); @@ -485,6 +619,23 @@ void meson_hdmi_pll_set(struct meson_drm *priv, regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, (val & HDMI_PLL_LOCK), 10, 0); break; + + case 5200000: + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800026c); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x135c5091); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); + + /* unreset */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + BIT(28), 0); + + /* Poll for lock bit */ + regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, + val, (val & HDMI_PLL_LOCK), 10, 0); + break; }; } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) { @@ -498,6 +649,42 @@ void meson_hdmi_pll_set(struct meson_drm *priv, regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); break; + case 3200000: + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000285); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb155); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); + break; + + case 3240000: + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000287); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); + break; + + case 3865000: + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002a1); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb02b); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); + break; + + case 4028000: + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002a7); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb355); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); + break; + case 4320000: regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002b4); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000); @@ -516,6 +703,15 @@ void meson_hdmi_pll_set(struct meson_drm *priv, regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); break; + case 5200000: + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002d8); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb2ab); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); + break; + }; /* Reset PLL */ @@ -590,15 +786,30 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, else freq = MESON_VCLK_HDMI_DDR_54000; break; + case 25175: + freq = MESON_VCLK_HDMI_25175; + break; + case 40000: + freq = MESON_VCLK_HDMI_40000; + break; + case 65000: + freq = MESON_VCLK_HDMI_65000; + break; case 74250: freq = MESON_VCLK_HDMI_74250; break; + case 108000: + freq = MESON_VCLK_HDMI_108000; + break; case 148500: if (dac_freq != 148500) freq = MESON_VCLK_HDMI_DDR_148500; else freq = MESON_VCLK_HDMI_148500; break; + case 162000: + freq = MESON_VCLK_HDMI_162000; + break; case 297000: freq = MESON_VCLK_HDMI_297000; break; diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c index 9509017..6e27013 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -697,6 +697,314 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = { }, }; +union meson_hdmi_venc_mode meson_hdmi_encp_mode_640x480_60 = { + .encp = { + .dvi_settings = 0x21, + .video_mode = 0x4040, + .video_mode_adv = 0x18, + /* video_prog_mode */ + /* video_sync_mode */ + /* video_yc_dly */ + /* video_rgb_ctrl */ + /* video_filt_ctrl */ + /* video_ofld_voav_ofst */ + /* yfp1_htime */ + /* yfp2_htime */ + .max_pxcnt = 0x31f, + /* hspuls_begin */ + /* hspuls_end */ + /* hspuls_switch */ + /* vspuls_begin */ + /* vspuls_end */ + /* vspuls_bline */ + /* vspuls_eline */ + .havon_begin = 0x90, + .havon_end = 0x30f, + .vavon_bline = 0x23, + .vavon_eline = 0x202, + /* eqpuls_begin */ + /* eqpuls_end */ + /* eqpuls_bline */ + /* eqpuls_eline */ + .hso_begin = 0, + .hso_end = 0x60, + .vso_begin = 0x1e, + .vso_end = 0x32, + .vso_bline = 0, + .vso_eline = 2, + .vso_eline_present = true, + /* sy_val */ + /* sy2_val */ + .max_lncnt = 0x20c, + }, +}; + +union meson_hdmi_venc_mode meson_hdmi_encp_mode_800x600_60 = { + .encp = { + .dvi_settings = 0x21, + .video_mode = 0x4040, + .video_mode_adv = 0x18, + /* video_prog_mode */ + /* video_sync_mode */ + /* video_yc_dly */ + /* video_rgb_ctrl */ + /* video_filt_ctrl */ + /* video_ofld_voav_ofst */ + /* yfp1_htime */ + /* yfp2_htime */ + .max_pxcnt = 0x41f, + /* hspuls_begin */ + /* hspuls_end */ + /* hspuls_switch */ + /* vspuls_begin */ + /* vspuls_end */ + /* vspuls_bline */ + /* vspuls_eline */ + .havon_begin = 0xD8, + .havon_end = 0x3f7, + .vavon_bline = 0x1b, + .vavon_eline = 0x272, + /* eqpuls_begin */ + /* eqpuls_end */ + /* eqpuls_bline */ + /* eqpuls_eline */ + .hso_begin = 0, + .hso_end = 0x80, + .vso_begin = 0x1e, + .vso_end = 0x32, + .vso_bline = 0, + .vso_eline = 4, + .vso_eline_present = true, + /* sy_val */ + /* sy2_val */ + .max_lncnt = 0x273, + }, +}; + +union meson_hdmi_venc_mode meson_hdmi_encp_mode_1024x768_60 = { + .encp = { + .dvi_settings = 0x21, + .video_mode = 0x4040, + .video_mode_adv = 0x18, + /* video_prog_mode */ + /* video_sync_mode */ + /* video_yc_dly */ + /* video_rgb_ctrl */ + /* video_filt_ctrl */ + /* video_ofld_voav_ofst */ + /* yfp1_htime */ + /* yfp2_htime */ + .max_pxcnt = 1343, + /* hspuls_begin */ + /* hspuls_end */ + /* hspuls_switch */ + /* vspuls_begin */ + /* vspuls_end */ + /* vspuls_bline */ + /* vspuls_eline */ + .havon_begin = 296, + .havon_end = 1319, + .vavon_bline = 35, + .vavon_eline = 802, + /* eqpuls_begin */ + /* eqpuls_end */ + /* eqpuls_bline */ + /* eqpuls_eline */ + .hso_begin = 0, + .hso_end = 136, + .vso_begin = 30, + .vso_end = 50, + .vso_bline = 0, + .vso_eline = 6, + .vso_eline_present = true, + /* sy_val */ + /* sy2_val */ + .max_lncnt = 805, + }, +}; + +union meson_hdmi_venc_mode meson_hdmi_encp_mode_1152x864_75 = { + .encp = { + .dvi_settings = 0x21, + .video_mode = 0x4040, + .video_mode_adv = 0x18, + /* video_prog_mode */ + /* video_sync_mode */ + /* video_yc_dly */ + /* video_rgb_ctrl */ + /* video_filt_ctrl */ + /* video_ofld_voav_ofst */ + /* yfp1_htime */ + /* yfp2_htime */ + .max_pxcnt = 0x63f, + /* hspuls_begin */ + /* hspuls_end */ + /* hspuls_switch */ + /* vspuls_begin */ + /* vspuls_end */ + /* vspuls_bline */ + /* vspuls_eline */ + .havon_begin = 0x180, + .havon_end = 0x5ff, + .vavon_bline = 0x23, + .vavon_eline = 0x382, + /* eqpuls_begin */ + /* eqpuls_end */ + /* eqpuls_bline */ + /* eqpuls_eline */ + .hso_begin = 0, + .hso_end = 0x80, + .vso_begin = 0x1e, + .vso_end = 0x32, + .vso_bline = 0, + .vso_eline = 3, + .vso_eline_present = true, + /* sy_val */ + /* sy2_val */ + .max_lncnt = 0x383, + }, +}; + +union meson_hdmi_venc_mode meson_hdmi_encp_mode_1280x1024_60 = { + .encp = { + .dvi_settings = 0x21, + .video_mode = 0x4040, + .video_mode_adv = 0x18, + /* video_prog_mode */ + /* video_sync_mode */ + /* video_yc_dly */ + /* video_rgb_ctrl */ + /* video_filt_ctrl */ + /* video_ofld_voav_ofst */ + /* yfp1_htime */ + /* yfp2_htime */ + .max_pxcnt = 0x697, + /* hspuls_begin */ + /* hspuls_end */ + /* hspuls_switch */ + /* vspuls_begin */ + /* vspuls_end */ + /* vspuls_bline */ + /* vspuls_eline */ + .havon_begin = 0x168, + .havon_end = 0x667, + .vavon_bline = 0x29, + .vavon_eline = 0x428, + /* eqpuls_begin */ + /* eqpuls_end */ + /* eqpuls_bline */ + /* eqpuls_eline */ + .hso_begin = 0, + .hso_end = 0x70, + .vso_begin = 0x1e, + .vso_end = 0x32, + .vso_bline = 0, + .vso_eline = 3, + .vso_eline_present = true, + /* sy_val */ + /* sy2_val */ + .max_lncnt = 0x429, + }, +}; + +union meson_hdmi_venc_mode meson_hdmi_encp_mode_1600x1200_60 = { + .encp = { + .dvi_settings = 0x21, + .video_mode = 0x4040, + .video_mode_adv = 0x18, + /* video_prog_mode */ + /* video_sync_mode */ + /* video_yc_dly */ + /* video_rgb_ctrl */ + /* video_filt_ctrl */ + /* video_ofld_voav_ofst */ + /* yfp1_htime */ + /* yfp2_htime */ + .max_pxcnt = 0x86f, + /* hspuls_begin */ + /* hspuls_end */ + /* hspuls_switch */ + /* vspuls_begin */ + /* vspuls_end */ + /* vspuls_bline */ + /* vspuls_eline */ + .havon_begin = 0x1f0, + .havon_end = 0x82f, + .vavon_bline = 0x31, + .vavon_eline = 0x4e0, + /* eqpuls_begin */ + /* eqpuls_end */ + /* eqpuls_bline */ + /* eqpuls_eline */ + .hso_begin = 0, + .hso_end = 0xc0, + .vso_begin = 0x1e, + .vso_end = 0x32, + .vso_bline = 0, + .vso_eline = 3, + .vso_eline_present = true, + /* sy_val */ + /* sy2_val */ + .max_lncnt = 0x4e1, + }, +}; + +struct meson_hdmi_venc_dmt_mode { + struct drm_display_mode drm_mode; + union meson_hdmi_venc_mode *mode; +} meson_hdmi_venc_dmt_modes[] = { + /* 640x480@60Hz */ + { + { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, + 752, 800, 0, 480, 490, 492, 525, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + &meson_hdmi_encp_mode_640x480_60, + }, + /* 800x600@60Hz */ + { + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, + 968, 1056, 0, 600, 601, 605, 628, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + &meson_hdmi_encp_mode_800x600_60, + }, + /* 1024x768@60Hz */ + { + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, + 1048, 1184, 1344, 0, 768, 771, 777, 806, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + &meson_hdmi_encp_mode_1024x768_60, + }, + /* 1152x864@75Hz */ + { + { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, + 1216, 1344, 1600, 0, 864, 865, 868, 900, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + &meson_hdmi_encp_mode_1152x864_75, + }, + /* 1280x1024@60Hz */ + { + { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, + 1328, 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + &meson_hdmi_encp_mode_1280x1024_60, + }, + /* 1600x1200@60Hz */ + { + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, + 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + &meson_hdmi_encp_mode_1600x1200_60, + }, + /* 1920x1080@60Hz */ + { + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, + 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + &meson_hdmi_encp_mode_1080p60 + }, + { }, /* sentinel */ +}; + struct meson_hdmi_venc_vic_mode { unsigned int vic; union meson_hdmi_venc_mode *mode; @@ -736,6 +1044,20 @@ static unsigned long modulo(unsigned long a, unsigned long b) return a; } +bool meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode) +{ + struct meson_hdmi_venc_dmt_mode *vmode = meson_hdmi_venc_dmt_modes; + + while (vmode->mode) { + if (drm_mode_equal(&vmode->drm_mode, mode)) + return true; + vmode++; + } + + return false; +} +EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode); + bool meson_venc_hdmi_supported_vic(int vic) { struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes; @@ -750,6 +1072,20 @@ bool meson_venc_hdmi_supported_vic(int vic) } EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic); +static union meson_hdmi_venc_mode +*meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode) +{ + struct meson_hdmi_venc_dmt_mode *vmode = meson_hdmi_venc_dmt_modes; + + while (vmode->mode) { + if (drm_mode_equal(&vmode->drm_mode, mode)) + return vmode->mode; + vmode++; + } + + return NULL; +} + static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic) { struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes; @@ -811,10 +1147,13 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, unsigned int sof_lines; unsigned int vsync_lines; - vmode = meson_venc_hdmi_get_vic_vmode(vic); + if (meson_venc_hdmi_supported_vic(vic)) + vmode = meson_venc_hdmi_get_vic_vmode(vic); + else + vmode = meson_venc_hdmi_get_dmt_vmode(mode); if (!vmode) { - dev_err(priv->dev, "%s: Fatal Error, unsupported vic %d\n", - __func__, vic); + dev_err(priv->dev, "%s: Fatal Error, unsupported mode " + DRM_MODE_FMT "\n", __func__, DRM_MODE_ARG(mode)); return; } @@ -864,7 +1203,7 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, hsync_pixels_venc *= 2; /* Disable VDACs */ - writel_bits_relaxed(0x1f, 0x1f, + writel_bits_relaxed(0xff, 0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h index a1b96e8..7c18a36 100644 --- a/drivers/gpu/drm/meson/meson_venc.h +++ b/drivers/gpu/drm/meson/meson_venc.h @@ -58,6 +58,7 @@ struct meson_cvbs_enci_mode { }; /* HDMI Clock parameters */ +bool meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode); bool meson_venc_hdmi_supported_vic(int vic); bool meson_venc_hdmi_venc_repeat(int vic); -- 2.7.4

1 0

[Bug 99859] Glamor Crashes on big endian Hardware
by bugzilla-daemon＠freedesktop.org 08 Mar '18

08 Mar '18

https://bugs.freedesktop.org/show_bug.cgi?id=99859 --- Comment #23 from erhard_f(a)mailbox.org --- Tried Glamor on a more recent xorg stack on my PM G5 11,2 which works perfectly well! It's on a Radeon HD 6450 however, so a r600 card and not a radeonsi as the HD 7750. I am running: sys-kernel/gentoo-sources-4.9.85 x11-libs/libdrm-2.4.90 x11-drivers/xf86-video-ati-7.10.0 media-libs/mesa-18.0.0_rc4 [ 153.370] (--) Depth 24 pixmap format is 32 bpp [ 153.372] (II) RADEON(0): [DRI2] Setup complete [ 153.372] (II) RADEON(0): [DRI2] DRI driver: r600 [ 153.372] (II) RADEON(0): [DRI2] VDPAU driver: r600 [ 153.374] (II) RADEON(0): Front buffer size: 8160K [ 153.374] (II) RADEON(0): VRAM usage limit set to 218116K [ 153.378] (II) RADEON(0): SYNC extension fences enabled [ 153.379] (II) RADEON(0): Present extension enabled [ 153.379] (==) RADEON(0): DRI3 enabled [ 153.379] (==) RADEON(0): Backing store enabled [ 153.379] (II) RADEON(0): Direct rendering enabled [ 153.484] (II) RADEON(0): Use GLAMOR acceleration. [ 153.485] (II) RADEON(0): Acceleration enabled [ 153.485] (==) RADEON(0): DPMS enabled [ 153.485] (==) RADEON(0): Silken mouse enabled [ 153.485] (II) RADEON(0): Set up textured video (glamor) [ 153.485] (II) RADEON(0): [XvMC] Associated with GLAMOR Textured Video. [ 153.485] (II) RADEON(0): [XvMC] Extension initialized. [ 153.485] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message. [ 153.487] (--) RandR disabled [ 153.492] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer [ 153.492] (II) AIGLX: enabled GLX_ARB_create_context [ 153.492] (II) AIGLX: enabled GLX_ARB_create_context_profile [ 153.492] (II) AIGLX: enabled GLX_EXT_create_context_es{,2}_profile [ 153.492] (II) AIGLX: enabled GLX_INTEL_swap_event [ 153.492] (II) AIGLX: enabled GLX_SGI_swap_control [ 153.492] (II) AIGLX: enabled GLX_EXT_framebuffer_sRGB [ 153.492] (II) AIGLX: enabled GLX_ARB_fbconfig_float [ 153.492] (II) AIGLX: enabled GLX_EXT_fbconfig_packed_float [ 153.492] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects [ 153.492] (II) AIGLX: enabled GLX_ARB_create_context_robustness [ 153.494] (II) AIGLX: Loaded and initialized r600 [ 153.494] (II) GLX: Initialized DRI2 GL provider for screen 0 [ 153.498] (II) RADEON(0): Setting screen physical size to 508 x 285 Only downside at the moment is that I need to run a 4.9.x kernel to get 2D/3D acceleration 'cause of bug #99851. -- You are receiving this mail because: You are the assignee for the bug.

1 0

[PATCH libdrm] freedreno: add missing symbols to symbol-check
by Eric Engestrom 08 Mar '18

08 Mar '18

Fixes: 1384c081233751569473 "freedreno: add interface to get buffer address" Signed-off-by: Eric Engestrom <eric.engestrom(a)imgtec.com> --- freedreno/freedreno-symbol-check | 2 ++ 1 file changed, 2 insertions(+) diff --git a/freedreno/freedreno-symbol-check b/freedreno/freedreno-symbol-check index 56e3d3eeace6f9deb280..3b119528c6cfbfd9d4a0 100755 --- a/freedreno/freedreno-symbol-check +++ b/freedreno/freedreno-symbol-check @@ -18,10 +18,12 @@ fd_bo_from_dmabuf fd_bo_from_fbdev fd_bo_from_handle fd_bo_from_name +fd_bo_get_iova fd_bo_get_name fd_bo_handle fd_bo_map fd_bo_new +fd_bo_put_iova fd_bo_ref fd_bo_size fd_device_del -- Cheers, Eric

3 2

nouveau 30bpp / deep color status
by Ilia Mirkin 08 Mar '18

08 Mar '18

In case anyone's curious about 30bpp framebuffer support, here's the current status: Kernel: Ben and I have switched the code to using a 256-based LUT for Kepler+, and I've also written a patch to cause the addfb ioctl to use the proper format. You can pick this up at: https://github.com/skeggsb/linux/commits/linux-4.16 (note the branch!) https://patchwork.freedesktop.org/patch/202322/ With these two, you should be able to use "X -depth 30" again on any G80+ GPU to bring up a screen (as you could in kernel 4.9 and earlier). However this still has some deficiencies, some of which I've addressed: xf86-video-nouveau: DRI3 was broken, and Xv was broken. Patches available at: https://github.com/imirkin/xf86-video-nouveau/commits/master mesa: The NVIDIA hardware (pre-Kepler) can only do XBGR scanout. Further the nouveau KMS doesn't add XRGB scanout for Kepler+ (although it could). Mesa was only enabled for XRGB, so I've piped XBGR through all the same places: https://github.com/imirkin/mesa/commits/30bpp libdrm: For testing, I added a modetest gradient pattern split horizontally. Top half is 10bpc, bottom half is 8bpc. This is useful for seeing whether you're really getting 10bpc, or if things are getting truncated along the way. Definitely hacky, but ... wasn't intending on upstreaming it anyways: https://github.com/imirkin/drm/commit/9b8776f58448b5745675c3a7f5eb2735e3989… ------------------------------------- Results with the patches (tested on a GK208B and a "deep color" TV over HDMI): - modetest with a 10bpc gradient shows up smoother than an 8bpc gradient. However it's still dithered to 8bpc, not "real" 10bpc. - things generally work in X -- dri2 and dri3, xv, and obviously regular X rendering / acceleration - lots of X software can't handle 30bpp modes (mplayer hates it for xv and x11 rendering, aterm bails on shading the root pixmap, probably others) I'm also told that with DP, it should actually send the higher-bpc data over the wire. With HDMI, we're still stuck at 24bpp for now (although the hardware can do 36bpp as well). This is why my gradient result above was still dithered. Things to do - mostly nouveau specific, but probably some general infra needed too: - Figure out how to properly expose the 1024-sized LUT - Add fp16 scanout - Stop relying on the max bpc of the monitor/connector and make decisions based on the "effective" bpc (e.g. based on the currently-set fb format, take hdmi/dp into account, etc). This will also affect the max clock somehow. Perhaps there should be a way to force a connector to a certain bpc. - Add higher-bpc HDMI support - Add 10bpc dithering (only makes sense if >= 10bpc output is *actually* enabled first) - Investigate YUV HDMI modes (esp since they can enable 4K@60 on HDMI 1.4 hardware) - Test out Wayland compositors - Teach xf86-video-modesetting about addfb2 or that nouveau's ordering is different. I don't necessarily plan on working further on this, so if there are interested parties, they should definitely try to pick it up. I'll try to upstream all my changes though. Cheers, -ilia

4 9

[PATCH] video: fbdev: via_aux_vt1632: remove VLA usage
by Gustavo A. R. Silva 08 Mar '18

08 Mar '18

In preparation to enabling -Wvla, remove VLA and replace it with a fixed-length array instead. Also, remove variable 'len'. Notice that no new IDs have been added in seven years. Signed-off-by: Gustavo A. R. Silva <gustavo(a)embeddedor.com> --- drivers/video/fbdev/via/via_aux_vt1632.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/video/fbdev/via/via_aux_vt1632.c b/drivers/video/fbdev/via/via_aux_vt1632.c index d24f4cd..0cd0d2a 100644 --- a/drivers/video/fbdev/via/via_aux_vt1632.c +++ b/drivers/video/fbdev/via/via_aux_vt1632.c @@ -35,10 +35,10 @@ static void probe(struct via_aux_bus *bus, u8 addr) .addr = addr, .name = name}; /* check vendor id and device id */ - const u8 id[] = {0x06, 0x11, 0x92, 0x31}, len = ARRAY_SIZE(id); - u8 tmp[len]; + const u8 id[4] = {0x06, 0x11, 0x92, 0x31}; + u8 tmp[4]; - if (!via_aux_read(&drv, 0x00, tmp, len) || memcmp(id, tmp, len)) + if (!via_aux_read(&drv, 0x00, tmp, 4) || memcmp(id, tmp, 4)) return; printk(KERN_INFO "viafb: Found %s at address 0x%x\n", name, addr); -- 2.7.4

3 2

[PATCH v9 0/5] rockchip: kevin: Enable edp display
by Enric Balletbo i Serra 08 Mar '18

08 Mar '18

Hi, Actually the name of this patch series is not really true as the edp display is working, but to not confuse I decided to maintain it. Now this patchset is more a group of cleanups, the patchset has been originally posted by Jeffy Chen and the 2 first commits from a previous version (v6) are already merged in mainline. In v8, four patches more landed. And this version are the remaining patches. Regards, Enric Changes in v9: - The following patches from v8 has been applied: - [PATCH v8 1/8] drm/bridge: analogix: Do not use device's drvdata - [PATCH v8 2/8] drm/bridge: analogix_dp: Fix connector and encoder cleanup - [PATCH v8 3/8] drm/rockchip: analogix_dp: Add a sanity check for rockchip_drm_psr_register() - The following patches from v8 has been superseeded. - [PATCH v8 7/8] drm/bridge/synopsys: dw-hdmi: Do not use device's drvdata - Superseeded by https://cgit.freedesktop.org/drm/drm-misc/commit/?id=eea034af90c64802fd747a… - Moved clk_disable_unprepare reordering in unbin to separate patch. - Added new patch to reorder clk_disable_unprepare call in inno_hdmi unbind() - dw_hdmi: Rewrite the commit message to reflect the change. Jeffy Chen (5): drm/rockchip: dw-mipi-dsi: Fix connector and encoder cleanup. drm/rockchip: inno_hdmi: Fix error handling path. drm/rockchip: inno_hdmi: reorder clk_disable_unprepare call in unbind drm/rockchip: dw_hdmi: Move HDMI vpll clock enable to bind() drm/bridge/synopsys: dw-hdmi: Add missing bridge detach drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 8 ++++++++ drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 8 ++++++-- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 17 +++++++++-------- drivers/gpu/drm/rockchip/inno_hdmi.c | 22 +++++++++++++++++----- 4 files changed, 40 insertions(+), 15 deletions(-) -- 2.16.1

4 12

[PATCH] drm/nouveau: Replace the iturbt_709 prop with the standarad COLOR_ENCODNIG prop
by Ville Syrjala 08 Mar '18

08 Mar '18

From: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Replace the ad-hoc iturbt_709 property with the new standard COLOR_ENCODING property. Compiles, but not tested. Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: nouveau(a)lists.freedesktop.org Cc: Ben Skeggs <bskeggs(a)redhat.com> Cc: Ilia Mirkin <imirkin(a)alum.mit.edu> Signed-off-by: Ville Syrjälä <ville.syrjala(a)linux.intel.com> --- drivers/gpu/drm/nouveau/dispnv04/overlay.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c index c8c2333f24ee..df4358e31075 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c @@ -46,7 +46,6 @@ struct nouveau_plane { struct drm_property *brightness; struct drm_property *hue; struct drm_property *saturation; - struct drm_property *iturbt_709; } props; int colorkey; @@ -54,7 +53,7 @@ struct nouveau_plane { int brightness; int hue; int saturation; - int iturbt_709; + enum drm_color_encoding color_encoding; void (*set_params)(struct nouveau_plane *); }; @@ -166,7 +165,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, if (fb->format->format == DRM_FORMAT_NV12 || fb->format->format == DRM_FORMAT_NV21) format |= NV_PVIDEO_FORMAT_PLANAR; - if (nv_plane->iturbt_709) + if (nv_plane->color_encoding == DRM_COLOR_YCBCR_BT709) format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; if (nv_plane->colorkey & (1 << 24)) format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; @@ -229,7 +228,7 @@ nv10_set_params(struct nouveau_plane *plane) nvif_wr32(dev, NV_PVIDEO_COLOR_KEY, plane->colorkey & 0xffffff); if (plane->cur) { - if (plane->iturbt_709) + if (plane->color_encoding == DRM_COLOR_YCBCR_BT709) format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; if (plane->colorkey & (1 << 24)) format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; @@ -258,8 +257,8 @@ nv_set_property(struct drm_plane *plane, nv_plane->hue = value; else if (property == nv_plane->props.saturation) nv_plane->saturation = value; - else if (property == nv_plane->props.iturbt_709) - nv_plane->iturbt_709 = value; + else if (property == nv_plane->base.color_encoding_property) + nv_plane->color_encoding = value; else return -EINVAL; @@ -313,14 +312,11 @@ nv10_overlay_init(struct drm_device *device) device, 0, "hue", 0, 359); plane->props.saturation = drm_property_create_range( device, 0, "saturation", 0, 8192 - 1); - plane->props.iturbt_709 = drm_property_create_range( - device, 0, "iturbt_709", 0, 1); if (!plane->props.colorkey || !plane->props.contrast || !plane->props.brightness || !plane->props.hue || - !plane->props.saturation || - !plane->props.iturbt_709) + !plane->props.saturation) goto cleanup; plane->colorkey = 0; @@ -343,9 +339,13 @@ nv10_overlay_init(struct drm_device *device) drm_object_attach_property(&plane->base.base, plane->props.saturation, plane->saturation); - plane->iturbt_709 = 0; - drm_object_attach_property(&plane->base.base, - plane->props.iturbt_709, plane->iturbt_709); + plane->color_encoding = DRM_COLOR_YCBCR_BT601; + drm_plane_create_color_properties(&plane->base, + BIT(DRM_COLOR_YCBCR_BT601) | + BIT(DRM_COLOR_YCBCR_BT709), + BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), + DRM_COLOR_YCBCR_BT601, + DRM_COLOR_YCBCR_LIMITED_RANGE); plane->set_params = nv10_set_params; nv10_set_params(plane); -- 2.13.6

4 6

[Bug 28433] Mesa DRI Intel 845G GEM Drivers returning artifacts in textures that can lockup PC on glxSwapBuffers.
by bugzilla-daemon＠freedesktop.org 08 Mar '18

08 Mar '18

https://bugs.freedesktop.org/show_bug.cgi?id=28433 --- Comment #4 from Gert Wollny <gw.fossdev(a)gmail.com> --- I can't see any artefacts on i915 with GM45. In fact there the rendering looks better then with the llvmpipe software renderer and r600. These two create over-bright pixels that are not present with i915. Versions tested: - i915 and llvmpipe: Mesa 13.0.6 - r600 and llvmpipe: Mesa 18.1.0-devel (git-dcd8730445 -- You are receiving this mail because: You are the assignee for the bug.

1 0

[PATCH 0/5] HDCP1.4 fixes
by Ramalingam C 08 Mar '18

08 Mar '18

This series addresses the requriement of below HDCP compliance tests DP: 1A-06 and 1B-05 HDMI: 1A-04 and 1A-07a One of the patch uses the I915 power infra-structure for checking the power state of PW#1. Which enables the init path for all legacy platforms. And encoder specific msg availability detection is moved into hdcp_shim. This will help to sync with DP hdcp data availability in the best possible way by fielding the CP_IRQ. Ramalingam C (5): drm/i915: Read HDCP R0 thrice in case of mismatch drm/i915: read Vprime thrice incase of mismatch drm/i915: Check hdcp key loadability drm/i915: Poll hdcp register on sudden NACK drm/i915: Move hdcp msg detection into shim drivers/gpu/drm/i915/intel_dp.c | 70 ++++++++++++++-- drivers/gpu/drm/i915/intel_drv.h | 6 +- drivers/gpu/drm/i915/intel_hdcp.c | 166 +++++++++++++++++++++++++++----------- drivers/gpu/drm/i915/intel_hdmi.c | 28 ++++++- 4 files changed, 214 insertions(+), 56 deletions(-) -- 2.7.4

4 18

[PATCH 1/6] drm/ttm: add ttm_bo_pipeline_gutting
by Christian König 08 Mar '18

08 Mar '18

Allows us to gut a BO of it's backing store when the driver says that it isn't needed any more. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/gpu/drm/ttm/ttm_bo.c | 15 ++++++++++++--- drivers/gpu/drm/ttm/ttm_bo_util.c | 24 ++++++++++++++++++++++++ include/drm/ttm/ttm_bo_driver.h | 9 +++++++++ 3 files changed, 45 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index ad142a92eb80..98e06f8bf23b 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -622,14 +622,23 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, reservation_object_assert_held(bo->resv); + placement.num_placement = 0; + placement.num_busy_placement = 0; + bdev->driver->evict_flags(bo, &placement); + + if (!placement.num_placement && !placement.num_busy_placement) { + ret = ttm_bo_pipeline_gutting(bo); + if (ret) + return ret; + + return ttm_tt_create(bo, false); + } + evict_mem = bo->mem; evict_mem.mm_node = NULL; evict_mem.bus.io_reserved_vm = false; evict_mem.bus.io_reserved_count = 0; - placement.num_placement = 0; - placement.num_busy_placement = 0; - bdev->driver->evict_flags(bo, &placement); ret = ttm_bo_mem_space(bo, &placement, &evict_mem, ctx); if (ret) { if (ret != -ERESTARTSYS) { diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 6d6a3f46143b..1f730b3f18e5 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -801,3 +801,27 @@ int ttm_bo_pipeline_move(struct ttm_buffer_object *bo, return 0; } EXPORT_SYMBOL(ttm_bo_pipeline_move); + +int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo) +{ + struct ttm_buffer_object *ghost; + int ret; + + ret = ttm_buffer_object_transfer(bo, &ghost); + if (ret) + return ret; + + ret = reservation_object_copy_fences(ghost->resv, bo->resv); + /* Last resort, wait for the BO to be idle when we are OOM */ + if (ret) + ttm_bo_wait(bo, false, false); + + memset(&bo->mem, 0, sizeof(bo->mem)); + bo->mem.mem_type = TTM_PL_SYSTEM; + bo->ttm = NULL; + + ttm_bo_unreserve(ghost); + ttm_bo_unref(&ghost); + + return 0; +} diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index f8e2515b401f..39cd6b086d3a 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -849,6 +849,15 @@ int ttm_bo_pipeline_move(struct ttm_buffer_object *bo, struct dma_fence *fence, bool evict, struct ttm_mem_reg *new_mem); +/** + * ttm_bo_pipeline_gutting. + * + * @bo: A pointer to a struct ttm_buffer_object. + * + * Pipelined gutting a BO of it's backing store. + */ +int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo); + /** * ttm_io_prot * -- 2.14.1

3 9

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel March 2018