dri-devel June 2018

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[Bug 73931] New: rmmod radeon and kernel crash
by bugzilla-daemon＠bugzilla.kernel.org 08 Jun '18

08 Jun '18

https://bugzilla.kernel.org/show_bug.cgi?id=73931 Bug ID: 73931 Summary: rmmod radeon and kernel crash Product: Drivers Version: 2.5 Kernel Version: 3.14 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: high Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: pali.rohar(a)gmail.com Regression: No Created attachment 132051 --> https://bugzilla.kernel.org/attachment.cgi?id=132051&action=edit rmmod_radeon_kernel_panic After calling rmmod radeon, kernel show lots of error lines and then crash. It looks like that radeon module does not cleanup hwmon interface at exit. After calling rmmod radeon there is still hwmon interface: $ readlink /sys/class/hwmon/hwmon1 ../../devices/pci0000:00/0000:00:01.0/0000:01:00.0/hwmon/hwmon1 And after calling ls, or cat in hwmon1 kernel crash... See attachment from syslog. $ lspci -nn 01:00.0 Display controller [0380]: Advanced Micro Devices, Inc. [AMD/ATI] Sun XT [Radeon HD 8670A/8670M/8690M] [1002:6660] -- You are receiving this mail because: You are watching the assignee of the bug.

1 11

[PATCH v7 1/2] drm/i915: update cursors asynchronously through atomic
by Enric Balletbo i Serra 08 Jun '18

08 Jun '18

From: Gustavo Padovan <gustavo.padovan(a)collabora.com> Add support to async updates of cursors by using the new atomic interface for that. Basically what this commit does is do what intel_legacy_cursor_update() did but through atomic. Cc: Daniel Vetter <daniel.vetter(a)intel.com> Cc: intel-gfx(a)lists.freedesktop.org Signed-off-by: Gustavo Padovan <gustavo.padovan(a)collabora.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo(a)collabora.com> --- This is another attempt to land the patches to update cursors asynchronously through atomic for the i915 driver. Last version was sent some time ago [1], so these series are rebased on top of current mainline and also solves some issues found. The patches were tested by running the igt test and check there is no regressions (kms_cursor_legacy and kms_atomic plane_cursor_legacy) Waiting for your feedback, Enric [1] https://lists.freedesktop.org/archives/dri-devel/2017-September/152141.html Changes in v7: - Rebase on top of drm-intel repository. Hopefully now will play nicely with autobuilders. Changes in v6: - Rework the intel_plane_atomic_async_update due driver changed from last time. - Removed the mutex_lock/unlock as causes a deadlock. Changes in v5: - Call drm_atomic_helper_async_check() from the check hook Changes in v4: - Set correct vma to new state for cleanup - Move size checks back to drivers (Ville Syrjälä) Changes in v3: - Move fb setting to core and use new state (Eric Anholt) drivers/gpu/drm/i915/intel_atomic_plane.c | 69 ++++++++++ drivers/gpu/drm/i915/intel_display.c | 155 +++------------------- 2 files changed, 87 insertions(+), 137 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index 6d068786eb41..5fc38ee55aba 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -253,11 +253,80 @@ static void intel_plane_atomic_update(struct drm_plane *plane, } } +static int intel_plane_atomic_async_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct drm_crtc_state *crtc_state; + + if (plane->type != DRM_PLANE_TYPE_CURSOR) + return -EINVAL; + + crtc_state = drm_atomic_get_existing_crtc_state(state->state, + state->crtc); + if (WARN_ON(!crtc_state)) + return -EINVAL; + + /* + * When crtc is inactive or there is a modeset pending, + * wait for it to complete in the slowpath + */ + if (!crtc_state->active || to_intel_crtc_state(crtc_state)->update_pipe) + return -EINVAL; + + /* + * If any parameters change that may affect watermarks, + * take the slowpath. Only changing fb or position should be + * in the fastpath. + */ + if (plane->state->crtc != state->crtc || + plane->state->src_w != state->src_w || + plane->state->src_h != state->src_h || + plane->state->crtc_w != state->crtc_w || + plane->state->crtc_h != state->crtc_h || + !plane->state->fb != !state->fb) + return -EINVAL; + + return 0; +} + +static void intel_plane_atomic_async_update(struct drm_plane *plane, + struct drm_plane_state *new_state) +{ + struct intel_plane *intel_plane = to_intel_plane(plane); + struct drm_crtc *crtc = plane->state->crtc; + struct drm_framebuffer *old_fb; + + old_fb = plane->state->fb; + + i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(new_state->fb), + intel_plane->frontbuffer_bit); + + plane->state->src_x = new_state->src_x; + plane->state->src_y = new_state->src_y; + plane->state->crtc_x = new_state->crtc_x; + plane->state->crtc_y = new_state->crtc_y; + plane->state->fb = new_state->fb; + + new_state->fb = old_fb; + + if (plane->state->visible) { + trace_intel_update_plane(plane, to_intel_crtc(crtc)); + intel_plane->update_plane(intel_plane, + to_intel_crtc_state(crtc->state), + to_intel_plane_state(plane->state)); + } else { + trace_intel_disable_plane(plane, to_intel_crtc(crtc)); + intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc)); + } +} + const struct drm_plane_helper_funcs intel_plane_helper_funcs = { .prepare_fb = intel_prepare_plane_fb, .cleanup_fb = intel_cleanup_plane_fb, .atomic_check = intel_plane_atomic_check, .atomic_update = intel_plane_atomic_update, + .atomic_async_check = intel_plane_atomic_async_check, + .atomic_async_update = intel_plane_atomic_async_update, }; /** diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 17c590b42fd7..4ff73bfd1616 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12319,6 +12319,9 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) return ret; + if (state->legacy_cursor_update) + state->async_update = !drm_atomic_helper_async_check(dev, + state); intel_fbc_choose_crtc(dev_priv, intel_state); return calc_watermark_data(state); } @@ -12743,38 +12746,27 @@ static int intel_atomic_commit(struct drm_device *dev, struct drm_i915_private *dev_priv = to_i915(dev); int ret = 0; - drm_atomic_state_get(state); - i915_sw_fence_init(&intel_state->commit_ready, - intel_atomic_commit_ready); - /* - * The intel_legacy_cursor_update() fast path takes care + * The atomic async update fast path takes care * of avoiding the vblank waits for simple cursor * movement and flips. For cursor on/off and size changes, * we want to perform the vblank waits so that watermark * updates happen during the correct frames. Gen9+ have * double buffered watermarks and so shouldn't need this. - * - * Unset state->legacy_cursor_update before the call to - * drm_atomic_helper_setup_commit() because otherwise - * drm_atomic_helper_wait_for_flip_done() is a noop and - * we get FIFO underruns because we didn't wait - * for vblank. - * - * FIXME doing watermarks and fb cleanup from a vblank worker - * (assuming we had any) would solve these problems. */ - if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) { - struct intel_crtc_state *new_crtc_state; - struct intel_crtc *crtc; - int i; + if (state->async_update) { + ret = drm_atomic_helper_prepare_planes(dev, state); + if (ret) + return ret; - for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i) - if (new_crtc_state->wm.need_postvbl_update || - new_crtc_state->update_wm_post) - state->legacy_cursor_update = false; + drm_atomic_helper_async_commit(dev, state); + return 0; } + drm_atomic_state_get(state); + i915_sw_fence_init(&intel_state->commit_ready, + intel_atomic_commit_ready); + ret = intel_atomic_prepare_commit(dev, state); if (ret) { DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); @@ -12963,6 +12955,9 @@ intel_prepare_plane_fb(struct drm_plane *plane, struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); int ret; + if (new_state->state->async_update) + return 0; + if (old_obj) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(new_state->state, @@ -13346,122 +13341,8 @@ static struct drm_plane_funcs intel_plane_funcs = { .format_mod_supported = intel_primary_plane_format_mod_supported, }; -static int -intel_legacy_cursor_update(struct drm_plane *plane, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int crtc_x, int crtc_y, - unsigned int crtc_w, unsigned int crtc_h, - uint32_t src_x, uint32_t src_y, - uint32_t src_w, uint32_t src_h, - struct drm_modeset_acquire_ctx *ctx) -{ - struct drm_i915_private *dev_priv = to_i915(crtc->dev); - int ret; - struct drm_plane_state *old_plane_state, *new_plane_state; - struct intel_plane *intel_plane = to_intel_plane(plane); - struct drm_framebuffer *old_fb; - struct drm_crtc_state *crtc_state = crtc->state; - - /* - * When crtc is inactive or there is a modeset pending, - * wait for it to complete in the slowpath - */ - if (!crtc_state->active || needs_modeset(crtc_state) || - to_intel_crtc_state(crtc_state)->update_pipe) - goto slow; - - old_plane_state = plane->state; - /* - * Don't do an async update if there is an outstanding commit modifying - * the plane. This prevents our async update's changes from getting - * overridden by a previous synchronous update's state. - */ - if (old_plane_state->commit && - !try_wait_for_completion(&old_plane_state->commit->hw_done)) - goto slow; - - /* - * If any parameters change that may affect watermarks, - * take the slowpath. Only changing fb or position should be - * in the fastpath. - */ - if (old_plane_state->crtc != crtc || - old_plane_state->src_w != src_w || - old_plane_state->src_h != src_h || - old_plane_state->crtc_w != crtc_w || - old_plane_state->crtc_h != crtc_h || - !old_plane_state->fb != !fb) - goto slow; - - new_plane_state = intel_plane_duplicate_state(plane); - if (!new_plane_state) - return -ENOMEM; - - drm_atomic_set_fb_for_plane(new_plane_state, fb); - - new_plane_state->src_x = src_x; - new_plane_state->src_y = src_y; - new_plane_state->src_w = src_w; - new_plane_state->src_h = src_h; - new_plane_state->crtc_x = crtc_x; - new_plane_state->crtc_y = crtc_y; - new_plane_state->crtc_w = crtc_w; - new_plane_state->crtc_h = crtc_h; - - ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), - to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */ - to_intel_plane_state(plane->state), - to_intel_plane_state(new_plane_state)); - if (ret) - goto out_free; - - ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); - if (ret) - goto out_free; - - ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state)); - if (ret) - goto out_unlock; - - intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP); - - old_fb = old_plane_state->fb; - i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), - intel_plane->frontbuffer_bit); - - /* Swap plane state */ - plane->state = new_plane_state; - - if (plane->state->visible) { - trace_intel_update_plane(plane, to_intel_crtc(crtc)); - intel_plane->update_plane(intel_plane, - to_intel_crtc_state(crtc->state), - to_intel_plane_state(plane->state)); - } else { - trace_intel_disable_plane(plane, to_intel_crtc(crtc)); - intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc)); - } - - intel_plane_unpin_fb(to_intel_plane_state(old_plane_state)); - -out_unlock: - mutex_unlock(&dev_priv->drm.struct_mutex); -out_free: - if (ret) - intel_plane_destroy_state(plane, new_plane_state); - else - intel_plane_destroy_state(plane, old_plane_state); - return ret; - -slow: - return drm_atomic_helper_update_plane(plane, crtc, fb, - crtc_x, crtc_y, crtc_w, crtc_h, - src_x, src_y, src_w, src_h, ctx); -} - static const struct drm_plane_funcs intel_cursor_plane_funcs = { - .update_plane = intel_legacy_cursor_update, + .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, .destroy = intel_plane_destroy, .atomic_get_property = intel_plane_atomic_get_property, -- 2.17.1

1 1

[PATCH v4 0/9] Add support for mediatek SOC MT2712
by Stu Hsieh 08 Jun '18

08 Jun '18

This patch add support for the Mediatek MT2712 DISP subsystem. MT2712 is base on MT8173, there are some difference as following: MT2712 support three disp output(two ovl and one rdma) Change in v4: - Move some modification about AAL1 from patch "Add support for mediatek SOC MT2712" to "add ddp component AAL1" - Move some modification about OD1 from patch "Add support for mediatek SOC MT2712" to "add ddp component OD1" - Move some modification about PWM2 from patch "Add support for mediatek SOC MT2712" to "add ddp component PWM2" - Move some modification about third ddp path from patch "Add support for mediatek SOC MT2712" to "add third ddp path" - Move the definition OD1_MOUT_EN_RDMA1 from patch "Add support for mediatek SOC MT2712" to "add connection from OD1 to RDMA1" - Rebase the patch "add connection from OD1 to RDMA1" after "add ddp component OD1" - Rebase the patch "add third ddp path" before "Add support for mediatek SOC MT2712" - Modify the 2712 MUTEX MODULE in the order by index - Added patch for ddp component PWM1 - For patch "add third ddp path" Add the condition in mtk_crtc_create() that if there is no ddp path, then return 0 to avoid the null crtc Change in v3: - Added patch for ddp component AAL1 - Added patch for ddp component OD1 - Added patch for ddp component PWM2 - Added patch to create third ddp path - Rebase patch "support maximum 64 mutex mod" before "Add support for mediatek SOC MT2712" - Rebase patch "add connection from OD1 to RDMA1" before "Add support for mediatek SOC MT2712" - Remove two definition about RDMA0 and RDMA2 - Change the definition about mutex module from bitwise to index Changes in v2: - update dt-bindings for mt2712 - Added patch to connection from OD1 to RDMA1 - Added patch to support maximum 64 mutex mod - rewrite mutex mod condition for reducing one byte - Change the component name AAL/OD to AAL0/OD0 for naming consistency - Move the compatible information about dpi to other patch which modify the dpi driver for mt2712 Stu Hsieh (9): drm/mediatek: update dt-bindings for mt2712 drm/mediatek: support maximum 64 mutex mod drm/mediatek: add ddp component AAL1 drm/mediatek: add ddp component OD1 drm/mediatek: add ddp component PWM1 drm/mediatek: add ddp component PWM2 drm/mediatek: add connection from OD1 to RDMA1 drm/mediatek: add third ddp path drm/mediatek: Add support for mediatek SOC MT2712 .../bindings/display/mediatek/mediatek,disp.txt | 2 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 124 +++++++++++++++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 +++++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +- 7 files changed, 158 insertions(+), 40 deletions(-) -- 2.12.5

4 20

[PATCH v2] drm/msm: Add OUT_RING64() helper macro
by Sharat Masetty 08 Jun '18

08 Jun '18

This patch adds a simple helper function to help write 64 bit payloads to the ringbuffer. Signed-off-by: Sharat Masetty <smasetty(a)codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 ++++-------- drivers/gpu/drm/msm/adreno/a5xx_power.c | 3 +-- drivers/gpu/drm/msm/msm_ringbuffer.h | 6 ++++++ 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 5cdf104..7a58a01 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -223,8 +223,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, /* Set the save preemption record for the ring/command */ OUT_PKT4(ring, REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO, 2); - OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id])); - OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id])); + OUT_RING64(ring, a5xx_gpu->preempt_iova[submit->ring->id]); /* Turn back on protected mode */ OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); @@ -248,8 +247,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, break; case MSM_SUBMIT_CMD_BUF: OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); - OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); - OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); + OUT_RING64(ring, submit->cmd[i].iova); OUT_RING(ring, submit->cmd[i].size); ibs++; break; @@ -282,8 +280,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, */ OUT_PKT7(ring, CP_EVENT_WRITE, 4); OUT_RING(ring, CACHE_FLUSH_TS | (1 << 31)); - OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); - OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); + OUT_RING64(ring, rbmemptr(ring, fence)); OUT_RING(ring, submit->seqno); /* Yield the floor on command completion */ @@ -469,8 +466,7 @@ static int a5xx_preempt_start(struct msm_gpu *gpu) /* Set the save preemption record for the ring/command */ OUT_PKT4(ring, REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO, 2); - OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[ring->id])); - OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[ring->id])); + OUT_RING64(ring, a5xx_gpu->preempt_iova[ring->id]); /* Turn back on protected mode */ OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c index e9c0e56..ea5bfa5 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c @@ -190,8 +190,7 @@ static int a5xx_gpmu_init(struct msm_gpu *gpu) /* Kick off the IB to load the GPMU microcode */ OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); - OUT_RING(ring, lower_32_bits(a5xx_gpu->gpmu_iova)); - OUT_RING(ring, upper_32_bits(a5xx_gpu->gpmu_iova)); + OUT_RING64(ring, a5xx_gpu->gpmu_iova); OUT_RING(ring, a5xx_gpu->gpmu_dwords); /* Turn back on protected mode */ diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h index cffce09..2fd8cc6 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -61,4 +61,10 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, *(ring->next++) = data; } +static inline void +OUT_RING64(struct msm_ringbuffer *ring, u64 data) +{ + OUT_RING(ring, lower_32_bits(data)); + OUT_RING(ring, upper_32_bits(data)); +} #endif /* __MSM_RINGBUFFER_H__ */ -- 1.9.1

1 0

[PATCH 00/15] Add support for R40 HDMI pipeline
by Jernej Skrabec 08 Jun '18

08 Jun '18

This series adds support for R40 HDMI pipeline. It is a bit special than other already supported pipelines because it has additional unit called TCON TOP responsible for relationship configuration between mixers, TCONs and HDMI. Additionally, it has additional gates for DSI and TV TCONs, TV encoder clock settings and pin muxing between LCD and TV encoders. However, it seems that TCON TOP will become a norm, since newer Allwinner SoCs like H6 also have this unit. I tested different possible configurations: - mixer0 <> TCON-TV0 <> HDMI - mixer0 <> TCON-TV1 <> HDMI - mixer1 <> TCON-TV0 <> HDMI - mixer1 <> TCON-TV1 <> HDMI Please review. Best regards, Jernej Jernej Skrabec (15): clk: sunxi-ng: r40: Add minimal rate for video PLLs clk: sunxi-ng: r40: Allow setting parent rate to display related clocks clk: sunxi-ng: r40: Export video PLLs dt-bindings: display: sunxi-drm: Add TCON TOP description drm/sun4i: Add TCON TOP driver drm/sun4i: tcon: Add support for tcon-top dt-bindings: display: sun4i-drm: Add R40 HDMI pipeline drm/sun4i: DE2 mixer: Add index quirk drm/sun4i: Add support for R40 mixers drm/sun4i: Add support for R40 TV TCONs drm/sun4i: DW HDMI PHY: Add support for second PLL drm/sun4i: Add support for second clock parent to DW HDMI PHY clk driver drm/sun4i: Add support for A64 HDMI PHY ARM: dts: sun8i: r40: Add HDMI pipeline ARM: dts: sun8i: r40: Enable HDMI output on BananaPi M2 Ultra .../bindings/display/sunxi/sun4i-drm.txt | 36 ++- .../boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 50 ++++ arch/arm/boot/dts/sun8i-r40.dtsi | 166 ++++++++++++ drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 58 ++-- drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 8 +- drivers/gpu/drm/sun4i/Makefile | 3 +- drivers/gpu/drm/sun4i/sun4i_tcon.c | 67 +++++ drivers/gpu/drm/sun4i/sun4i_tcon.h | 8 + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 8 +- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 61 ++++- drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 90 ++++-- drivers/gpu/drm/sun4i/sun8i_mixer.c | 30 +- drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 + drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 256 ++++++++++++++++++ drivers/gpu/drm/sun4i/sun8i_tcon_top.h | 20 ++ include/dt-bindings/clock/sun8i-r40-ccu.h | 4 + include/dt-bindings/clock/sun8i-tcon-top.h | 11 + 17 files changed, 813 insertions(+), 65 deletions(-) create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.c create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.h create mode 100644 include/dt-bindings/clock/sun8i-tcon-top.h -- 2.17.0

8 45

[PATCH v9 0/3] drm: Introduce writeback connectors
by Liviu Dudau 07 Jun '18

07 Jun '18

Hi, This is v9 of the writeback connector series. Compared to v8 I've addressed the comments from Eric Anholt, as well as Maarten Lankhorst's and Daniel Vetter's one on the client capabilities. Most importantly, I've also realised that Dave Airlie has moved the drm-next tree to fd.org and went and rebased the patches on top of the new tree, which had conflicts with this series as the aspect ration capability was introduced in the meanwhile. I will ask Gustavo to pull this series into drm-misc if there are no further comments. Best regards, Liviu Brian Starkey (2): drm: Add writeback connector type drm: writeback: Add out-fences for writeback connectors Liviu Dudau (1): drm: writeback: Add client capability for exposing writeback connectors Documentation/gpu/drm-kms.rst | 9 + drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/drm_atomic.c | 227 +++++++++++++- drivers/gpu/drm/drm_atomic_helper.c | 30 ++ drivers/gpu/drm/drm_connector.c | 4 +- drivers/gpu/drm/drm_ioctl.c | 7 + drivers/gpu/drm/drm_mode_config.c | 5 + drivers/gpu/drm/drm_writeback.c | 360 +++++++++++++++++++++++ include/drm/drm_atomic.h | 11 + include/drm/drm_connector.h | 13 + include/drm/drm_file.h | 7 + include/drm/drm_mode_config.h | 23 ++ include/drm/drm_modeset_helper_vtables.h | 11 + include/drm/drm_writeback.h | 129 ++++++++ include/uapi/drm/drm.h | 9 + include/uapi/drm/drm_mode.h | 1 + 16 files changed, 837 insertions(+), 11 deletions(-) create mode 100644 drivers/gpu/drm/drm_writeback.c create mode 100644 include/drm/drm_writeback.h -- 2.17.0

2 6

[DPU PATCH v3] Higher values of pclk can exceed 32 bits when multiplied by a factor.
by Abhinav Kumar 07 Jun '18

07 Jun '18

Make the pclk_rate u64 to accommodate higher pixel clock rates. Changes in v3: - Rebased on top of https://patchwork.kernel.org/patch/10348865/ Signed-off-by: Abhinav Kumar <abhinavk(a)codeaurora.org> --- drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index b9f2ef9..596959c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -669,7 +669,8 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; u8 lanes = msm_host->lanes; u32 bpp = dsi_get_bpp(msm_host->format); - u32 pclk_rate; + u64 pclk_rate; + u64 pclk_bpp; if (!mode) { pr_err("%s: mode not set\n", __func__); @@ -689,13 +690,15 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) if (is_dual_dsi) pclk_rate /= 2; + pclk_bpp = pclk_rate * bpp; if (lanes > 0) { - msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes); + do_div(pclk_bpp, (8 * lanes)); } else { pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); - msm_host->byte_clk_rate = (pclk_rate * bpp) / 8; + do_div(pclk_bpp, 8); } msm_host->pixel_clk_rate = pclk_rate; + msm_host->byte_clk_rate = pclk_bpp; DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, msm_host->byte_clk_rate); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

3 2

[DPU PATCH v4] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor
by Abhinav Kumar 07 Jun '18

07 Jun '18

Make the pclk_rate u64 to accommodate higher pixel clock rates. Changes in v4: - fixed commit message Signed-off-by: Abhinav Kumar <abhinavk(a)codeaurora.org> --- drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index b9f2ef9..596959c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -669,7 +669,8 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; u8 lanes = msm_host->lanes; u32 bpp = dsi_get_bpp(msm_host->format); - u32 pclk_rate; + u64 pclk_rate; + u64 pclk_bpp; if (!mode) { pr_err("%s: mode not set\n", __func__); @@ -689,13 +690,15 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) if (is_dual_dsi) pclk_rate /= 2; + pclk_bpp = pclk_rate * bpp; if (lanes > 0) { - msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes); + do_div(pclk_bpp, (8 * lanes)); } else { pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); - msm_host->byte_clk_rate = (pclk_rate * bpp) / 8; + do_div(pclk_bpp, 8); } msm_host->pixel_clk_rate = pclk_rate; + msm_host->byte_clk_rate = pclk_bpp; DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, msm_host->byte_clk_rate); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

1 0

Re: [Freedreno] [DPU PATCH v2 2/7] drm/msm/dpu: clean up dpu plane custom properties
by Sean Paul 07 Jun '18

07 Jun '18

On Tue, Jun 05, 2018 at 08:45:33PM -0700, Jeykumar Sankaran wrote: > This change removes all the dpu plane custom properties > and its handlers. > > changs in v2: > - remove stale code in blend config(Sean Paul) > - Makefile changes to remove warning flags(Sean Paul) > > Signed-off-by: Jeykumar Sankaran <jsanka(a)codeaurora.org> > --- > drivers/gpu/drm/msm/Makefile | 8 - > drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h | 99 -- > .../gpu/drm/msm/disp/dpu1/dpu_color_processing.c | 1521 -------------------- > .../gpu/drm/msm/disp/dpu1/dpu_color_processing.h | 120 -- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 205 +-- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 - > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 1 - > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c | 1443 ------------------- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 72 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 89 -- > .../msm/disp/dpu1/dpu_hw_color_proc_common_v4.h | 69 - > .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c | 242 ---- > .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h | 40 - > .../drm/msm/disp/dpu1/dpu_hw_color_processing.h | 20 - > .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.c | 565 -------- > .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.h | 92 -- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 44 - > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 15 - > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 209 --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h | 220 --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 44 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 68 - > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 6 - > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c | 757 ---------- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h | 27 - > .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c | 943 ------------ > .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h | 75 - > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 219 --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 73 - > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 1 - > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 156 ++ > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 - > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1269 +--------------- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 31 - > drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c | 139 -- > drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h | 310 ---- > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 102 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 - > drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c | 2 - > drivers/gpu/drm/msm/msm_drv.h | 28 - > include/uapi/drm/dpu_drm.h | 187 --- > include/uapi/drm/msm_drm.h | 1 - > 44 files changed, 282 insertions(+), 9241 deletions(-) > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.h > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c > delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h > /snip > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c /snip > - > -int dpu_reg_dma_init(void __iomem *addr, struct dpu_mdss_cfg *m, > - struct drm_device *dev) > -{ > - int rc = 0; > - > - if (!addr || !m || !dev) { > - DRM_DEBUG("invalid addr %pK catalog %pK dev %pK\n", addr, m, > - dev); > - return 0; > - } > - > - reg_dma.drm_dev = dev; > - reg_dma.caps = &m->dma_cfg; > - reg_dma.addr = addr; > - > - if (!m->reg_dma_count) > - return 0; > - > - switch (reg_dma.caps->version) { > - case 1: > - rc = init_v1(&reg_dma); > - if (rc) > - DRM_DEBUG("init v1 dma ops failed\n"); > - else > - dpu_dbg_reg_register_base("reg_dma", addr, > - reg_dma.caps->len); > - break; > - default: > - break; > - } > - > - return 0; > -} > - ../scripts/Makefile.build:559: recipe for target 'drivers/gpu/drm' failed ../scripts/Makefile.build:559: recipe for target 'drivers/gpu' failed /usr/local/google/home/seanpaul/s/dpu-staging/Makefile:1060: recipe for target 'drivers' failed make[1]: Leaving directory '/usr/local/google/home/seanpaul/s/dpu-staging/.build_arm' Makefile:146: recipe for target 'sub-make' failed ../drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c: In function ‘dpu_crtc_atomic_check’: ../drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:2097:1: warning: the frame size of 1048 bytes is larger than 1024 bytes [-Wframe-larger-than=] } ^ ../drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c: In function ‘dpu_kms_hw_init’: ../drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c:1512:7: error: implicit declaration of function ‘dpu_reg_dma_init’; did you mean ‘dpu_rm_init’? [-Werror=implicit-function-declaration] rc = dpu_reg_dma_init(dpu_kms->reg_dma, dpu_kms->catalog, ^~~~~~~~~~~~~~~~ dpu_rm_init cc1: some warnings being treated as errors /snip -- Sean Paul, Software Engineer, Google / Chromium OS

1 0

[DPU PATCH v4] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor.
by Abhinav Kumar 07 Jun '18

07 Jun '18

1 0

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dri-devel June 2018