dri-devel June 2018

dri-devel@lists.freedesktop.org

241 participants
1687 discussions

[PATCH 4.9 55/61] drm/psr: Fix missed entry in PSR setup time table.
by Greg Kroah-Hartman 05 Jun '18

05 Jun '18

4.9-stable review patch. If anyone has any objections, please let me know. ------------------ From: Dhinakaran Pandiyan <dhinakaran.pandiyan(a)intel.com> commit bdcc02cf1bb508fc700df7662f55058f651f2621 upstream. Entry corresponding to 220 us setup time was missing. I am not aware of any specific bug this fixes, but this could potentially result in enabling PSR on a panel with a higher setup time requirement than supported by the hardware. I verified the value is present in eDP spec … [View More]

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[PATCH v2 00/26] arm64: allwinner: Add A64 DE2 HDMI support
by Jagan Teki 05 Jun '18

05 Jun '18

Allwinner A64 has display engine pipeline like other Allwinner SOC's A83T/H3/H5. A64 behaviour similar to Allwinner A83T where Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI Mixer1 => TCON1 => HDMI as per Display System Block DiagramAllwinner_A64_User_Manual_V1.1.pdf This is second patch-set followed with previous RFC[1] and first series[2] and merely concentrated on HDMI pipeline through TCON1 and rest will add eventually. This series fixed previous version comments - about documenting … [View More]fallback compatibles - adding new compatible for mixer1 - support for multiple DW HDMI PHY clock parents (thanks, to Jernej) Note: Pine64 boards are unable to get edid by default like other A64 boards, but forcing 'video=HDMI-A-1:1920x1080@60D' kernel command line can create edid with display on penel. Log: [ 1.613196] sun4i-drm display-engine: bound 1200000.mixer (ops sun8i_mixer_ops) [ 1.620764] sun4i-drm display-engine: No panel or bridge found... RGB output disabled [ 1.628612] sun4i-drm display-engine: bound 1c0d000.lcd-controller (ops sun4i_tcon_ops) [ 1.637677] sun8i-dw-hdmi 1ee0000.hdmi: Detected HDMI TX controller v1.32a with HDCP (sun8i_dw_hdmi_ph y) [ 1.647699] sun8i-dw-hdmi 1ee0000.hdmi: registered DesignWare HDMI I2C bus driver [ 1.656090] [drm] forcing HDMI-A-1 connector on [ 1.660664] sun4i-drm display-engine: bound 1ee0000.hdmi (ops sun8i_dw_hdmi_ops) [ 1.668063] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 1.674684] [drm] No driver support for vblank timestamp query. [ 2.497502] Console: switching to colour frame buffer device 240x67 [ 2.551795] sun4i-drm display-engine: fb0: frame buffer device [ 2.558166] [drm] Initialized sun4i-drm 1.0.0 20150629 for display-engine on minor 0 [2] https://lkml.org/lkml/2018/4/30/288 [1] https://lkml.org/lkml/2018/4/24/547 Icenowy Zheng (1): drm: sun4i: add support for HVCC regulator for DWC HDMI glue Jagan Teki (22): dt-bindings: clock: Add compatible for A64 DE2 CCU arm64: dts: allwinner: a64: Add DE2 CCU clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I clk: sunxi-ng: a64: Add minimal rate for video PLLs drm/sun4i: Add support for A64 mixer1 dt-bindings: display: Add compatible for A64 DE2 tcon1 blocks drm/sun4i: Add support for A64 display engine arm64: dts: allwinner: a64: Add DE2 tcon1 pipeline drm/sun4i: Enable DE2 Mixer for SUN8I and SUN50I arm64: defconfig: Enable CONFIG_DRM_SUN4I dt-bindings: display: Add compatible for A64 HDMI dt-bindings: display: Add compatible for A64 HDMI PHY dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO[0-1] macros arm64: dts: allwinner: a64: Add HDMI support drm/sun4i: Enable DesignWare HDMI for SUN8I and SUN50I arm64: dts: allwinner: a64: Add HDMI pipeline arm64: dts: allwinner: a64: bananapi-m64: Enable HDMI output arm64: dts: allwinner: a64: nanopi-a64: Enable HDMI output arm64: dts: allwinner: a64: orangepi-win: Enable HDMI output arm64: dts: allwinner: a64: a64-olinuxino: Enable HDMI output arm64: dts: allwinner: a64: pine64: Enable HDMI output arm64: dts: allwinner: a64: sopine: Enable HDMI output Jernej Skrabec (3): drm/sun4i: DE2 mixer: Add index quirk drm/sun4i: Add support for multiple DW HDMI PHY clock parents drm/sun4i: Add support for A64 HDMI PHY .../devicetree/bindings/clock/sun8i-de2.txt | 1 + .../bindings/display/sunxi/sun4i-drm.txt | 5 + .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 26 +++++ .../boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 26 +++++ .../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 26 +++++ .../boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 26 +++++ .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 26 +++++ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 26 +++++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 124 +++++++++++++++++++++ arch/arm64/configs/defconfig | 1 + drivers/clk/sunxi-ng/Kconfig | 2 + drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 46 ++++---- drivers/gpu/drm/sun4i/Kconfig | 3 +- drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 14 +++ drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 11 +- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 44 ++++++-- drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 89 +++++++++++---- drivers/gpu/drm/sun4i/sun8i_mixer.c | 17 ++- drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 + include/dt-bindings/clock/sun50i-a64-ccu.h | 2 + 21 files changed, 458 insertions(+), 60 deletions(-) -- 2.14.3 [View Less]

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[PATCH v7 1/5] drm/rockchip: add transfer function for cdn-dp
by Lin Huang 05 Jun '18

05 Jun '18

From: Chris Zhong <zyw(a)rock-chips.com> We may support training outside firmware, so we need support dpcd read/write to get the message or do some setting with display. Signed-off-by: Chris Zhong <zyw(a)rock-chips.com> Signed-off-by: Lin Huang <hl(a)rock-chips.com> Reviewed-by: Sean Paul <seanpaul(a)chromium.org> Reviewed-by: Enric Balletbo <enric.balletbo(a)collabora.com> --- Changes in v2: - update patch following Enric suggest Changes in v3: - None Changes in … [View More]v4: - None Changes in v5: - None Changes in v6: - None Changes in v7: - None drivers/gpu/drm/rockchip/cdn-dp-core.c | 55 +++++++++++++++++++++++---- drivers/gpu/drm/rockchip/cdn-dp-core.h | 1 + drivers/gpu/drm/rockchip/cdn-dp-reg.c | 69 ++++++++++++++++++++++++++++++---- drivers/gpu/drm/rockchip/cdn-dp-reg.h | 14 ++++++- 4 files changed, 122 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c index c6fbdcd..cce64c1 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c @@ -176,8 +176,8 @@ static int cdn_dp_get_sink_count(struct cdn_dp_device *dp, u8 *sink_count) u8 value; *sink_count = 0; - ret = cdn_dp_dpcd_read(dp, DP_SINK_COUNT, &value, 1); - if (ret) + ret = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, &value, 1); + if (ret < 0) return ret; *sink_count = DP_GET_SINK_COUNT(value); @@ -374,9 +374,9 @@ static int cdn_dp_get_sink_capability(struct cdn_dp_device *dp) if (!cdn_dp_check_sink_connection(dp)) return -ENODEV; - ret = cdn_dp_dpcd_read(dp, DP_DPCD_REV, dp->dpcd, - DP_RECEIVER_CAP_SIZE); - if (ret) { + ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd, + sizeof(dp->dpcd)); + if (ret < 0) { DRM_DEV_ERROR(dp->dev, "Failed to get caps %d\n", ret); return ret; } @@ -582,8 +582,8 @@ static bool cdn_dp_check_link_status(struct cdn_dp_device *dp) if (!port || !dp->link.rate || !dp->link.num_lanes) return false; - if (cdn_dp_dpcd_read(dp, DP_LANE0_1_STATUS, link_status, - DP_LINK_STATUS_SIZE)) { + if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) != + DP_LINK_STATUS_SIZE) { DRM_ERROR("Failed to get link status\n"); return false; } @@ -1012,6 +1012,40 @@ static int cdn_dp_pd_event(struct notifier_block *nb, return NOTIFY_DONE; } +static ssize_t cdn_dp_aux_transfer(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg) +{ + struct cdn_dp_device *dp = container_of(aux, struct cdn_dp_device, aux); + int ret; + u8 status; + + switch (msg->request & ~DP_AUX_I2C_MOT) { + case DP_AUX_NATIVE_WRITE: + case DP_AUX_I2C_WRITE: + case DP_AUX_I2C_WRITE_STATUS_UPDATE: + ret = cdn_dp_dpcd_write(dp, msg->address, msg->buffer, + msg->size); + break; + case DP_AUX_NATIVE_READ: + case DP_AUX_I2C_READ: + ret = cdn_dp_dpcd_read(dp, msg->address, msg->buffer, + msg->size); + break; + default: + return -EINVAL; + } + + status = cdn_dp_get_aux_status(dp); + if (status == AUX_STATUS_ACK) + msg->reply = DP_AUX_NATIVE_REPLY_ACK; + else if (status == AUX_STATUS_NACK) + msg->reply = DP_AUX_NATIVE_REPLY_NACK; + else if (status == AUX_STATUS_DEFER) + msg->reply = DP_AUX_NATIVE_REPLY_DEFER; + + return ret; +} + static int cdn_dp_bind(struct device *dev, struct device *master, void *data) { struct cdn_dp_device *dp = dev_get_drvdata(dev); @@ -1030,6 +1064,13 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data) dp->active = false; dp->active_port = -1; dp->fw_loaded = false; + dp->aux.name = "DP-AUX"; + dp->aux.transfer = cdn_dp_aux_transfer; + dp->aux.dev = dev; + + ret = drm_dp_aux_register(&dp->aux); + if (ret) + return ret; INIT_WORK(&dp->event_work, cdn_dp_pd_event_work); diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.h b/drivers/gpu/drm/rockchip/cdn-dp-core.h index f57e296..46159b2 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.h +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h @@ -78,6 +78,7 @@ struct cdn_dp_device { struct platform_device *audio_pdev; struct work_struct event_work; struct edid *edid; + struct drm_dp_aux aux; struct mutex lock; bool connected; diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.c b/drivers/gpu/drm/rockchip/cdn-dp-reg.c index eb3042c..979355d 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-reg.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-reg.c @@ -221,7 +221,12 @@ static int cdn_dp_reg_write_bit(struct cdn_dp_device *dp, u16 addr, sizeof(field), field); } -int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len) +/* + * Returns the number of bytes transferred on success, or a negative + * error code on failure. -ETIMEDOUT is returned if mailbox message was + * not send successfully; + */ +ssize_t cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len) { u8 msg[5], reg[5]; int ret; @@ -247,24 +252,41 @@ int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len) goto err_dpcd_read; ret = cdn_dp_mailbox_read_receive(dp, data, len); + if (!ret) + return len; err_dpcd_read: + DRM_DEV_ERROR(dp->dev, "dpcd read failed: %d\n", ret); return ret; } -int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value) +#define CDN_AUX_HEADER_SIZE 5 +#define CDN_AUX_MSG_SIZE 20 +/* + * Returns the number of bytes transferred on success, or a negative error + * code on failure. -ETIMEDOUT is returned if mailbox message was not send + * success; -EINVAL is returned if get the wrong data size after message + * is sent + */ +ssize_t cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len) { - u8 msg[6], reg[5]; + u8 msg[CDN_AUX_MSG_SIZE + CDN_AUX_HEADER_SIZE]; + u8 reg[CDN_AUX_HEADER_SIZE]; int ret; - msg[0] = 0; - msg[1] = 1; + if (WARN_ON(len > CDN_AUX_MSG_SIZE) || WARN_ON(len <= 0)) + return -EINVAL; + + msg[0] = (len >> 8) & 0xff; + msg[1] = len & 0xff; msg[2] = (addr >> 16) & 0xff; msg[3] = (addr >> 8) & 0xff; msg[4] = addr & 0xff; - msg[5] = value; + + memcpy(msg + CDN_AUX_HEADER_SIZE, data, len); + ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_WRITE_DPCD, - sizeof(msg), msg); + CDN_AUX_HEADER_SIZE + len, msg); if (ret) goto err_dpcd_write; @@ -277,8 +299,12 @@ int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value) if (ret) goto err_dpcd_write; - if (addr != (reg[2] << 16 | reg[3] << 8 | reg[4])) + if ((len != (reg[0] << 8 | reg[1])) || + (addr != (reg[2] << 16 | reg[3] << 8 | reg[4]))) { ret = -EINVAL; + } else { + return len; + } err_dpcd_write: if (ret) @@ -286,6 +312,33 @@ int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value) return ret; } +int cdn_dp_get_aux_status(struct cdn_dp_device *dp) +{ + u8 status; + int ret; + + ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, + DPTX_GET_LAST_AUX_STAUS, 0, NULL); + if (ret) + goto err_get_hpd; + + ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX, + DPTX_GET_LAST_AUX_STAUS, + sizeof(status)); + if (ret) + goto err_get_hpd; + + ret = cdn_dp_mailbox_read_receive(dp, &status, sizeof(status)); + if (ret) + goto err_get_hpd; + + return status; + +err_get_hpd: + DRM_DEV_ERROR(dp->dev, "get aux status failed: %d\n", ret); + return ret; +} + int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem, u32 i_size, const u32 *d_mem, u32 d_size) { diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.h b/drivers/gpu/drm/rockchip/cdn-dp-reg.h index c4bbb4a83..6580b11 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-reg.h +++ b/drivers/gpu/drm/rockchip/cdn-dp-reg.h @@ -328,6 +328,13 @@ #define GENERAL_BUS_SETTINGS 0x03 #define GENERAL_TEST_ACCESS 0x04 +/* AUX status*/ +#define AUX_STATUS_ACK 0 +#define AUX_STATUS_NACK 1 +#define AUX_STATUS_DEFER 2 +#define AUX_STATUS_SINK_ERROR 3 +#define AUX_STATUS_BUS_ERROR 4 + #define DPTX_SET_POWER_MNG 0x00 #define DPTX_SET_HOST_CAPABILITIES 0x01 #define DPTX_GET_EDID 0x02 @@ -469,8 +476,11 @@ int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip); int cdn_dp_event_config(struct cdn_dp_device *dp); u32 cdn_dp_get_event(struct cdn_dp_device *dp); int cdn_dp_get_hpd_status(struct cdn_dp_device *dp); -int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value); -int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len); +ssize_t cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, + u8 *data, u16 len); +ssize_t cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, + u8 *data, u16 len); +int cdn_dp_get_aux_status(struct cdn_dp_device *dp); int cdn_dp_get_edid_block(void *dp, u8 *edid, unsigned int block, size_t length); int cdn_dp_train_link(struct cdn_dp_device *dp); -- 2.7.4 [View Less]

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[PATCH] drm/atomic: Constify mode argument to mode_valid_path()
by Laurent Pinchart 05 Jun '18

05 Jun '18

The mode_valid_path() function validates the mode it receives without ever modifying it. Constify the mode pointer argument to make that explicit. Signed-off-by: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> --- drivers/gpu/drm/drm_atomic_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 130da5195f3b..7c3958f73dd4 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/… [View More]

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[PATCH v2 12/21] drm: i2c: ch7006: use match_string() helper
by Yisheng Xie 05 Jun '18

05 Jun '18

match_string() returns the index of an array for a matching string, which can be used instead of open coded variant. Cc: David Airlie <airlied(a)linux.ie> Cc: Yisheng Xie <xieyisheng1(a)huawei.com> Cc: Daniel Vetter <daniel.vetter(a)ffwll.ch> Cc: Arvind Yadav <arvind.yadav.cs(a)gmail.com> Cc: dri-devel(a)lists.freedesktop.org Signed-off-by: Yisheng Xie <xieyisheng1(a)huawei.com> --- v2: - handle err case before normal case. drivers/gpu/drm/i2c/ch7006_drv.c | 13 … [View More]

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[PATCH v2 11/21] drm/nouveau: use match_string() helper
by Yisheng Xie 05 Jun '18

05 Jun '18

match_string() returns the index of an array for a matching string, which can be used instead of open coded variant. Cc: Ben Skeggs <bskeggs(a)redhat.com> Cc: David Airlie <airlied(a)linux.ie> Cc: dri-devel(a)lists.freedesktop.org Cc: nouveau(a)lists.freedesktop.org Signed-off-by: Yisheng Xie <xieyisheng1(a)huawei.com> --- v2: - handle err case before normal case - per Andy drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 … [View More]

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[PATCH] drm/bridge: analogix-anx78xx: Switch to SPDX identifier.
by Enric Balletbo i Serra 05 Jun '18

05 Jun '18

Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Enric Balletbo i Serra <enric.balletbo(a)collabora.com> --- drivers/gpu/drm/bridge/analogix-anx78xx.c | 24 ++++++++--------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix-anx78xx.c index b49043866be6..54d7e7981bed 100644 --- a/drivers/gpu/drm/bridge/analogix-anx78xx.c +++ b/drivers/gpu/drm/… [View More]

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[Bug 106589] HP w2207 monitor not waking from sleep
by bugzilla-daemon＠freedesktop.org 05 Jun '18

05 Jun '18

https://bugs.freedesktop.org/show_bug.cgi?id=106589 Bug ID: 106589 Summary: HP w2207 monitor not waking from sleep Product: DRI Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: DRM/AMDgpu Assignee: dri-devel(a)lists.freedesktop.org Reporter: tseewald(a)gmail.com Created attachment 139653 --&… [View More]

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[v4 0/3] Add support for Adreno a6xx
by Jordan Crouse 05 Jun '18

05 Jun '18

This is initial version of a6xx support for the Adreno a6xx GPU family as found on the sdm845 SoC. This code is ahead of most of the rest of the sdm845 code that would be needed to actually bring up a device and it is definitely far in advance of any user side support for the a6xx GPU so this is mainly just a chance to look over the code structure and get a feel for the direction that the hardware is going in. The a6xx GPU is an iteration of the a5xx family so most of the GPU side code looks … [View More]pretty close to the same except for the usual register differences. The big different is in power control. On the a5xx there was a rudimentary device called the GMU that did some basic power stuff but left most of the complexity to the kernel. On the a6xx the power complexity is being moved to a component called the GMU (graphics management unit). This stack has a number of dependencies that are in various stages of being merged: https://patchwork.kernel.org/patch/10286375/ - dev_pm_opp_get_of_node() https://patchwork.kernel.org/patch/10333575/ - command DB https://patchwork.kernel.org/patch/10301163/ - pm_runtime ops for arm-smmu [v4 - Add clock parsing helper function and use it for GPU and GMU. Update recommended clock gating settings. Fix a bug in the CMD DB parser. Update register values from updated database ] [v3 - fix inverted register definition for GMU_SPTPRAC_CLK_STATUS; fix incorrect register check in a5xx_gmu_gx_is_on(), use dev_pm_opp_get_of_node() from Rajendra and Viresh to read the qcom,level from the device tree; read qcom,level from the DT to get the voltage level to pass to the GMU, fix issues identified by smatch] [v2 - addressed comments from Lucas Stach; added pm_runtime_get_supplier calls for accesses to the GMU IOMMU; moved to SPDX headers for new files] *** BLURB HERE *** Jordan Crouse (2): drm/msm: Add a helper function to parse clock names drm/msm: Add A6XX device support Sharat Masetty (1): drm/msm: Add generated headers for A6XX drivers/gpu/drm/msm/Makefile | 3 + drivers/gpu/drm/msm/adreno/a6xx.xml.h | 1784 ++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1174 +++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 162 ++ drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 382 +++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 807 +++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 60 + drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 435 +++++ drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 127 ++ drivers/gpu/drm/msm/adreno/adreno_device.c | 12 + drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 4 + drivers/gpu/drm/msm/msm_drv.c | 57 + drivers/gpu/drm/msm/msm_drv.h | 4 + drivers/gpu/drm/msm/msm_gpu.c | 62 +- drivers/gpu/drm/msm/msm_gpu.h | 2 +- 16 files changed, 5024 insertions(+), 53 deletions(-) create mode 100644 drivers/gpu/drm/msm/adreno/a6xx.xml.h create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.c create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.h create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu.c create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu.h create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_hfi.c create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_hfi.h -- 2.17.0 [View Less]

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[Bug 199917] New: Stack dump with amdgpu.dc=1 the instant FreeSync is enabled in the connected display.
by bugzilla-daemon＠bugzilla.kernel.org 05 Jun '18

05 Jun '18

https://bugzilla.kernel.org/show_bug.cgi?id=199917 Bug ID: 199917 Summary: Stack dump with amdgpu.dc=1 the instant FreeSync is enabled in the connected display. Product: Drivers Version: 2.5 Kernel Version: 4.17.0-041700-generic Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) … [View More] Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: nicholas.johnson(a)outlook.com.au Regression: No Created attachment 276315 --> https://bugzilla.kernel.org/attachment.cgi?id=276315&action=edit dmesg output and the error starts on the line with "Jun 4 13:26" in it My hardware: Dell XPS 9370 (i7-8650U, 16GB RAM) - although should be reproducible on any system with two Thunderbolt 3 ports. Gigabyte Aorus Thunderbolt Gaming Box external graphics with AMD Radeon R9 Nano installed - should be reproducible with any R9 Fury (Fiji) series. VBIOS is UEFI GOP, laptop BIOS up to date Monitor is Samsung U32E850R with FreeSync support - although any FreeSync monitor should be sufficient. 4.17 kernel enables amdgpu.dc=1 by default, but on previous kernels, you have to pass it explicitly. There is a separate bug with getting the GPU posted when on Thunderbolt - ATOM BIOS loop. However, trying again with the other Thunderbolt port on the computer than the one with which you first attempted, works. Once approved, I can mess around with Xorg conf (seriously, why does Xorg have to be so difficult?) and get the lightdm / Cinnamon running on the external GPU with Intel graphics ignored. This is with FreeSync disabled in the monitor settings. No issues, no errors in dmesg. However, when I enable FreeSync in the monitor menu, when the video signal returns, dmesg has spewed a barrage of errors, as attached in the file (starting from the line containing "Jun 4 13:26" - search without quotes. That line was when I first enabled FreeSync. Passing amdgpu.dc=0 eliminates this particular problem. There are a lot more problems for AMD to fix, though. It is unknown of yet if this error is specific to Thunderbolt only, or if it also happens with the same Radeon GPU installed inside of a desktop. Either way, the AMDGPU DC is not ready for prime time, and should not have been enabled by default until tested properly. -- You are receiving this mail because: You are watching the assignee of the bug. [View Less]

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dri-devel June 2018