dri-devel July 2018

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1883 discussions

[PULL] drm-intel-next
by Rodrigo Vivi 19 Jul '18

19 Jul '18

Hi Dave, This is our final pull request for 4.19. I was waiting some gvt pull that I had nacked for lack of review, but that didn't came on time and it will have to wait for next-fixes or later. Here goes drm-intel-next-2018-07-19: On GEM side: - GuC related fixes (Chris, Michal) - GTT read-only pages support (Jon, Chris) - More selftests fixes (Chris) - More GPU reset improvements (Chris) - Flush caches after GGTT writes (Chris) - Handle recursive shrinker for vma->last_active allocation (Chris) - Other execlists fixes (Chris) On Display side: - GLK HDMI fix (Clint) - Rework and cleanup around HPD pin (Ville) - Preparation work for Display Stream Compression support coming on ICL (Anusha) - Nuke LVDS lid notification (Ville) - Assume eDP is always connected (Ville) - Kill intel panel detection (Ville) drm-intel-next-2018-07-12: On GVT there's the addition of vGPU huge page support for guest, with one BXT fix and gvt dependency handling. On Display side there's: - More PSR clean up and fixes (Rodrigo, DK and Tarun) - GMBUS improvements for HDCP2.2 compliance (Ram) - Fix strncpy truncation on intel_tv (Dominique) - Cleanup modesetting on load-error path (Chris) On GEM side: - Gem init hw fix (Michal) - More selftests fixes (Michal, Chris) - Execlists optimizations (Chris) - Introduce i915_address_space.mutex (Chris) - Stolen memory support for Ice Lake (Paulo) - Unwind HW init after GVT setup failure (Chris) - Other fixes for gpu parking, gem_suspend, and handcheck reset (Chris) Thanks, Rodrigo. The following changes since commit 82edc7e8b8c06151bdc653935bc13b83e2f0fcfa: drm/i915: Update DRIVER_DATE to 20180709 (2018-07-09 15:39:27 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2018-07-19 for you to fetch changes up to ef821e3f14e868779505bf08f96afb4eade53652: drm/i915: Update DRIVER_DATE to 20180719 (2018-07-19 08:47:59 -0700) ---------------------------------------------------------------- On GEM side: - GuC related fixes (Chris, Michal) - GTT read-only pages support (Jon, Chris) - More selftests fixes (Chris) - More GPU reset improvements (Chris) - Flush caches after GGTT writes (Chris) - Handle recursive shrinker for vma->last_active allocation (Chris) - Other execlists fixes (Chris) On Display side: - GLK HDMI fix (Clint) - Rework and cleanup around HPD pin (Ville) - Preparation work for Display Stream Compression support coming on ICL (Anusha) - Nuke LVDS lid notification (Ville) - Assume eDP is always connected (Ville) - Kill intel panel detection (Ville) ---------------------------------------------------------------- Anusha Srivatsa (4): drm/i915/icl: Add VIDEO_DIP registers i915/dp/dsc: Add DSC PPS register definitions i915/dp/dsc: Add Rate Control Buffer Threshold Registers i915/dp/dsc: Add Rate Control Range Parameter Registers Changbin Du (14): drm/i915/gvt: Add new 64K entry type drm/i915/gvt: Add PTE IPS bit operations drm/i915/gvt: Handle MMIO GEN8_GAMW_ECO_DEV_RW_IA for 64K GTT drm/i915/gvt: Detect 64K gtt entry by IPS bit of PDE drm/i915/gvt: Add software PTE flag to mark special 64K splited entry drm/i915/gvt: Add GTT clear_pse operation drm/i915/gvt: Split ppgtt_alloc_spt into two parts drm/i915/gvt: Make PTE iterator 64K entry aware drm/i915/gvt: Add 64K huge gtt support drm/i915/kvmgt: Support setting dma map for huge pages drm/i915/gvt: Add 2M huge gtt support drm/i915/gvt: Handle special sequence on PDE IPS bit drm/i915/gvt: Fix error handling in ppgtt_populate_spt_by_guest_entry drm/i915: Enable platform support for vGPU huge gtt pages Chris Wilson (34): drm/i915: Remove function details from device error messages drm/i915/selftests: Constrain mock_gtt tests to fit within RAM drm/i915/selftests: Filter out both physical address swizzles drm/i915: Only reset hangcheck at the start of an activity cycle drm/i915: Tidy i915_gem_suspend() drm/i915: Flush the residual parking on emergency shutdown drm/i915: Cleanup modesetting on load-error path drm/i915: Unwind HW init after GVT setup failure drm/i915: Introduce i915_address_space.mutex drm/i915/selftests: Add a safety net to live_workarounds drm/i915/execlists: Switch to rb_root_cached drm/i915: Silence warning for no vlv powercontext drm/i915/guc: Skip cleaning up the doorbells on error-before-allocate drm/i915/guc: Protect against NULL client dereference in error path drm/i915/gtt: Disable read-only support under GVT drm/i915: Prevent writing into a read-only object via a GGTT mmap drm/i915: Reject attempted pwrites into a read-only object drm/i915/userptr: Enable read-only support on gen8+ drm/i915/guc: Protect against no desc-pool on premature shutdown drm/i915/selftests: Include the start of each subtest in the GEM trace drm/i915: Do not short-circuit tasklets during reset drm/i915/execlists: Drop clear_gtiir() on GPU reset drm/i915/selftests: Downgrade igt_timeout message drm/i915: Remove pci private pointer after destroying the device private drm/i915/execlists: Disable submission tasklet upon wedging drm/i915/execlists: Always clear preempt status on cancelling all drm/i915/selftests: Force a preemption hang drm/i915/selftests: Exercise reset to break stuck GTT eviction drm/i915/selftests: Free the backing store between iterations drm/i915: Flush chipset caches after GGTT writes drm/i915: Always retire residual requests before suspend drm/i915/guc: Keep guc submission permanently engaged drm/i915: Handle recursive shrinker for vma->last_active allocation drm/i915/execlists: Move the assertion we have the rpm wakeref down Clint Taylor (1): drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. Colin Xu (1): drm/i915/gvt: Handle EDP_PSR_IMR and EDP_PSR_IIR for BXT. Dhinakaran Pandiyan (1): drm/i915/psr: Split sink status into a separate debugfs node Dominique Martinet (1): drm/i915/tv: fix strncpy truncation warning Hang Yuan (1): drm/i915/gvt: declare gvt as i915's soft dependency Jon Bloomfield (2): drm/i915/gtt: Add read only pages to gen8_pte_encode drm/i915/gtt: Read-only pages for insert_entries on bdw+ Michał Winiarski (3): drm/i915: Tidy error handling in i915_gem_init_hw drm/i915/selftests: Fixup GuC FW negative test drm/i915/guc: Disable rpm wakeref asserts in GuC irq handler Paulo Zanoni (2): x86/gpu: reserve ICL's graphics stolen memory drm/i915: use the ICL stolen memory Ramalingam C (2): drm/i915/gmbus: Increase the Bytes per Rd/Wr Op drm/i915/gmbus: Enable burst read Rodrigo Vivi (6): Merge tag 'gvt-next-2018-07-11' of https://github.com/intel/gvt-linux into drm-intel-next-queued drm/i915/psr: Remove useless function calls. drm/i915/psr: Remove few mod parameters option. drm/i915: Update DRIVER_DATE to 20180712 drm/i915: Kill sink_crc for good drm/i915: Update DRIVER_DATE to 20180719 Tarun Vyas (1): drm/i915: Use crtc_state->has_psr instead of CAN_PSR for pipe update Ville Syrjälä (10): drm/i915: Introduce for_each_intel_dp() drm/i915: Introduce intel_encoder_is_dig_port() drm/i915: Rewrite mst suspend/resume in terms of encoders drm/i915: Nuke dev_priv->irq_port[] drm/i915: s/int i/enum hpd_pin pin/ drm/i915: Pass hpd_pin to long_pulse_detect() drm/i915: Print the long_mask alongside the pin_mask drm/i915: Nuke the LVDS lid notifier drm/i915: Assume eDP is always connected drm/i915: Remove intel_panel_detect() arch/x86/kernel/early-quirks.c | 18 + drivers/gpu/drm/drm_gem.c | 9 + drivers/gpu/drm/i915/gvt/gtt.c | 423 +++++++++++++++++--- drivers/gpu/drm/i915/gvt/gtt.h | 9 + drivers/gpu/drm/i915/gvt/gvt.c | 4 + drivers/gpu/drm/i915/gvt/handlers.c | 39 +- drivers/gpu/drm/i915/gvt/hypercall.h | 2 +- drivers/gpu/drm/i915/gvt/kvmgt.c | 126 ++++-- drivers/gpu/drm/i915/gvt/mpt.h | 7 +- drivers/gpu/drm/i915/gvt/vgpu.c | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 150 ++----- drivers/gpu/drm/i915/i915_drv.c | 40 +- drivers/gpu/drm/i915/i915_drv.h | 21 +- drivers/gpu/drm/i915/i915_gem.c | 76 ++-- drivers/gpu/drm/i915/i915_gem_gtt.c | 88 +++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 9 +- drivers/gpu/drm/i915/i915_gem_object.h | 14 +- drivers/gpu/drm/i915/i915_gem_shrinker.c | 12 + drivers/gpu/drm/i915/i915_gem_stolen.c | 38 +- drivers/gpu/drm/i915/i915_gem_userptr.c | 18 +- drivers/gpu/drm/i915/i915_irq.c | 115 +++--- drivers/gpu/drm/i915/i915_params.c | 6 +- drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/i915_pci.c | 13 +- drivers/gpu/drm/i915/i915_reg.h | 436 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_selftest.h | 2 +- drivers/gpu/drm/i915/i915_vma.c | 8 + drivers/gpu/drm/i915/intel_ddi.c | 14 +- drivers/gpu/drm/i915/intel_display.c | 23 +- drivers/gpu/drm/i915/intel_display.h | 4 + drivers/gpu/drm/i915/intel_dp.c | 221 ++--------- drivers/gpu/drm/i915/intel_drv.h | 55 ++- drivers/gpu/drm/i915/intel_engine_cs.c | 19 +- drivers/gpu/drm/i915/intel_guc.c | 2 + drivers/gpu/drm/i915/intel_guc_submission.c | 72 ++-- drivers/gpu/drm/i915/intel_gvt.c | 3 + drivers/gpu/drm/i915/intel_hotplug.c | 118 +++--- drivers/gpu/drm/i915/intel_i2c.c | 70 +++- drivers/gpu/drm/i915/intel_lrc.c | 147 ++----- drivers/gpu/drm/i915/intel_lrc.h | 2 + drivers/gpu/drm/i915/intel_lvds.c | 136 +------ drivers/gpu/drm/i915/intel_panel.c | 20 - drivers/gpu/drm/i915/intel_pm.c | 8 +- drivers/gpu/drm/i915/intel_psr.c | 17 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +- drivers/gpu/drm/i915/intel_ringbuffer.h | 40 +- drivers/gpu/drm/i915/intel_sprite.c | 2 +- drivers/gpu/drm/i915/intel_tv.c | 3 +- drivers/gpu/drm/i915/selftests/huge_pages.c | 6 + drivers/gpu/drm/i915/selftests/i915_gem_context.c | 113 +++++- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +- drivers/gpu/drm/i915/selftests/i915_gem_object.c | 3 +- drivers/gpu/drm/i915/selftests/i915_selftest.c | 2 + drivers/gpu/drm/i915/selftests/igt_wedge_me.h | 58 +++ drivers/gpu/drm/i915/selftests/intel_guc.c | 10 +- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 171 +++++++- drivers/gpu/drm/i915/selftests/intel_lrc.c | 115 ++++++ drivers/gpu/drm/i915/selftests/intel_workarounds.c | 8 +- include/drm/drm_vma_manager.h | 1 + include/drm/i915_drm.h | 4 +- 60 files changed, 2158 insertions(+), 1010 deletions(-) create mode 100644 drivers/gpu/drm/i915/selftests/igt_wedge_me.h

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[PATCH v2] drm/amd/display/dc/dce: Fix multiple potential integer overflows
by Gustavo A. R. Silva 19 Jul '18

19 Jul '18

Add suffix ULL to constant 5 and cast variables target_pix_clk_khz and feedback_divider to uint64_t in order to avoid multiple potential integer overflows and give the compiler complete information about the proper arithmetic to use. Notice that such constant and variables are used in contexts that expect expressions of type uint64_t (64 bits, unsigned). The current casts to uint64_t effectively apply to each expression as a whole, but they do not prevent them from being evaluated using 32-bit arithmetic instead of 64-bit arithmetic. Also, once the expressions are properly evaluated using 64-bit arithmentic, there is no need for the parentheses that enclose them. Addresses-Coverity-ID: 1460245 ("Unintentional integer overflow") Addresses-Coverity-ID: 1460286 ("Unintentional integer overflow") Addresses-Coverity-ID: 1460401 ("Unintentional integer overflow") Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Gustavo A. R. Silva <gustavo(a)embeddedor.com> --- Changes in v2: - Add suffix ULL to constant 5 instead of UL. Thanks to Michel Dänzer for pointing this out. drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 88b09dd..ca13775 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -133,7 +133,7 @@ static bool calculate_fb_and_fractional_fb_divider( uint64_t feedback_divider; feedback_divider = - (uint64_t)(target_pix_clk_khz * ref_divider * post_divider); + (uint64_t)target_pix_clk_khz * ref_divider * post_divider; feedback_divider *= 10; /* additional factor, since we divide by 10 afterwards */ feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor); @@ -145,8 +145,8 @@ static bool calculate_fb_and_fractional_fb_divider( * of fractional feedback decimal point and the fractional FB Divider precision * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/ - feedback_divider += (uint64_t) - (5 * calc_pll_cs->fract_fb_divider_precision_factor); + feedback_divider += 5ULL * + calc_pll_cs->fract_fb_divider_precision_factor; feedback_divider = div_u64(feedback_divider, calc_pll_cs->fract_fb_divider_precision_factor * 10); @@ -203,8 +203,8 @@ static bool calc_fb_divider_checking_tolerance( &fract_feedback_divider); /*Actual calculated value*/ - actual_calc_clk_khz = (uint64_t)(feedback_divider * - calc_pll_cs->fract_fb_divider_factor) + + actual_calc_clk_khz = (uint64_t)feedback_divider * + calc_pll_cs->fract_fb_divider_factor + fract_feedback_divider; actual_calc_clk_khz *= calc_pll_cs->ref_freq_khz; actual_calc_clk_khz = -- 2.7.4

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[Bug 107065] "BUG: unable to handle kernel paging request at 0000000000002000" at amdgpu_vm_cpu_set_ptes at S3 resume
by bugzilla-daemon＠freedesktop.org 19 Jul '18

19 Jul '18

https://bugs.freedesktop.org/show_bug.cgi?id=107065 Bug ID: 107065 Summary: "BUG: unable to handle kernel paging request at 0000000000002000" at amdgpu_vm_cpu_set_ptes at S3 resume Product: DRI Version: DRI git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: major Priority: medium Component: DRM/AMDgpu Assignee: dri-devel(a)lists.freedesktop.org Reporter: jb5sgc1n.nya(a)20mm.eu When I resume from S3 using the 4.17.2-1-ARCH kernel, with amdgpu.vm_update_mode=3 (for reasons explained in https://bugs.freedesktop.org/show_bug.cgi?id=102322 ) first the amdgpu driver and shortly thereafter the system crashes with the following kernel messages: Jun 28 21:14:25 ryzen kernel: ACPI: Low-level resume complete Jun 28 21:14:25 ryzen kernel: PM: Restoring platform NVS memory Jun 28 21:14:25 ryzen kernel: Enabling non-boot CPUs ... ... Jun 28 21:14:25 ryzen kernel: [drm] PCIE GART of 256M enabled (table at 0x000000F400040000). Jun 28 21:14:25 ryzen kernel: [drm] UVD and UVD ENC initialized successfully. Jun 28 21:14:25 ryzen kernel: [drm] VCE initialized successfully. Jun 28 21:14:25 ryzen kernel: OOM killer enabled. Jun 28 21:14:25 ryzen kernel: Restarting tasks ... done. Jun 28 21:14:25 ryzen kernel: PM: suspend exit Jun 28 21:14:25 ryzen kernel: BUG: unable to handle kernel paging request at 0000000000002000 Jun 28 21:14:25 ryzen kernel: PGD 0 P4D 0 Jun 28 21:14:25 ryzen kernel: Oops: 0002 [#1] PREEMPT SMP NOPTI Jun 28 21:14:25 ryzen kernel: Modules linked in: arc4 md4 sha512_ssse3 sha512_generic nls_utf8 cifs ccm dns_resolver fscache> Jun 28 21:14:25 ryzen kernel: bluetooth snd_hwdep snd_pcm eeepc_wmi snd_timer asus_wmi snd sparse_keymap mxm_wmi wmi_bmof i> Jun 28 21:14:25 ryzen kernel: dm_crypt dm_mod i2c_dev Jun 28 21:14:25 ryzen kernel: CPU: 3 PID: 882 Comm: amdgpu_cs:0 Tainted: G W O 4.17.2-1-ARCH #1 Jun 28 21:14:25 ryzen kernel: Hardware name: System manufacturer System Product Name/PRIME X370-PRO, BIOS 4011 04/19/2018 Jun 28 21:14:25 ryzen kernel: RIP: 0010:gmc_v8_0_set_pte_pde+0x1b/0x30 [amdgpu] Jun 28 21:14:25 ryzen kernel: RSP: 0018:ffffb8b8c3fa7a70 EFLAGS: 00010202 Jun 28 21:14:25 ryzen kernel: RAX: 000000fffffff000 RBX: 0000000000000001 RCX: 000000f400956001 Jun 28 21:14:25 ryzen kernel: RDX: 0000000000002000 RSI: 0000000000002000 RDI: ffff9edab48a0000 Jun 28 21:14:25 ryzen kernel: RBP: 0000000000000000 R08: 0000000000000001 R09: 0000000000000000 Jun 28 21:14:25 ryzen kernel: R10: ffffffffc03e4c50 R11: ffff9edab30d0800 R12: 0000000000002000 Jun 28 21:14:25 ryzen kernel: R13: 0000000000000001 R14: ffffb8b8c3fa7ae8 R15: 000000f400956000 Jun 28 21:14:25 ryzen kernel: FS: 00007f622bb59700(0000) GS:ffff9edadecc0000(0000) knlGS:0000000000000000 Jun 28 21:14:25 ryzen kernel: CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 Jun 28 21:14:25 ryzen kernel: CR2: 0000000000002000 CR3: 00000007e03f8000 CR4: 00000000003406e0 Jun 28 21:14:25 ryzen kernel: Call Trace: Jun 28 21:14:25 ryzen kernel: amdgpu_vm_cpu_set_ptes+0x76/0xf0 [amdgpu] Jun 28 21:14:25 ryzen kernel: amdgpu_vm_update_directories+0x1ca/0x3c0 [amdgpu] Jun 28 21:14:25 ryzen kernel: ? amdgpu_vm_do_copy_ptes+0xc0/0xc0 [amdgpu] Jun 28 21:14:25 ryzen kernel: amdgpu_cs_ioctl+0x1169/0x1a70 [amdgpu] Jun 28 21:14:25 ryzen kernel: ? dequeue_entity+0x156/0x950 Jun 28 21:14:25 ryzen kernel: ? amdgpu_cs_find_mapping+0x110/0x110 [amdgpu] Jun 28 21:14:25 ryzen kernel: drm_ioctl_kernel+0x5b/0xb0 [drm] Jun 28 21:14:25 ryzen kernel: drm_ioctl+0x1b7/0x370 [drm] Jun 28 21:14:25 ryzen kernel: ? amdgpu_cs_find_mapping+0x110/0x110 [amdgpu] Jun 28 21:14:25 ryzen kernel: amdgpu_drm_ioctl+0x49/0x80 [amdgpu] Jun 28 21:14:25 ryzen kernel: do_vfs_ioctl+0xa4/0x610 Jun 28 21:14:25 ryzen kernel: ksys_ioctl+0x60/0x90 Jun 28 21:14:25 ryzen kernel: __x64_sys_ioctl+0x16/0x20 Jun 28 21:14:25 ryzen kernel: do_syscall_64+0x5b/0x170 Jun 28 21:14:25 ryzen kernel: entry_SYSCALL_64_after_hwframe+0x44/0xa9 Jun 28 21:14:25 ryzen kernel: RIP: 0033:0x7f623b586667 Jun 28 21:14:25 ryzen kernel: RSP: 002b:00007f622bb58a98 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 Jun 28 21:14:25 ryzen kernel: RAX: ffffffffffffffda RBX: 00007f622bb58b88 RCX: 00007f623b586667 Jun 28 21:14:25 ryzen kernel: RDX: 00007f622bb58b00 RSI: 00000000c0186444 RDI: 000000000000000b Jun 28 21:14:25 ryzen kernel: RBP: 00007f622bb58b00 R08: 00007f622bb58bb0 R09: 0000000000000010 Jun 28 21:14:25 ryzen kernel: R10: 00007f622bb58bb0 R11: 0000000000000246 R12: 00000000c0186444 Jun 28 21:14:25 ryzen kernel: R13: 000000000000000b R14: 000000000000000a R15: 0000000000000000 Jun 28 21:14:25 ryzen kernel: Code: 8b 80 d8 00 00 00 e9 85 ed 5c c2 0f 1f 44 00 00 0f 1f 44 00 00 48 b8 00 f0 ff ff ff 00 0> Jun 28 21:14:25 ryzen kernel: RIP: gmc_v8_0_set_pte_pde+0x1b/0x30 [amdgpu] RSP: ffffb8b8c3fa7a70 Jun 28 21:14:25 ryzen kernel: CR2: 0000000000002000 Jun 28 21:14:25 ryzen kernel: ---[ end trace 6fce4be2faa5be7e ]--- -- You are receiving this mail because: You are the assignee for the bug.

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[PATCH] Revert "drm/sun4i: Handle DRM_BUS_FLAG_PIXDATA_*EDGE"
by Paul Kocialkowski 19 Jul '18

19 Jul '18

This reverts commit 2c17a4368aad2b88b68e4390c819e226cf320f70. The offending commit triggers a run-time fault when accessing the panel element of the sun4i_tcon structure when no such panel is attached. It was apparently assumed in said commit that a panel is always used with the TCON. Although it is often the case, this is not always true. For instance a bridge might be used instead of a panel. This issue was discovered using an A13-OLinuXino, that uses the TCON in RGB mode for a simple DAC-based VGA bridge. Cc: stable(a)vger.kernel.org Signed-off-by: Paul Kocialkowski <paul.kocialkowski(a)bootlin.com> --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index c3d92d537240..8045871335b5 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -17,7 +17,6 @@ #include <drm/drm_encoder.h> #include <drm/drm_modes.h> #include <drm/drm_of.h> -#include <drm/drm_panel.h> #include <uapi/drm/drm_mode.h> @@ -350,9 +349,6 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, const struct drm_display_mode *mode) { - struct drm_panel *panel = tcon->panel; - struct drm_connector *connector = panel->connector; - struct drm_display_info display_info = connector->display_info; unsigned int bp, hsync, vsync; u8 clk_delay; u32 val = 0; @@ -410,27 +406,6 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, if (mode->flags & DRM_MODE_FLAG_PVSYNC) val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; - /* - * On A20 and similar SoCs, the only way to achieve Positive Edge - * (Rising Edge), is setting dclk clock phase to 2/3(240°). - * By default TCON works in Negative Edge(Falling Edge), - * this is why phase is set to 0 in that case. - * Unfortunately there's no way to logically invert dclk through - * IO_POL register. - * The only acceptable way to work, triple checked with scope, - * is using clock phase set to 0° for Negative Edge and set to 240° - * for Positive Edge. - * On A33 and similar SoCs there would be a 90° phase option, - * but it divides also dclk by 2. - * Following code is a way to avoid quirks all around TCON - * and DOTCLOCK drivers. - */ - if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE) - clk_set_phase(tcon->dclk, 240); - - if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE) - clk_set_phase(tcon->dclk, 0); - regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE, val); -- 2.17.0

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[PATCH RESEND v2 1/2] drm/sun4i: sun4i: Register quirks with the backend structure
by Paul Kocialkowski 19 Jul '18

19 Jul '18

In prevision for introducing a new quirk that will be used at atomic plane check time, register the quirks structure with the backend structure. This way, it can easily be grabbed where needed. Signed-off-by: Paul Kocialkowski <paul.kocialkowski(a)bootlin.com> --- Version 2 of this series was resent to include this patch, that was missing from the original v2 submission but is still very much needed. drivers/gpu/drm/sun4i/sun4i_backend.c | 2 ++ drivers/gpu/drm/sun4i/sun4i_backend.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index de0a76dfa1a2..075cb0ff56ca 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -882,6 +882,8 @@ static int sun4i_backend_bind(struct device *dev, struct device *master, : SUN4I_BACKEND_MODCTL_OUT_LCD0)); } + backend->quirks = quirks; + return 0; err_disable_ram_clk: diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.h b/drivers/gpu/drm/sun4i/sun4i_backend.h index 4caee0392fa4..ad6609323f0e 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.h +++ b/drivers/gpu/drm/sun4i/sun4i_backend.h @@ -187,6 +187,8 @@ struct sun4i_backend { /* Protects against races in the frontend teardown */ spinlock_t frontend_lock; bool frontend_teardown; + + const struct sun4i_backend_quirks *quirks; }; static inline struct sun4i_backend * -- 2.18.0

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[radeon-alex:drm-next-4.19-wip 101/128] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega12_hwmgr.c:504 vega12_get_dpm_frequency_by_index() error: uninitialized symbol 'result'.
by Dan Carpenter 19 Jul '18

19 Jul '18

tree: git://people.freedesktop.org/~agd5f/linux.git drm-next-4.19-wip head: 73b1f7132d9ad442b24d70d8769a4642302d6b49 commit: ce7577a2194b58bf7faf303612a24b7cd5210afc [101/128] drm/amdgpu/pp: split out common smumgr smu9 code smatch warnings: drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega12_hwmgr.c:504 vega12_get_dpm_frequency_by_index() error: uninitialized symbol 'result'. git remote add radeon-alex git://people.freedesktop.org/~agd5f/linux.git git remote update radeon-alex git checkout ce7577a2194b58bf7faf303612a24b7cd5210afc vim +/result +504 drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega12_hwmgr.c 7436854e Kenneth Feng 2018-03-20 487 7436854e Kenneth Feng 2018-03-20 488 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, 7436854e Kenneth Feng 2018-03-20 489 PPCLK_e clkID, uint32_t index, uint32_t *clock) 7436854e Kenneth Feng 2018-03-20 490 { 7436854e Kenneth Feng 2018-03-20 491 int result; 7436854e Kenneth Feng 2018-03-20 492 7436854e Kenneth Feng 2018-03-20 493 /* 7436854e Kenneth Feng 2018-03-20 494 *SMU expects the Clock ID to be in the top 16 bits. 7436854e Kenneth Feng 2018-03-20 495 *Lower 16 bits specify the level 7436854e Kenneth Feng 2018-03-20 496 */ 7436854e Kenneth Feng 2018-03-20 497 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, 7436854e Kenneth Feng 2018-03-20 498 PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index)) == 0, 7436854e Kenneth Feng 2018-03-20 499 "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!", 7436854e Kenneth Feng 2018-03-20 500 return -EINVAL); 7436854e Kenneth Feng 2018-03-20 501 ce7577a2 Alex Deucher 2018-07-12 502 *clock = smum_get_argument(hwmgr); 7436854e Kenneth Feng 2018-03-20 503 7436854e Kenneth Feng 2018-03-20 @504 return result; ^^^^^^^^^^^^^ Should just be return 0; 7436854e Kenneth Feng 2018-03-20 505 } 7436854e Kenneth Feng 2018-03-20 506 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

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[PATCH] MAINTAINERS: add new TTM maintainers
by Christian König 19 Jul '18

19 Jul '18

Roger unfortunately doesn't work for AMD any longer. So add Rui and Jerry as co-maintainer as well. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 9d5eeff51b5f..e613df455ae0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4884,7 +4884,8 @@ F: Documentation/gpu/xen-front.rst DRM TTM SUBSYSTEM M: Christian Koenig <christian.koenig(a)amd.com> -M: Roger He <Hongbo.He(a)amd.com> +M: Huang Rui <ray.huang(a)amd.com> +M: Junwei Zhang <Jerry.Zhang(a)amd.com> T: git git://people.freedesktop.org/~agd5f/linux S: Maintained L: dri-devel(a)lists.freedesktop.org -- 2.14.1

2 1

[PATCH v2 0/1] fbdev/core: Disable console-lock warnings when fb.lockless_register_fb is set
by Thomas Zimmermann 19 Jul '18

19 Jul '18

Hi, this is a follow-up patch for the recent addition of 'ignore_console_lock_warning' to the console module [1] and should probably go through the same tree. When debugging fbdev console registration, the console-lock warnings will now be disabled temporarily. Best regards Thomas [1] https://marc.info/?l=dri-devel&m=153140585411176&w=2 v2: - restore ignore_console_lock_warning if lock_fb_info() fails Thomas Zimmermann (1): fbdev/core: Disable console-lock warnings when fb.lockless_register_fb is set drivers/video/fbdev/core/fbmem.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) -- 2.18.0

5 8

[PATCH] drm/xen-front: Fix error code in xen_drm_front_gem_get_sg_table()
by Dan Carpenter 19 Jul '18

19 Jul '18

The xen_drm_front_gem_get_sg_table() function is supposed to return error pointer. The current code, would trigger a NULL dereference in drm_gem_map_dma_buf(). Fixes: c575b7eeb89f ("drm/xen-front: Add support for Xen PV display frontend") Signed-off-by: Dan Carpenter <dan.carpenter(a)oracle.com> diff --git a/drivers/gpu/drm/xen/xen_drm_front_gem.c b/drivers/gpu/drm/xen/xen_drm_front_gem.c index c85bfe7571cb..4507bc03ed8f 100644 --- a/drivers/gpu/drm/xen/xen_drm_front_gem.c +++ b/drivers/gpu/drm/xen/xen_drm_front_gem.c @@ -179,7 +179,7 @@ struct sg_table *xen_drm_front_gem_get_sg_table(struct drm_gem_object *gem_obj) struct xen_gem_object *xen_obj = to_xen_gem_obj(gem_obj); if (!xen_obj->pages) - return NULL; + return ERR_PTR(-EINVAL); return drm_prime_pages_to_sg(xen_obj->pages, xen_obj->num_pages); }

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[bug report] drm: re-enable error handling
by Dan Carpenter 19 Jul '18

19 Jul '18

Hello Nicholas Mc Guire, The patch d530b5f1ca0b: "drm: re-enable error handling" from Jul 14, 2018, leads to the following static checker warning: drivers/gpu/drm/drm_context.c:375 drm_legacy_addctx() warn: unsigned 'ctx->handle' is never less than zero. drivers/gpu/drm/drm_context.c 359 int drm_legacy_addctx(struct drm_device *dev, void *data, 360 struct drm_file *file_priv) 361 { 362 struct drm_ctx_list *ctx_entry; 363 struct drm_ctx *ctx = data; 364 365 if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT) && 366 !drm_core_check_feature(dev, DRIVER_LEGACY)) 367 return -EINVAL; 368 369 ctx->handle = drm_legacy_ctxbitmap_next(dev); 370 if (ctx->handle == DRM_KERNEL_CONTEXT) { 371 /* Skip kernel's context and get a new one. */ 372 ctx->handle = drm_legacy_ctxbitmap_next(dev); 373 } 374 DRM_DEBUG("%d\n", ctx->handle); 375 if (ctx->handle < 0) { ^^^^^^^^^^^^^^^ This can't be true. 376 DRM_DEBUG("Not enough free contexts.\n"); 377 /* Should this return -EBUSY instead? */ 378 return -ENOMEM; 379 } regards, dan carpenter

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dri-devel July 2018