Adding PCI IDs to different projects is a boring manual task that
motivated me to create this series. The idea is to centralize the IDs in
the kernel header and let other projects copy it.
Initially my plan was to convert all gens, back to gen2, but that proved
slightly difficult since there are some corner cases to cover and I
didn't want to block the important part, i.e.: for recent gens, there's
no risk of missing a PCI ID.
v2: address comments from Chris by pulling it out to a separate .…
[View More]c
v3: remove/add comments on first patch and rebase the rest
Discussed on v2 but left for later:
- replace intel_is_genx() with a simple check for bufmgr->gen,
after making sure said variable is initialized on all code
paths.
- treat unknown gen as a future gen
- convert gen < 9 to use the new header
Lucas De Marchi (5):
intel: add generic functions to check PCI ID
intel: make gen11 use generic gen macro
intel: make gen10 use generic gen macro
intel: make gen9 use generic gen macro
intel: get gen once for gen >= 9
intel/Makefile.sources | 1 +
intel/i915_pciids.h | 461 +++++++++++++++++++++++++++++++++++++++
intel/intel_bufmgr_gem.c | 8 +-
intel/intel_chipset.c | 85 ++++++++
intel/intel_chipset.h | 253 +--------------------
intel/intel_decode.c | 8 +-
intel/meson.build | 2 +-
7 files changed, 561 insertions(+), 257 deletions(-)
create mode 100644 intel/i915_pciids.h
create mode 100644 intel/intel_chipset.c
--
2.17.1
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Hi Dave,
Here goes drm-intel-fixes-2018-09-05:
The critical fix here on display side is the DP MST regression one.
But this pull also include fixes for DP SST, small VDSC register fix
and GVT's bucked with "BXT fixes, two guest warning fixes, dmabuf
format mod fix and one for recent multiple VM timeout failure."
Thanks,
Rodrigo.
The following changes since commit 57361846b52bc686112da6ca5368d11210796804:
Linux 4.19-rc2 (2018-09-02 14:37:30 -0700)
are available in the Git repository at:
…
[View More]git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2018-09-05
for you to fetch changes up to 2b82435cb90bed2c5f8398730d964dd11602217c:
drm/i915/dp_mst: Fix enabling pipe clock for all streams (2018-09-03 21:34:36 -0700)
----------------------------------------------------------------
The critical fix here on display side is the DP MST regression one.
But this pull also include fixes for DP SST, small VDSC register fix
and GVT's bucked with "BXT fixes, two guest warning fixes, dmabuf
format mod fix and one for recent multiple VM timeout failure."
----------------------------------------------------------------
Colin Xu (2):
drm/i915/gvt: Make correct handling to vreg BXT_PHY_CTL_FAMILY
drm/i915/gvt: Handle GEN9_WM_CHICKEN3 with F_CMD_ACCESS.
Hang Yuan (1):
drm/i915/gvt: move intel_runtime_pm_get out of spin_lock in stop_schedule
Imre Deak (1):
drm/i915/dp_mst: Fix enabling pipe clock for all streams
Jan-Marek Glogowski (1):
drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"
Manasi Navare (1):
drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
Rodrigo Vivi (1):
Merge tag 'gvt-fixes-2018-09-04' of https://github.com/intel/gvt-linux into drm-intel-fixes
Xiaolin Zhang (1):
drm/i915/gvt: emulate gen9 dbuf ctl register access
Zhenyu Wang (2):
drm/i915/gvt: Fix drm_format_mod value for vGPU plane
drm/i915/gvt: Give new born vGPU higher scheduling chance
drivers/gpu/drm/i915/gvt/dmabuf.c | 33 ++++++++++++++++++++++-------
drivers/gpu/drm/i915/gvt/fb_decoder.c | 5 ++---
drivers/gpu/drm/i915/gvt/fb_decoder.h | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 33 +++++++++++++++++++++++------
drivers/gpu/drm/i915/gvt/mmio_context.c | 2 --
drivers/gpu/drm/i915/gvt/sched_policy.c | 37 ++++++++++++++++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/intel_ddi.c | 17 ++++++++-------
drivers/gpu/drm/i915/intel_dp.c | 33 ++++++++++++++++-------------
drivers/gpu/drm/i915/intel_dp_mst.c | 4 ++++
10 files changed, 120 insertions(+), 50 deletions(-)
[View Less]
Adding PCI IDs to different projects is a boring manual task that
motivated me to create this series. The idea is to centralize the IDs in
the kernel header and let other projects copy it.
Initially my plan was to convert all gens, back to gen2, but that proved
slightly difficult since there are some corner cases to cover and I
didn't want to block the important part, i.e.: for recent gens, there's
no risk of missing a PCI ID.
v2: address comments from Chris by pulling it out to a separate .…
[View More]c
Lucas De Marchi (5):
intel: add generic functions to check PCI ID
intel: make gen11 use generic gen macro
intel: make gen10 use generic gen macro
intel: make gen9 use generic gen macro
intel: get gen once for gen >= 9
intel/Makefile.sources | 1 +
intel/i915_pciids.h | 461 +++++++++++++++++++++++++++++++++++++++
intel/intel_bufmgr_gem.c | 8 +-
intel/intel_chipset.c | 84 +++++++
intel/intel_chipset.h | 254 +--------------------
intel/intel_decode.c | 8 +-
intel/meson.build | 2 +-
7 files changed, 561 insertions(+), 257 deletions(-)
create mode 100644 intel/i915_pciids.h
create mode 100644 intel/intel_chipset.c
--
2.17.1
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From: Fabio Estevam <fabio.estevam(a)nxp.com>
Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com>
---
drivers/gpu/drm/panel/panel-seiko-43wvf1g.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c b/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
index 75f9253..70654f9 100644
--- a/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
+++ b/…
[View More]drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 NXP Semiconductors.
* Author: Marco Franchi <marco.franchi(a)nxp.com>
*
* Based on Panel Simple driver by Thierry Reding <treding(a)nvidia.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version
- * 2 as published by the Free Software Foundation.
*/
#include <linux/backlight.h>
--
2.7.4
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