dri-devel October 2019

dri-devel@lists.freedesktop.org

359 participants
1833 discussions

[GIT PULL FOR v5.5] R-Car DU changes
by Laurent Pinchart 15 Oct '19

15 Oct '19

Hi Dave, The following changes since commit 7ed093602e0e1b60a0fc074a9692687e7d2b723d: Merge tag 'drm-misc-next-2019-10-09-2' of git://anongit.freedesktop.org/drm/drm-misc into drm-next (2019-10-11 09:30:53 +1000) are available in the Git repository at: git://linuxtv.org/pinchartl/media.git tags/du-next-20191016 for you to fetch changes up to f3a36d469621e52a04392820fa96bc4f2a9d29e7: dt-bindings: display: renesas: Add r8a774b1 support (2019-10-16 00:28:32 +0300) ---------------------------------------------------------------- - R-Car DU support for R8A774B1 SoC - R-Car DU fixes for H2 ES2.0 and later revisions ---------------------------------------------------------------- Biju Das (5): dt-bindings: display: renesas: du: Document the r8a774b1 bindings drm: rcar-du: Add R8A774B1 support dt-bindings: display: renesas: lvds: Document r8a774b1 bindings drm: rcar-du: lvds: Add r8a774b1 support dt-bindings: display: renesas: Add r8a774b1 support Geert Uytterhoeven (1): drm: rcar_lvds: Fix color mismatches on R-Car H2 ES2.0 and later Jacopo Mondi (1): drm: rcar-du: kms: Expand comment in vsps parsing routine .../bindings/display/bridge/renesas,dw-hdmi.txt | 1 + .../bindings/display/bridge/renesas,lvds.txt | 1 + .../devicetree/bindings/display/renesas,du.txt | 2 ++ drivers/gpu/drm/rcar-du/rcar_du_drv.c | 30 ++++++++++++++++++++++ drivers/gpu/drm/rcar-du/rcar_du_kms.c | 6 ++++- drivers/gpu/drm/rcar-du/rcar_lvds.c | 29 ++++++++++++++++----- 6 files changed, 61 insertions(+), 8 deletions(-) -- Regards, Laurent Pinchart

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[PATCH 1/3] dt-bindings: arm: samsung: Force clkoutN names to be unique in PMU
by Krzysztof Kozlowski 15 Oct '19

15 Oct '19

The clkoutN names of clocks must be unique because they represent unique inputs of clock multiplexer. Signed-off-by: Krzysztof Kozlowski <krzk(a)kernel.org> --- Documentation/devicetree/bindings/arm/samsung/pmu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml index 73b56fc5bf58..d8e03716f5d2 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml @@ -53,8 +53,10 @@ properties: List of clock names for particular CLKOUT mux inputs minItems: 1 maxItems: 32 - items: - pattern: '^clkout([0-9]|[12][0-9]|3[0-1])$' + allOf: + - items: + pattern: '^clkout([0-9]|[12][0-9]|3[0-1])$' + - uniqueItems: true clocks: minItems: 1 -- 2.17.1

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[PATCH] drm: Add LT-tunable PHY repeater mode operations
by Siqueira, Rodrigo 15 Oct '19

15 Oct '19

LT-tunable PHY Repeaters can operate in two different modes: transparent (default) and non-transparent. The value 0x55 specifies the transparent mode, and 0xaa represents the non-transparent; this commit adds these two values as definitions. Cc: Abdoulaye Berthe <Abdoulaye.Berthe(a)amd.com> Cc: Harry Wentland <harry.wentland(a)amd.com> Cc: Leo Li <sunpeng.li(a)amd.com> Cc: Jani Nikula <jani.nikula(a)linux.intel.com> Cc: Manasi Navare <manasi.d.navare(a)intel.com> Cc: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Signed-off-by: Abdoulaye Berthe <Abdoulaye.Berthe(a)amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira(a)amd.com> --- include/drm/drm_dp_helper.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index bf62b43aaf2b..cfadeeef8492 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1034,6 +1034,10 @@ #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */ #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ +/* Repeater modes */ +#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */ +#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */ + /* DP HDCP message start offsets in DPCD address space */ #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET -- 2.23.0

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Re: [PATCH 3/4] dt-bindings: display: renesas: lvds: Document r8a774b1 bindings
by Rob Herring 15 Oct '19

15 Oct '19

On Mon, 30 Sep 2019 10:15:04 +0100, Biju Das wrote: > Document the RZ/G2N (R8A774B1) LVDS bindings. > > Signed-off-by: Biju Das <biju.das(a)bp.renesas.com> > --- > Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh(a)kernel.org>

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Re: [PATCH 1/4] dt-bindings: display: renesas: du: Document the r8a774b1 bindings
by Rob Herring 15 Oct '19

15 Oct '19

On Mon, 30 Sep 2019 10:15:02 +0100, Biju Das wrote: > Document the RZ/G2N (R8A774B1) SoC in the R-Car DU bindings. > > Signed-off-by: Biju Das <biju.das(a)bp.renesas.com> > --- > Documentation/devicetree/bindings/display/renesas,du.txt | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh(a)kernel.org>

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[PATCH] dt-bindings: display: Convert sharp, ld-d5116z01b panel to DT schema
by Jeffrey Hugo 15 Oct '19

15 Oct '19

Convert the sharp,ld-d5116z01b panel binding to DT schema. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo(a)gmail.com> --- .../display/panel/sharp,ld-d5116z01b.txt | 26 ---------------- .../display/panel/sharp,ld-d5116z01b.yaml | 30 +++++++++++++++++++ 2 files changed, 30 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt create mode 100644 Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.yaml diff --git a/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt b/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt deleted file mode 100644 index fd9cf39bde77..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt +++ /dev/null @@ -1,26 +0,0 @@ -Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel - -Required properties: -- compatible: should be "sharp,ld-d5116z01b" -- power-supply: regulator to provide the VCC supply voltage (3.3 volts) - -This binding is compatible with the simple-panel binding. - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in [1]. This -node should describe panel's video bus. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - panel: panel { - compatible = "sharp,ld-d5116z01b"; - power-supply = <&vlcd_3v3>; - - port { - panel_ep: endpoint { - remote-endpoint = <&bridge_out_ep>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.yaml b/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.yaml new file mode 100644 index 000000000000..fbb647eb33c9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sharp,ld-d5116z01b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel + +maintainers: + - Jeffrey Hugo <jeffrey.l.hugo(a)gmail.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sharp,ld-d5116z01b + + power-supply: true + backlight: true + port: true + no-hpd: true + +additionalProperties: false + +required: + - compatible + - power-supply + +... -- 2.17.1

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[PATCH v4] dt-bindings: display: Convert stm32 display bindings to json-schema
by Benjamin Gaignard 15 Oct '19

15 Oct '19

Convert the STM32 display binding to DT schema format using json-schema. Split the original bindings in two yaml files: - one for display controller (ltdc) - one for DSI controller Signed-off-by: Benjamin Gaignard <benjamin.gaignard(a)st.com> --- changes in v4: - describe interruptions items - remove unit address from port property - remove dma-ranges (DT patches send too) changes in v3: - use (GPL-2.0-only OR BSD-2-Clause) license changes in v2: - use BSD-2-Clause license - add panel property - fix identation - remove pinctrl-names: true - remove pinctrl-[0-9]+: true - rework ports block to include port@0 and port@1 - use const for #adress-cells and #size-cells - add additionalProperties: false .../devicetree/bindings/display/st,stm32-dsi.yaml | 151 +++++++++++++++++++++ .../devicetree/bindings/display/st,stm32-ltdc.txt | 144 -------------------- .../devicetree/bindings/display/st,stm32-ltdc.yaml | 81 +++++++++++ 3 files changed, 232 insertions(+), 144 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/st,stm32-dsi.yaml delete mode 100644 Documentation/devicetree/bindings/display/st,stm32-ltdc.txt create mode 100644 Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml diff --git a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml new file mode 100644 index 000000000000..a99532b38589 --- /dev/null +++ b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 DSI host controller + +maintainers: + - Philippe Cornu <philippe.cornu(a)st.com> + - Yannick Fertre <yannick.fertre(a)st.com> + +description: + The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller. + +properties: + compatible: + const: st,stm32-dsi + + reg: + maxItems: 1 + + clocks: + items: + - description: Module Clock + - description: DSI bus clock + - description: Pixel clock + minItems: 2 + maxItems: 3 + + clock-names: + items: + - const: pclk + - const: ref + - const: px_clk + minItems: 2 + maxItems: 3 + + resets: + maxItems: 1 + + reset-names: + items: + - const: apb + + phy-dsi-supply: + maxItems: 1 + description: + Phandle of the regulator that provides the supply voltage. + + ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + Documentation/devicetree/bindings/graph.txt + properties: + port@0: + type: object + description: + DSI input port node, connected to the ltdc rgb output port. + + port@1: + type: object + description: + DSI output port node, connected to a panel or a bridge input port" + +patternProperties: + "^(panel|panel-dsi)@[0-9]$": + type: object + description: + A node containing the panel or bridge description as documented in + Documentation/devicetree/bindings/display/mipi-dsi-bus.txt + properties: + port: + type: object + description: + Panel or bridge port node, connected to the DSI output port (port@1) + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - "#address-cells" + - "#size-cells" + - compatible + - reg + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + #include <dt-bindings/gpio/gpio.h> + dsi: dsi@5a000000 { + compatible = "st,stm32-dsi"; + reg = <0x5a000000 0x800>; + clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clock-names = "pclk", "ref", "px_clk"; + resets = <&rcc DSI_R>; + reset-names = "apb"; + phy-dsi-supply = <&reg18>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&ltdc_ep1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel-dsi@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply = <&v3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + +... + + diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt deleted file mode 100644 index 60c54da4e526..000000000000 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt +++ /dev/null @@ -1,144 +0,0 @@ -* STMicroelectronics STM32 lcd-tft display controller - -- ltdc: lcd-tft display controller host - Required properties: - - compatible: "st,stm32-ltdc" - - reg: Physical base address of the IP registers and length of memory mapped region. - - clocks: A list of phandle + clock-specifier pairs, one for each - entry in 'clock-names'. - - clock-names: A list of clock names. For ltdc it should contain: - - "lcd" for the clock feeding the output pixel clock & IP clock. - - resets: reset to be used by the device (defined by use of RCC macro). - Required nodes: - - Video port for DPI RGB output: ltdc has one video port with up to 2 - endpoints: - - for external dpi rgb panel or bridge, using gpios. - - for internal dpi input of the MIPI DSI host controller. - Note: These 2 endpoints cannot be activated simultaneously. - -* STMicroelectronics STM32 DSI controller specific extensions to Synopsys - DesignWare MIPI DSI host controller - -The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI -DSI host controller. For all mandatory properties & nodes, please refer -to the related documentation in [5]. - -Mandatory properties specific to STM32 DSI: -- #address-cells: Should be <1>. -- #size-cells: Should be <0>. -- compatible: "st,stm32-dsi". -- clock-names: - - phy pll reference clock string name, must be "ref". -- resets: see [5]. -- reset-names: see [5]. - -Mandatory nodes specific to STM32 DSI: -- ports: A node containing DSI input & output port nodes with endpoint - definitions as documented in [3] & [4]. - - port@0: DSI input port node, connected to the ltdc rgb output port. - - port@1: DSI output port node, connected to a panel or a bridge input port. -- panel or bridge node: A node containing the panel or bridge description as - documented in [6]. - - port: panel or bridge port node, connected to the DSI output port (port@1). -Optional properties: -- phy-dsi-supply: phandle of the regulator that provides the supply voltage. - -Note: You can find more documentation in the following references -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/reset/reset.txt -[3] Documentation/devicetree/bindings/media/video-interfaces.txt -[4] Documentation/devicetree/bindings/graph.txt -[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt -[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt - -Example 1: RGB panel -/ { - ... - soc { - ... - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F4_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - - port { - ltdc_out_rgb: endpoint { - }; - }; - }; - }; -}; - -Example 2: DSI panel - -/ { - ... - soc { - ... - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F4_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - - port { - ltdc_out_dsi: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; - }; - - - dsi: dsi@40016c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-dsi"; - reg = <0x40016c00 0x800>; - clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; - clock-names = "pclk", "ref"; - resets = <&rcc STM32F4_APB2_RESET(DSI)>; - reset-names = "apb"; - phy-dsi-supply = <&reg18>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <&ltdc_out_dsi>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&dsi_in_panel>; - }; - }; - - }; - - panel-dsi@0 { - reg = <0>; /* dsi virtual channel (0..3) */ - compatible = ...; - enable-gpios = ...; - - port { - dsi_in_panel: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - - }; - - }; - - }; -}; diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml new file mode 100644 index 000000000000..a40197ab281e --- /dev/null +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 lcd-tft display controller + +maintainers: + - Philippe Cornu <philippe.cornu(a)st.com> + - Yannick Fertre <yannick.fertre(a)st.com> + +properties: + compatible: + const: st,stm32-ltdc + + reg: + maxItems: 1 + + interrupts: + items: + - description: events interrupt line. + - description: errors interrupt line. + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: lcd + + resets: + maxItems: 1 + + port: + type: object + description: + "Video port for DPI RGB output. + ltdc has one video port with up to 2 endpoints: + - for external dpi rgb panel or bridge, using gpios. + - for internal dpi input of the MIPI DSI host controller. + Note: These 2 endpoints cannot be activated simultaneously. + Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt." + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x5a001000 0x400>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LTDC_PX>; + clock-names = "lcd"; + resets = <&rcc LTDC_R>; + + port { + ltdc_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + +... + -- 2.15.0

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[PATCH] drm/msm/a5xx: Fix barrier usage in set_preempt_state()
by Davidlohr Bueso 15 Oct '19

15 Oct '19

Because it is not a Rmw operation, atomic_set() is never serialized, and therefore the 'upgradable' smp_mb__{before,after}_atomic() calls that order the write to preempt_state are completely bogus. This patch replaces these with smp_mb(), which seems like the original intent of when the code was written. Signed-off-by: Davidlohr Bueso <dbueso(a)suse.de> --- drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c index 9cf9353a7ff1..d27d8d3208c6 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c @@ -30,10 +30,10 @@ static inline void set_preempt_state(struct a5xx_gpu *gpu, * preemption or in the interrupt handler so barriers are needed * before... */ - smp_mb__before_atomic(); + smp_mb(); atomic_set(&gpu->preempt_state, new); /* ... and after*/ - smp_mb__after_atomic(); + smp_mb(); } /* Write the most recent wptr for the given ring into the hardware */ -- 2.16.4

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[PATCH] drm/amdgpu/display: hook renoir dc to pplib funcs
by Hersen Wu 15 Oct '19

15 Oct '19

enable dc get dmp clock table and set dcn watermarks via pplib. Signed-off-by: Hersen Wu <hersenxs.wu(a)amd.com> --- .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 93 +++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 2 +- 2 files changed, 94 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c index 95564b8de3ce..7add40dea9b7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c @@ -891,6 +891,90 @@ enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp, return PP_SMU_RESULT_FAIL; } +#ifdef CONFIG_DRM_AMD_DC_DCN2_1 +enum pp_smu_status pp_rn_get_dpm_clock_table( + struct pp_smu *pp, struct dpm_clocks *clock_table) +{ + const struct dc_context *ctx = pp->dm; + struct amdgpu_device *adev = ctx->driver_context; + struct smu_context *smu = &adev->smu; + + if (!smu->ppt_funcs) + return PP_SMU_RESULT_UNSUPPORTED; + + if (!smu->ppt_funcs->get_dpm_clock_table) + return PP_SMU_RESULT_UNSUPPORTED; + + if (!smu->ppt_funcs->get_dpm_clock_table(smu, clock_table)) + return PP_SMU_RESULT_OK; + + return PP_SMU_RESULT_FAIL; +} + +enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp, + struct pp_smu_wm_range_sets *ranges) +{ + const struct dc_context *ctx = pp->dm; + struct amdgpu_device *adev = ctx->driver_context; + struct smu_context *smu = &adev->smu; + struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges; + struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = + wm_with_clock_ranges.wm_dmif_clocks_ranges; + struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks = + wm_with_clock_ranges.wm_mcif_clocks_ranges; + int32_t i; + + if (!smu->funcs) + return PP_SMU_RESULT_UNSUPPORTED; + + wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets; + wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets; + + for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) { + if (ranges->reader_wm_sets[i].wm_inst > 3) + wm_dce_clocks[i].wm_set_id = WM_SET_A; + else + wm_dce_clocks[i].wm_set_id = + ranges->reader_wm_sets[i].wm_inst; + + wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz = + ranges->reader_wm_sets[i].min_drain_clk_mhz; + + wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz = + ranges->reader_wm_sets[i].max_drain_clk_mhz; + + wm_dce_clocks[i].wm_min_mem_clk_in_khz = + ranges->reader_wm_sets[i].min_fill_clk_mhz; + + wm_dce_clocks[i].wm_max_mem_clk_in_khz = + ranges->reader_wm_sets[i].max_fill_clk_mhz; + } + + for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) { + if (ranges->writer_wm_sets[i].wm_inst > 3) + wm_soc_clocks[i].wm_set_id = WM_SET_A; + else + wm_soc_clocks[i].wm_set_id = + ranges->writer_wm_sets[i].wm_inst; + wm_soc_clocks[i].wm_min_socclk_clk_in_khz = + ranges->writer_wm_sets[i].min_fill_clk_mhz; + + wm_soc_clocks[i].wm_max_socclk_clk_in_khz = + ranges->writer_wm_sets[i].max_fill_clk_mhz; + + wm_soc_clocks[i].wm_min_mem_clk_in_khz = + ranges->writer_wm_sets[i].min_drain_clk_mhz; + + wm_soc_clocks[i].wm_max_mem_clk_in_khz = + ranges->writer_wm_sets[i].max_drain_clk_mhz; + } + + smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges); + + return PP_SMU_RESULT_OK; +} +#endif + void dm_pp_get_funcs( struct dc_context *ctx, struct pp_smu_funcs *funcs) @@ -935,6 +1019,15 @@ void dm_pp_get_funcs( funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support; break; #endif + +#ifdef CONFIG_DRM_AMD_DC_DCN2_1 + case DCN_VERSION_2_1: + funcs->ctx.ver = PP_SMU_VER_RN; + funcs->rn_funcs.pp_smu.dm = ctx; + funcs->rn_funcs.set_wm_ranges = pp_rn_set_wm_ranges; + funcs->rn_funcs.get_dpm_clock_table = pp_rn_get_dpm_clock_table; + break; +#endif default: DRM_ERROR("smu version is not supported !\n"); break; diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h index c03a441ee638..24d65dbbd749 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h @@ -252,7 +252,7 @@ struct pp_smu_funcs_nv { #if defined(CONFIG_DRM_AMD_DC_DCN2_1) #define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8 -#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 4 +#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8 #define PP_SMU_NUM_FCLK_DPM_LEVELS 4 #define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4 -- 2.17.1

2 1

[Bug 112007] Broken powerplay table for Navi10 RX 5700XT.
by bugzilla-daemon＠freedesktop.org 15 Oct '19

15 Oct '19

1 0

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dri-devel October 2019