dri-devel December 2020

dri-devel@lists.freedesktop.org

278 participants
659 discussions

[PATCH 0/2] drm/cma-helper: Move mmap to object functions
by Thomas Zimmermann 15 Jan '21

15 Jan '21

This patchset moves CMA's mmap into a GEM object function. This change allows for removing CMA's mmap and gem_prime_mmap callbacks in favor of the default implementation. Tested with vc4 on RPi3. Thomas Zimmermann (2): drm/cma-helper: Remove prime infix from GEM object functions drm/cma-helper: Implement mmap as GEM CMA object functions drivers/gpu/drm/drm_file.c | 3 +- drivers/gpu/drm/drm_gem_cma_helper.c | 141 +++++++++------------------ drivers/gpu/drm/pl111/pl111_drv.c | 2 +- drivers/gpu/drm/vc4/vc4_bo.c | 6 +- include/drm/drm_gem_cma_helper.h | 14 +-- 5 files changed, 58 insertions(+), 108 deletions(-) -- 2.29.2

4 11

[PATCH 1/2] drm/bridge/lontium-lt9611uxc: fix waiting for EDID to become available
by Dmitry Baryshkov 15 Jan '21

15 Jan '21

- Call wake_up() when EDID ready event is received to wake wait_event_interruptible_timeout() - Increase waiting timeout, reading EDID can take longer than 100ms, so let's be on a safe side. - Return NULL pointer from get_edid() callback rather than ERR_PTR() pointer, as DRM code does NULL checks rather than IS_ERR(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov(a)linaro.org> --- drivers/gpu/drm/bridge/lontium-lt9611uxc.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c index 0c98d27f84ac..b708700e182d 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c @@ -145,8 +145,10 @@ static irqreturn_t lt9611uxc_irq_thread_handler(int irq, void *dev_id) lt9611uxc_unlock(lt9611uxc); - if (irq_status & BIT(0)) + if (irq_status & BIT(0)) { lt9611uxc->edid_read = !!(hpd_status & BIT(0)); + wake_up_all(&lt9611uxc->wq); + } if (irq_status & BIT(1)) { if (lt9611uxc->connector.dev) @@ -465,7 +467,7 @@ static enum drm_connector_status lt9611uxc_bridge_detect(struct drm_bridge *brid static int lt9611uxc_wait_for_edid(struct lt9611uxc *lt9611uxc) { return wait_event_interruptible_timeout(lt9611uxc->wq, lt9611uxc->edid_read, - msecs_to_jiffies(100)); + msecs_to_jiffies(500)); } static int lt9611uxc_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) @@ -503,7 +505,10 @@ static struct edid *lt9611uxc_bridge_get_edid(struct drm_bridge *bridge, ret = lt9611uxc_wait_for_edid(lt9611uxc); if (ret < 0) { dev_err(lt9611uxc->dev, "wait for EDID failed: %d\n", ret); - return ERR_PTR(ret); + return NULL; + } else if (ret == 0) { + dev_err(lt9611uxc->dev, "wait for EDID timeout\n"); + return NULL; } return drm_do_get_edid(connector, lt9611uxc_get_edid_block, lt9611uxc); -- 2.29.2

3 5

[PATCH RESEND v2] drm/bridge/tc358775: Fixes bus formats read
by Vinay Simha BN 14 Jan '21

14 Jan '21

- atomic_check removed - video data input and output formats added - bus formats read from drm_bridge_state.output_bus_cfg.format and .atomic_get_input_bus_fmts() instead of connector Signed-off-by: Vinay Simha BN <simhavcs(a)gmail.com> --- v1: * Laurent Pinchart review comments incorporated drm_bridge_state.output_bus_cfg.format instead of connector v2: * Laurent Pinchart review comments incorporated atomic_check removed video data input and output formats added --- drivers/gpu/drm/bridge/tc358775.c | 75 ++++++++++++++++++++++++++++++--------- 1 file changed, 58 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c index 2272adc..cc27570 100644 --- a/drivers/gpu/drm/bridge/tc358775.c +++ b/drivers/gpu/drm/bridge/tc358775.c @@ -271,6 +271,20 @@ struct tc_data { struct gpio_desc *stby_gpio; u8 lvds_link; /* single-link or dual-link */ u8 bpc; + u32 output_bus_fmt; +}; + +static const u32 tc_lvds_in_bus_fmts[] = { + MEDIA_BUS_FMT_RGB565_1X16, + MEDIA_BUS_FMT_RGB666_1X18, + MEDIA_BUS_FMT_RGB666_1X24_CPADHI, + MEDIA_BUS_FMT_RBG888_1X24, +}; + +static const u32 tc_lvds_out_bus_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, + MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, }; static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) @@ -359,19 +373,6 @@ static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val) ret, addr); } -/* helper function to access bus_formats */ -static struct drm_connector *get_connector(struct drm_encoder *encoder) -{ - struct drm_device *dev = encoder->dev; - struct drm_connector *connector; - - list_for_each_entry(connector, &dev->mode_config.connector_list, head) - if (connector->encoder == encoder) - return connector; - - return NULL; -} - static void tc_bridge_enable(struct drm_bridge *bridge) { struct tc_data *tc = bridge_to_tc(bridge); @@ -380,7 +381,10 @@ static void tc_bridge_enable(struct drm_bridge *bridge) u32 val = 0; u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay; struct drm_display_mode *mode; - struct drm_connector *connector = get_connector(bridge->encoder); + struct drm_bridge_state *state = + drm_priv_to_bridge_state(bridge->base.state); + + tc->output_bus_fmt = state->output_bus_cfg.format; mode = &bridge->encoder->crtc->state->adjusted_mode; @@ -451,14 +455,13 @@ static void tc_bridge_enable(struct drm_bridge *bridge) d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6)); dev_dbg(tc->dev, "bus_formats %04x bpc %d\n", - connector->display_info.bus_formats[0], + tc->output_bus_fmt, tc->bpc); /* * Default hardware register settings of tc358775 configured * with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format */ - if (connector->display_info.bus_formats[0] == - MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) { + if (tc->output_bus_fmt == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) { /* VESA-24 */ d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0)); @@ -590,6 +593,40 @@ static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc) return 0; } +static u32 * +tc_bridge_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts = NULL; + u8 i; + + *num_input_fmts = 0; + + for (i = 0 ; i < ARRAY_SIZE(tc_lvds_out_bus_fmts) ; ++i) { + if (output_fmt == tc_lvds_out_bus_fmts[i]) + break; + } + + if (i == ARRAY_SIZE(tc_lvds_out_bus_fmts)) + return NULL; + + *num_input_fmts = ARRAY_SIZE(tc_lvds_in_bus_fmts); + + input_fmts = kcalloc(*num_input_fmts, ARRAY_SIZE(tc_lvds_in_bus_fmts), + GFP_KERNEL); + if (!input_fmts) + return NULL; + + for (i = 0; i < ARRAY_SIZE(tc_lvds_in_bus_fmts); ++i) + input_fmts[i] = tc_lvds_in_bus_fmts[i]; + + return input_fmts; +} + static int tc_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags) { @@ -639,6 +676,10 @@ static int tc_bridge_attach(struct drm_bridge *bridge, } static const struct drm_bridge_funcs tc_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_get_input_bus_fmts = tc_bridge_get_input_bus_fmts, .attach = tc_bridge_attach, .pre_enable = tc_bridge_pre_enable, .enable = tc_bridge_enable, -- 2.7.4

4 4

[PATCH] drm/mediatek: mtk_dpi: Create connector for bridges
by Hsin-Yi Wang 13 Jan '21

13 Jan '21

Similar to a9d9fea74be2 ("drm/mediatek: mtk_dsi: Create connector for bridges"): Use the drm_bridge_connector helper to create a connector for pipelines that use drm_bridge. This allows splitting connector operations across multiple bridges when necessary, instead of having the last bridge in the chain creating the connector and handling all connector operations internally. Signed-off-by: Hsin-Yi Wang <hsinyi(a)chromium.org> --- drivers/gpu/drm/mediatek/mtk_dpi.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 52f11a63a330..189377e342fa 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -20,6 +20,7 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_bridge.h> +#include <drm/drm_bridge_connector.h> #include <drm/drm_crtc.h> #include <drm/drm_of.h> #include <drm/drm_simple_kms_helper.h> @@ -66,6 +67,7 @@ struct mtk_dpi { struct drm_encoder encoder; struct drm_bridge bridge; struct drm_bridge *next_bridge; + struct drm_connector *connector; void __iomem *regs; struct device *dev; struct clk *engine_clk; @@ -603,12 +605,21 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->ddp_comp); - ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, 0); + ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret) { dev_err(dev, "Failed to attach bridge: %d\n", ret); goto err_cleanup; } + dpi->connector = drm_bridge_connector_init(drm_dev, &dpi->encoder); + if (IS_ERR(dpi->connector)) { + dev_err(dev, "Unable to create bridge connector\n"); + ret = PTR_ERR(dpi->connector); + goto err_cleanup; + } + drm_connector_attach_encoder(dpi->connector, &dpi->encoder); + dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; -- 2.29.2.576.ga3fc446d84-goog

2 2

[PATCH v3 00/12] RFC Support hot device unplug in amdgpu
by Andrey Grodzovsky 13 Jan '21

13 Jan '21

Until now extracting a card either by physical extraction (e.g. eGPU with thunderbolt connection or by emulation through syfs -> /sys/bus/pci/devices/device_id/remove) would cause random crashes in user apps. The random crashes in apps were mostly due to the app having mapped a device backed BO into its address space was still trying to access the BO while the backing device was gone. To answer this first problem Christian suggested to fix the handling of mapped memory in the clients when the device goes away by forcibly unmap all buffers the user processes has by clearing their respective VMAs mapping the device BOs. Then when the VMAs try to fill in the page tables again we check in the fault handlerif the device is removed and if so, return an error. This will generate a SIGBUS to the application which can then cleanly terminate.This indeed was done but this in turn created a problem of kernel OOPs were the OOPSes were due to the fact that while the app was terminating because of the SIGBUSit would trigger use after free in the driver by calling to accesses device structures that were already released from the pci remove sequence.This was handled by introducing a 'flush' sequence during device removal were we wait for drm file reference to drop to 0 meaning all user clients directly using this device terminated. v2: Based on discussions in the mailing list with Daniel and Pekka [1] and based on the document produced by Pekka from those discussions [2] the whole approach with returning SIGBUS and waiting for all user clients having CPU mapping of device BOs to die was dropped. Instead as per the document suggestion the device structures are kept alive until the last reference to the device is dropped by user client and in the meanwhile all existing and new CPU mappings of the BOs belonging to the device directly or by dma-buf import are rerouted to per user process dummy rw page.Also, I skipped the 'Requirements for KMS UAPI' section of [2] since i am trying to get the minimal set of requirements that still give useful solution to work and this is the'Requirements for Render and Cross-Device UAPI' section and so my test case is removing a secondary device, which is render only and is not involved in KMS. v3: More updates following comments from v2 such as removing loop to find DRM file when rerouting page faults to dummy page,getting rid of unnecessary sysfs handling refactoring and moving prevention of GPU recovery post device unplug from amdgpu to scheduler layer. On top of that added unplug support for the IOMMU enabled system. With these patches I am able to gracefully remove the secondary card using sysfs remove hook while glxgears is running off of secondary card (DRI_PRIME=1) without kernel oopses or hangs and keep working with the primary card or soft reset the device without hangs or oopses TODOs for followup work: Convert AMDGPU code to use devm (for hw stuff) and drmm (for sw stuff and allocations) (Daniel) Rework AMDGPU sysfs handling using default groups attributes (Greg) Support plugging the secondary device back after unplug - currently still experiencing HW error on plugging back. Add support for 'Requirements for KMS UAPI' section of [2] - unplugging primary, display connected card. [1] - Discussions during v2 of the patchset https://lists.freedesktop.org/archives/amd-gfx/2020-June/050806.html [2] - drm/doc: device hot-unplug for userspace https://www.spinics.net/lists/dri-devel/msg259755.html [3] - Related gitlab ticket https://gitlab.freedesktop.org/drm/amd/-/issues/1081 Andrey Grodzovsky (12): drm: Add dummy page per device or GEM object drm: Unamp the entire device address space on device unplug drm/ttm: Remap all page faults to per process dummy page. drm/ttm: Set dma addr to null after freee drm/ttm: Expose ttm_tt_unpopulate for driver use drm/sched: Cancel and flush all oustatdning jobs before finish. drm/sched: Prevent any job recoveries after device is unplugged. drm/amdgpu: Split amdgpu_device_fini into early and late drm/amdgpu: Add early fini callback drm/amdgpu: Avoid sysfs dirs removal post device unplug drm/amdgpu: Register IOMMU topology notifier per device. drm/amdgpu: Fix a bunch of sdma code crash post device unplug drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 82 +++++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 17 ++++- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 24 ++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++- drivers/gpu/drm/amd/include/amd_shared.h | 2 + drivers/gpu/drm/drm_drv.c | 3 + drivers/gpu/drm/drm_file.c | 8 +++ drivers/gpu/drm/drm_prime.c | 10 +++ drivers/gpu/drm/etnaviv/etnaviv_sched.c | 3 +- drivers/gpu/drm/lima/lima_sched.c | 3 +- drivers/gpu/drm/panfrost/panfrost_job.c | 2 +- drivers/gpu/drm/scheduler/sched_main.c | 18 ++++- drivers/gpu/drm/ttm/ttm_bo_vm.c | 54 ++++++++++++--- drivers/gpu/drm/ttm/ttm_page_alloc.c | 2 + drivers/gpu/drm/ttm/ttm_tt.c | 1 + drivers/gpu/drm/v3d/v3d_sched.c | 15 +++-- include/drm/drm_file.h | 2 + include/drm/drm_gem.h | 2 + include/drm/gpu_scheduler.h | 6 +- 31 files changed, 287 insertions(+), 47 deletions(-) -- 2.7.4

9 106

[PATCH v5 01/11] dt-bindings: usb: convert usb-device.txt to YAML schema
by Chunfeng Yun 13 Jan '21

13 Jan '21

Convert usb-device.txt to YAML schema usb-device.yaml Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> --- v5: changes suggested by Rob: 1. limit the pattern length 2. remove properties description for hard wired USB devices in usb-hcd.yaml depends on series: https://patchwork.kernel.org/project/linux-usb/list/?series=399561 [v6,00/19] dt-bindings: usb: Add generic USB HCD, xHCI, DWC USB3 DT schema v4: no changes, update dependent series: https://patchwork.kernel.org/project/linux-usb/list/?series=399561 [v6,00/19] dt-bindings: usb: Add generic USB HCD, xHCI, DWC USB3 DT schema v3: 1. remove $nodenmae and items key word for compatilbe; 2. add additionalProperties; The followings are suggested by Rob: 3. merge the following patch [v2,1/4] dt-bindings: usb: convert usb-device.txt to YAML schema [v2,2/4] dt-bindings: usb: add properties for hard wired devices 4. define the unit-address for hard-wired device in usb-hcd.yaml, also define its 'reg' and 'compatible'; 5. This series is base on Serge's series: https://patchwork.kernel.org/project/linux-usb/cover/20201111090853.14112-1… [v4,00/18] dt-bindings: usb: Add generic USB HCD, xHCI, DWC USB3 DT schema v2 changes suggested by Rob: 1. modify pattern to support any USB class 2. convert usb-device.txt into usb-device.yaml --- .../devicetree/bindings/usb/usb-device.txt | 102 -------------- .../devicetree/bindings/usb/usb-device.yaml | 124 ++++++++++++++++++ .../devicetree/bindings/usb/usb-hcd.yaml | 19 +++ 3 files changed, 143 insertions(+), 102 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/usb-device.txt create mode 100644 Documentation/devicetree/bindings/usb/usb-device.yaml diff --git a/Documentation/devicetree/bindings/usb/usb-device.txt b/Documentation/devicetree/bindings/usb/usb-device.txt deleted file mode 100644 index 036be172b1ae..000000000000 --- a/Documentation/devicetree/bindings/usb/usb-device.txt +++ /dev/null @@ -1,102 +0,0 @@ -Generic USB Device Properties - -Usually, we only use device tree for hard wired USB device. -The reference binding doc is from: -http://www.devicetree.org/open-firmware/bindings/usb/usb-1_0.ps - -Four types of device-tree nodes are defined: "host-controller nodes" -representing USB host controllers, "device nodes" representing USB devices, -"interface nodes" representing USB interfaces and "combined nodes" -representing simple USB devices. - -A combined node shall be used instead of a device node and an interface node -for devices of class 0 or 9 (hub) with a single configuration and a single -interface. - -A "hub node" is a combined node or an interface node that represents a USB -hub. - - -Required properties for device nodes: -- compatible: "usbVID,PID", where VID is the vendor id and PID the product id. - The textual representation of VID and PID shall be in lower case hexadecimal - with leading zeroes suppressed. The other compatible strings from the above - standard binding could also be used, but a device adhering to this binding - may leave out all except for "usbVID,PID". -- reg: the number of the USB hub port or the USB host-controller port to which - this device is attached. The range is 1-255. - - -Required properties for device nodes with interface nodes: -- #address-cells: shall be 2 -- #size-cells: shall be 0 - - -Required properties for interface nodes: -- compatible: "usbifVID,PID.configCN.IN", where VID is the vendor id, PID is - the product id, CN is the configuration value and IN is the interface - number. The textual representation of VID, PID, CN and IN shall be in lower - case hexadecimal with leading zeroes suppressed. The other compatible - strings from the above standard binding could also be used, but a device - adhering to this binding may leave out all except for - "usbifVID,PID.configCN.IN". -- reg: the interface number and configuration value - -The configuration component is not included in the textual representation of -an interface-node unit address for configuration 1. - - -Required properties for combined nodes: -- compatible: "usbVID,PID", where VID is the vendor id and PID the product id. - The textual representation of VID and PID shall be in lower case hexadecimal - with leading zeroes suppressed. The other compatible strings from the above - standard binding could also be used, but a device adhering to this binding - may leave out all except for "usbVID,PID". -- reg: the number of the USB hub port or the USB host-controller port to which - this device is attached. The range is 1-255. - - -Required properties for hub nodes with device nodes: -- #address-cells: shall be 1 -- #size-cells: shall be 0 - - -Required properties for host-controller nodes with device nodes: -- #address-cells: shall be 1 -- #size-cells: shall be 0 - - -Example: - -&usb1 { /* host controller */ - #address-cells = <1>; - #size-cells = <0>; - - hub@1 { /* hub connected to port 1 */ - compatible = "usb5e3,608"; - reg = <1>; - }; - - device@2 { /* device connected to port 2 */ - compatible = "usb123,4567"; - reg = <2>; - }; - - device@3 { /* device connected to port 3 */ - compatible = "usb123,abcd"; - reg = <3>; - - #address-cells = <2>; - #size-cells = <0>; - - interface@0 { /* interface 0 of configuration 1 */ - compatible = "usbif123,abcd.config1.0"; - reg = <0 1>; - }; - - interface@0,2 { /* interface 0 of configuration 2 */ - compatible = "usbif123,abcd.config2.0"; - reg = <0 2>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/usb-device.yaml b/Documentation/devicetree/bindings/usb/usb-device.yaml new file mode 100644 index 000000000000..7bb25a45427d --- /dev/null +++ b/Documentation/devicetree/bindings/usb/usb-device.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/usb-device.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The device tree bindings for the Generic USB Device + +maintainers: + - Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> + +description: | + Usually, we only use device tree for hard wired USB device. + The reference binding doc is from: + http://www.devicetree.org/open-firmware/bindings/usb/usb-1_0.ps + + Four types of device-tree nodes are defined: "host-controller nodes" + representing USB host controllers, "device nodes" representing USB devices, + "interface nodes" representing USB interfaces and "combined nodes" + representing simple USB devices. + + A combined node shall be used instead of a device node and an interface node + for devices of class 0 or 9 (hub) with a single configuration and a single + interface. + + A "hub node" is a combined node or an interface node that represents a USB + hub. + +properties: + compatible: + pattern: "^usb[0-9a-f]{1,4},[0-9a-f]{1,4}$" + description: Device nodes or combined nodes. + "usbVID,PID", where VID is the vendor id and PID the product id. + The textual representation of VID and PID shall be in lower case + hexadecimal with leading zeroes suppressed. The other compatible + strings from the above standard binding could also be used, + but a device adhering to this binding may leave out all except + for "usbVID,PID". + + reg: + description: the number of the USB hub port or the USB host-controller + port to which this device is attached. The range is 1-255. + maxItems: 1 + + "#address-cells": + description: should be 1 for hub nodes with device nodes, + should be 2 for device nodes with interface nodes. + enum: [1, 2] + + "#size-cells": + const: 0 + +patternProperties: + "^interface@[0-9a-f]{1,2}(,[0-9a-f]{1,2})$": + type: object + description: USB interface nodes. + The configuration component is not included in the textual + representation of an interface-node unit address for configuration 1. + + properties: + compatible: + pattern: "^usbif[0-9a-f]{1,4},[0-9a-f]{1,4}.config[0-9a-f]{1,2}.[0-9a-f]{1,2}$" + description: Interface nodes. + "usbifVID,PID.configCN.IN", where VID is the vendor id, PID is + the product id, CN is the configuration value and IN is the interface + number. The textual representation of VID, PID, CN and IN shall be + in lower case hexadecimal with leading zeroes suppressed. + The other compatible strings from the above standard binding could + also be used, but a device adhering to this binding may leave out + all except for "usbifVID,PID.configCN.IN". + + reg: + description: should be 2 cells long, the first cell represents + the interface number and the second cell represents the + configuration value. + maxItems: 1 + +required: + - compatile + - reg + +additionalProperties: true + +examples: + #hub connected to port 1 + #device connected to port 2 + #device connected to port 3 + # interface 0 of configuration 1 + # interface 0 of configuration 2 + - | + usb@11270000 { + reg = <0x11270000 0x1000>; + interrupts = <0x0 0x4e 0x0>; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb5e3,608"; + reg = <1>; + }; + + device@2 { + compatible = "usb123,4567"; + reg = <2>; + }; + + device@3 { + compatible = "usb123,abcd"; + reg = <3>; + + #address-cells = <2>; + #size-cells = <0>; + + interface@0 { + compatible = "usbif123,abcd.config1.0"; + reg = <0 1>; + }; + + interface@0,2 { + compatible = "usbif123,abcd.config2.0"; + reg = <0 2>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/usb-hcd.yaml b/Documentation/devicetree/bindings/usb/usb-hcd.yaml index 9881ac10380d..56853c17af66 100644 --- a/Documentation/devicetree/bindings/usb/usb-hcd.yaml +++ b/Documentation/devicetree/bindings/usb/usb-hcd.yaml @@ -23,6 +23,18 @@ properties: targeted hosts (non-PC hosts). type: boolean + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^.*@[0-9a-f]{1,2}$": + description: The hard wired USB devices + type: object + $ref: /usb/usb-device.yaml + additionalProperties: true examples: @@ -30,4 +42,11 @@ examples: usb { phys = <&usb2_phy1>, <&usb3_phy1>; phy-names = "usb"; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + }; }; -- 2.18.0

3 18

[PATCH] drm/bridge: ti-sn65dsi86: rename GPIO register bits
by Shawn Guo 12 Jan '21

12 Jan '21

From: Shawn Guo <shawn.guo(a)linaro.org> It renames GPIO register bits to drop 'SN_' prefix, so that they are consistent to other definitions - prefixing register name with 'SN_' but not for bit fields. Signed-off-by: Shawn Guo <shawn.guo(a)linaro.org> --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index f27306c51e4d..8eac9d77eba1 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -63,13 +63,13 @@ #define SN_HPD_DISABLE_REG 0x5C #define HPD_DISABLE BIT(0) #define SN_GPIO_IO_REG 0x5E -#define SN_GPIO_INPUT_SHIFT 4 -#define SN_GPIO_OUTPUT_SHIFT 0 +#define GPIO_INPUT_SHIFT 4 +#define GPIO_OUTPUT_SHIFT 0 #define SN_GPIO_CTRL_REG 0x5F -#define SN_GPIO_MUX_INPUT 0 -#define SN_GPIO_MUX_OUTPUT 1 -#define SN_GPIO_MUX_SPECIAL 2 -#define SN_GPIO_MUX_MASK 0x3 +#define GPIO_MUX_INPUT 0 +#define GPIO_MUX_OUTPUT 1 +#define GPIO_MUX_SPECIAL 2 +#define GPIO_MUX_MASK 0x3 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) #define SN_AUX_ADDR_19_16_REG 0x74 #define SN_AUX_ADDR_15_8_REG 0x75 @@ -1035,7 +1035,7 @@ static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) if (ret) return ret; - return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); + return !!(val & BIT(GPIO_INPUT_SHIFT + offset)); } static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, @@ -1051,8 +1051,8 @@ static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, val &= 1; ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, - BIT(SN_GPIO_OUTPUT_SHIFT + offset), - val << (SN_GPIO_OUTPUT_SHIFT + offset)); + BIT(GPIO_OUTPUT_SHIFT + offset), + val << (GPIO_OUTPUT_SHIFT + offset)); if (ret) dev_warn(pdata->dev, "Failed to set bridge GPIO %u: %d\n", offset, ret); @@ -1069,8 +1069,8 @@ static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, return 0; ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, - SN_GPIO_MUX_MASK << shift, - SN_GPIO_MUX_INPUT << shift); + GPIO_MUX_MASK << shift, + GPIO_MUX_INPUT << shift); if (ret) { set_bit(offset, pdata->gchip_output); return ret; @@ -1103,8 +1103,8 @@ static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, /* Set direction */ ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, - SN_GPIO_MUX_MASK << shift, - SN_GPIO_MUX_OUTPUT << shift); + GPIO_MUX_MASK << shift, + GPIO_MUX_OUTPUT << shift); if (ret) { clear_bit(offset, pdata->gchip_output); pm_runtime_put(pdata->dev); -- 2.17.1

3 3

[RFC PATCH 000/162] DG1 + LMEM enabling
by Matthew Auld 12 Jan '21

12 Jan '21

This series includes a version of Maarten' series[1], which converts more of the driver locking over to dma-resv. On top of this we now implement things like LMEM eviction, which has a dependency on this new locking design. In terms of new uAPI we have gem_create_ext, which offers extensions support for gem_create. For now the only extension we add is giving userspace the ability to optionally provide a priority list of potential placements for the object. The other bit of new uAPI is the query interface for memory regions, which describes the supported memory regions for the device. What this reports can then be fed into gem_create_ext to specify where an object might reside, like device local memory. Note that the class/instance complexity in the uAPI is not very relevant for DG1, but is in preparation for the Xe HP multi-tile architecture with multiple memory regions. The series still includes relocation support, but that's purely for CI, until we have completed all the IGT rework[2] and so will not be merged. Likewise for pread/pwrite, which will also be dropped from DG1+. [1] https://patchwork.freedesktop.org/series/82337/ [2] https://patchwork.freedesktop.org/series/82954/ Abdiel Janulgue (3): drm/i915/query: Expose memory regions through the query uAPI drm/i915: Provide a way to disable PCIe relaxed write ordering drm/i915: Reintroduce mem->reserved Animesh Manna (2): drm/i915/lmem: reset the lmem buffer created by fbdev drm/i915/dsb: Enable lmem for dsb Anshuman Gupta (1): drm/i915/oprom: Basic sanitization Anusha Srivatsa (1): drm/i915/lmem: Bypass aperture when lmem is available Bommu Krishnaiah (1): drm/i915/gem: Update shmem available memory CQ Tang (13): drm/i915/dg1: Fix occasional migration error drm/i915: i915 returns -EBUSY on thread contention drm/i915: setup GPU device lmem region drm/i915: Fix object page offset within a region drm/i915: add i915_gem_object_is_devmem() function drm/i915: finish memory region support for stolen objects. drm/i915: Create stolen memory region from local memory drm/i915/dg1: intel_memory_region_evict() changes for eviction drm/i915/dg1: i915_gem_object_memcpy(..) infrastructure drm/i915/dg1: Eviction logic drm/i915/dg1: Add enable_eviction modparam drm/i915/dg1: Add lmem_size modparam drm/i915: need consider system BO snoop for dgfx Chris Wilson (2): drm/i915/gt: Move move context layout registers and offsets to lrc_reg.h drm/i915/gt: Rename lrc.c to execlists_submission.c Clint Taylor (3): drm/i915/dg1: Read OPROM via SPI controller drm/i915/dg1: Compute MEM Bandwidth using MCHBAR drm/i915/dg1: Double memory bandwidth available Daniele Ceraolo Spurio (5): drm/i915: split gen8+ flush and bb_start emission functions to their own file drm/i915: split wa_bb code to its own file drm/i915: Make intel_init_workaround_bb more compatible with ww locking. drm/i915/guc: put all guc objects in lmem when available drm/i915: WA for zero memory channel Imre Deak (1): drm/i915/dg1: Reserve first 1MB of local memory Kui Wen (1): drm/i915/dg1: Do not check r->sgt.pfn for NULL Lucas De Marchi (2): drm/i915: move eviction to prepare hook drm/i915/dg1: allow pci to auto probe Maarten Lankhorst (60): drm/i915: Pin timeline map after first timeline pin, v5. drm/i915: Move cmd parser pinning to execbuffer drm/i915: Add missing -EDEADLK handling to execbuf pinning, v2. drm/i915: Ensure we hold the object mutex in pin correctly v2 drm/i915: Add gem object locking to madvise. drm/i915: Move HAS_STRUCT_PAGE to obj->flags drm/i915: Rework struct phys attachment handling drm/i915: Convert i915_gem_object_attach_phys() to ww locking, v2. drm/i915: make lockdep slightly happier about execbuf. drm/i915: Disable userptr pread/pwrite support. drm/i915: No longer allow exporting userptr through dma-buf drm/i915: Reject more ioctls for userptr drm/i915: Reject UNSYNCHRONIZED for userptr, v2. drm/i915: Make compilation of userptr code depend on MMU_NOTIFIER. drm/i915: Fix userptr so we do not have to worry about obj->mm.lock, v5. drm/i915: Flatten obj->mm.lock drm/i915: Populate logical context during first pin. drm/i915: Make ring submission compatible with obj->mm.lock removal, v2. drm/i915: Handle ww locking in init_status_page drm/i915: Rework clflush to work correctly without obj->mm.lock. drm/i915: Pass ww ctx to intel_pin_to_display_plane drm/i915: Add object locking to vm_fault_cpu drm/i915: Move pinning to inside engine_wa_list_verify() drm/i915: Take reservation lock around i915_vma_pin. drm/i915: Make __engine_unpark() compatible with ww locking v2 drm/i915: Take obj lock around set_domain ioctl drm/i915: Defer pin calls in buffer pool until first use by caller. drm/i915: Fix pread/pwrite to work with new locking rules. drm/i915: Fix workarounds selftest, part 1 drm/i915: Add igt_spinner_pin() to allow for ww locking around spinner. drm/i915: Add ww locking around vm_access() drm/i915: Increase ww locking for perf. drm/i915: Lock ww in ucode objects correctly drm/i915: Add ww locking to dma-buf ops. drm/i915: Add missing ww lock in intel_dsb_prepare. drm/i915: Fix ww locking in shmem_create_from_object drm/i915: Use a single page table lock for each gtt. drm/i915/selftests: Prepare huge_pages testcases for obj->mm.lock removal. drm/i915/selftests: Prepare client blit for obj->mm.lock removal. drm/i915/selftests: Prepare coherency tests for obj->mm.lock removal. drm/i915/selftests: Prepare context tests for obj->mm.lock removal. drm/i915/selftests: Prepare dma-buf tests for obj->mm.lock removal. drm/i915/selftests: Prepare execbuf tests for obj->mm.lock removal. drm/i915/selftests: Prepare mman testcases for obj->mm.lock removal. drm/i915/selftests: Prepare object tests for obj->mm.lock removal. drm/i915/selftests: Prepare object blit tests for obj->mm.lock removal. drm/i915/selftests: Prepare igt_gem_utils for obj->mm.lock removal drm/i915/selftests: Prepare context selftest for obj->mm.lock removal drm/i915/selftests: Prepare hangcheck for obj->mm.lock removal drm/i915/selftests: Prepare execlists for obj->mm.lock removal drm/i915/selftests: Prepare mocs tests for obj->mm.lock removal drm/i915/selftests: Prepare ring submission for obj->mm.lock removal drm/i915/selftests: Prepare timeline tests for obj->mm.lock removal drm/i915/selftests: Prepare i915_request tests for obj->mm.lock removal drm/i915/selftests: Prepare memory region tests for obj->mm.lock removal drm/i915/selftests: Prepare cs engine tests for obj->mm.lock removal drm/i915/selftests: Prepare gtt tests for obj->mm.lock removal drm/i915: Finally remove obj->mm.lock. drm/i915: Keep userpointer bindings if seqcount is unchanged, v2. drm/i915: Implement eviction locking v2 Matt Roper (1): drm/i915/lmem: Fail driver init if LMEM training failed Matthew Auld (19): drm/i915/selftest: also consider non-contiguous objects drm/i915/selftest: assert we get 2M GTT pages drm/i915/selftest: handle local-memory in perf_memcpy HAX drm/i915/lmem: support CPU relocations HAX drm/i915/lmem: support pread and pwrite drm/i915: introduce kernel blitter_context drm/i915/region: support basic eviction drm/i915: support basic object migration drm/i915/uapi: introduce drm_i915_gem_create_ext drm/i915: setup the LMEM region drm/i915/gtt: map the PD up front drm/i915/gtt/dgfx: place the PD in LMEM drm/i915/gtt: make flushing conditional drm/i915/gtt/dg1: add PTE_LM plumbing for PPGTT drm/i915/gtt/dg1: add PTE_LM plumbing for GGTT drm/i915: allocate context from LMEM drm/i915: move engine scratch to LMEM drm/i915/lmem: support optional CPU clearing for special internal use drm/i915: drop fake lmem Michael J. Ruhl (2): drm/i915/dmabuf: Disallow LMEM objects from dma-buf drm/i915/dg1: Introduce dmabuf mmap to LMEM Michel Thierry (2): drm/i915/lmem: allocate cmd ring in lmem drm/i915/lmem: allocate HWSP in lmem Mohammed Khajapasha (2): drm/i915/fbdev: Use lmem physical addresses for fb_mmap() on discrete drm/i915: Return error value when bo not in LMEM for discrete Prathap Kumar Valsan (2): drm/i915: Store gt in memory region drm/i915/pm: suspend and restore ppgtt mapping Ramalingam C (6): drm/i915: define intel_partial_pages_for_sg_table drm/i915: create and destroy dummy vma drm/i915: blt copy between objs using pre-created vma windows drm/i915: window_blt_copy is used for swapin and swapout drm/i915: Lmem eviction statistics by category drm/i915/gem/selftest: test and measure window based blt cpy Stuart Summers (1): drm/i915: Allow non-uniform subslices in gen12+ Sudeep Dutt (2): drm/i915/dg1: Track swap in/out stats via debugfs drm/i915/dg1: Measure swap in/out timing stats Thomas Hellström (15): HAX drm/i915: Work around the selftest timeline lock splat workaround drm/i915: Introduce drm_i915_lock_isolated drm/i915: Lock hwsp objects isolated for pinning at create time drm/i915: Prepare for obj->mm.lock removal drm/i915: Avoid some false positives in assert_object_held() drm/i915: Reference contending lock objects drm/i915: Break out dma_resv ww locking utilities to separate files drm/i915: Introduce a for_i915_gem_ww(){} drm/i915: Untangle the vma pages_mutex drm/i915: Add blit functions that can be called from within a WW transaction drm/i915: Delay publishing objects on the eviction lists drm/i915: Perform execbuffer object locking as a separate step drm/i915: Support ww eviction drm/i915: Use a ww transaction in the fault handler drm/i915: Use a ww transaction in i915_gem_object_pin_map_unlocked() Tvrtko Ursulin (4): drm/i915/dg1: Eliminate eviction mutex drm/i915/dg1: Keep engine awake across whole blit drm/i915/dg1: Add dedicated context for blitter eviction drm/i915: Improve accuracy of eviction stats Venkata Ramana Nayana (8): drm/i915: suspend/resume eviction drm/i915: Reset blitter context when unpark engine drm/i915/gt: Allocate default ctx objects in SMEM drm/i915: suspend/resume enable blitter eviction drm/i915: suspend/resume handling of perma-pinned objects drm/i915: Support ww locks in suspend/resume drm/i915/dg1: Fix mapping type for default state object drm/i915/dg1: Fix GPU hang due to shmemfs page drop Venkata Sandeep Dhanalakota (2): drm/i915: Update the helper to set correct mapping drm/i915/lmem: Limit block size to 4G Zbigniew Kempczyński (1): drm/i915: Distinction of memory regions drivers/gpu/drm/i915/Kconfig.debug | 11 + drivers/gpu/drm/i915/Makefile | 7 +- drivers/gpu/drm/i915/display/intel_bios.c | 75 +- drivers/gpu/drm/i915/display/intel_bw.c | 64 +- drivers/gpu/drm/i915/display/intel_display.c | 80 +- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/display/intel_dsb.c | 9 +- drivers/gpu/drm/i915/display/intel_fbc.c | 20 +- drivers/gpu/drm/i915/display/intel_fbdev.c | 54 +- drivers/gpu/drm/i915/display/intel_opregion.c | 169 ++++ drivers/gpu/drm/i915/display/intel_opregion.h | 31 +- drivers/gpu/drm/i915/display/intel_overlay.c | 34 +- drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 15 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_create.c | 398 ++++++++ drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 123 ++- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 52 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 302 +++++- drivers/gpu/drm/i915/gem/i915_gem_fence.c | 95 -- drivers/gpu/drm/i915/gem/i915_gem_internal.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 254 ++++- drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 22 + drivers/gpu/drm/i915/gem/i915_gem_mman.c | 187 ++-- drivers/gpu/drm/i915/gem/i915_gem_mman.h | 11 + drivers/gpu/drm/i915/gem/i915_gem_object.c | 711 +++++++++++++- drivers/gpu/drm/i915/gem/i915_gem_object.h | 206 +++- .../gpu/drm/i915/gem/i915_gem_object_blt.c | 101 +- .../gpu/drm/i915/gem/i915_gem_object_blt.h | 10 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 46 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 140 ++- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 110 +-- drivers/gpu/drm/i915/gem/i915_gem_region.c | 234 ++++- drivers/gpu/drm/i915/gem/i915_gem_region.h | 3 +- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 46 +- drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 52 +- drivers/gpu/drm/i915/gem/i915_gem_shrinker.h | 6 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 247 +++-- drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 10 +- drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 - drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 870 ++++++----------- .../drm/i915/gem/selftests/huge_gem_object.c | 4 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 60 +- .../i915/gem/selftests/i915_gem_client_blt.c | 8 +- .../i915/gem/selftests/i915_gem_coherency.c | 18 +- .../drm/i915/gem/selftests/i915_gem_context.c | 21 +- .../drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +- .../i915/gem/selftests/i915_gem_execbuffer.c | 2 +- .../drm/i915/gem/selftests/i915_gem_mman.c | 33 +- .../drm/i915/gem/selftests/i915_gem_object.c | 2 +- .../i915/gem/selftests/i915_gem_object_blt.c | 172 +++- .../drm/i915/gem/selftests/i915_gem_phys.c | 10 +- .../drm/i915/gem/selftests/igt_gem_utils.c | 2 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 11 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 393 ++++++++ drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 26 + drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 91 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 2 + drivers/gpu/drm/i915/gt/intel_context.c | 3 +- drivers/gpu/drm/i915/gt/intel_context.h | 2 + drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 13 +- drivers/gpu/drm/i915/gt/intel_engine.h | 4 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 125 ++- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 14 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 + .../drm/i915/gt/intel_engine_workaround_bb.c | 364 +++++++ .../drm/i915/gt/intel_engine_workaround_bb.h | 14 + ...tel_lrc.c => intel_execlists_submission.c} | 899 +++--------------- .../drm/i915/gt/intel_execlists_submission.h | 66 ++ drivers/gpu/drm/i915/gt/intel_ggtt.c | 93 +- drivers/gpu/drm/i915/gt/intel_gt.c | 14 +- .../gpu/drm/i915/gt/intel_gt_buffer_pool.c | 47 +- .../gpu/drm/i915/gt/intel_gt_buffer_pool.h | 5 + .../drm/i915/gt/intel_gt_buffer_pool_types.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 1 + drivers/gpu/drm/i915/gt/intel_gtt.c | 105 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 23 +- drivers/gpu/drm/i915/gt/intel_lrc.h | 128 --- drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 39 + drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 20 +- drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 + drivers/gpu/drm/i915/gt/intel_ring.c | 24 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 184 ++-- drivers/gpu/drm/i915/gt/intel_sseu.c | 6 +- drivers/gpu/drm/i915/gt/intel_timeline.c | 121 ++- drivers/gpu/drm/i915/gt/intel_timeline.h | 1 + .../gpu/drm/i915/gt/intel_timeline_types.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +- drivers/gpu/drm/i915/gt/mock_engine.c | 24 +- drivers/gpu/drm/i915/gt/selftest_context.c | 5 +- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 4 +- .../{selftest_lrc.c => selftest_execlists.c} | 37 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +- drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 5 +- .../drm/i915/gt/selftest_ring_submission.c | 4 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 100 +- .../gpu/drm/i915/gt/selftest_workarounds.c | 101 +- drivers/gpu/drm/i915/gt/shmem_utils.c | 11 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 13 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 11 +- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 4 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.c | 18 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 37 +- drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +- drivers/gpu/drm/i915/gvt/mmio_context.h | 2 + drivers/gpu/drm/i915/gvt/scheduler.c | 1 + drivers/gpu/drm/i915/i915_active.c | 20 +- drivers/gpu/drm/i915/i915_cmd_parser.c | 104 +- drivers/gpu/drm/i915/i915_debugfs.c | 42 +- drivers/gpu/drm/i915/i915_drv.c | 277 +++++- drivers/gpu/drm/i915/i915_drv.h | 57 +- drivers/gpu/drm/i915/i915_gem.c | 418 +++----- drivers/gpu/drm/i915/i915_gem.h | 12 - drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- drivers/gpu/drm/i915/i915_gem_ww.c | 93 ++ drivers/gpu/drm/i915/i915_gem_ww.h | 53 ++ drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- drivers/gpu/drm/i915/i915_memcpy.c | 2 +- drivers/gpu/drm/i915/i915_memcpy.h | 2 +- drivers/gpu/drm/i915/i915_mm.c | 2 +- drivers/gpu/drm/i915/i915_params.c | 11 +- drivers/gpu/drm/i915/i915_params.h | 3 +- drivers/gpu/drm/i915/i915_pci.c | 5 +- drivers/gpu/drm/i915/i915_perf.c | 57 +- drivers/gpu/drm/i915/i915_query.c | 62 ++ drivers/gpu/drm/i915/i915_reg.h | 17 + drivers/gpu/drm/i915/i915_selftest.h | 2 + drivers/gpu/drm/i915/i915_vma.c | 154 ++- drivers/gpu/drm/i915/i915_vma.h | 28 +- drivers/gpu/drm/i915/intel_memory_region.c | 229 ++++- drivers/gpu/drm/i915/intel_memory_region.h | 53 +- drivers/gpu/drm/i915/intel_region_lmem.c | 168 ++-- drivers/gpu/drm/i915/intel_region_lmem.h | 3 +- drivers/gpu/drm/i915/intel_uncore.c | 12 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 100 +- .../drm/i915/selftests/i915_live_selftests.h | 1 + drivers/gpu/drm/i915/selftests/i915_perf.c | 3 +- drivers/gpu/drm/i915/selftests/i915_request.c | 10 +- drivers/gpu/drm/i915/selftests/igt_spinner.c | 136 ++- drivers/gpu/drm/i915/selftests/igt_spinner.h | 5 + .../drm/i915/selftests/intel_memory_region.c | 442 ++++++++- drivers/gpu/drm/i915/selftests/mock_region.c | 4 +- include/uapi/drm/i915_drm.h | 118 +++ 148 files changed, 7813 insertions(+), 3312 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_create.c delete mode 100644 drivers/gpu/drm/i915/gem/i915_gem_fence.c create mode 100644 drivers/gpu/drm/i915/gt/gen8_engine_cs.c create mode 100644 drivers/gpu/drm/i915/gt/gen8_engine_cs.h create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_workaround_bb.c create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_workaround_bb.h rename drivers/gpu/drm/i915/gt/{intel_lrc.c => intel_execlists_submission.c} (87%) create mode 100644 drivers/gpu/drm/i915/gt/intel_execlists_submission.h delete mode 100644 drivers/gpu/drm/i915/gt/intel_lrc.h rename drivers/gpu/drm/i915/gt/{selftest_lrc.c => selftest_execlists.c} (99%) create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h -- 2.26.2

9 207

[PATCH v2 00/48] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs
by Dmitry Osipenko 12 Jan '21

12 Jan '21

Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces power consumption and heating of the Tegra chips. Tegra SoC has multiple hardware units which belong to a core power domain of the SoC and share the core voltage. The voltage must be selected in accordance to a minimum requirement of every core hardware unit. The minimum core voltage requirement depends on: 1. Clock enable state of a hardware unit. 2. Clock frequency. 3. Unit's internal idling/active state. This series is tested on Acer A500 (T20), AC100 (T20), Nexus 7 (T30), Ouya (T30), TK1 (T124) and some others. I also added voltage scaling to the Ventana (T20) and Cardhu (T30) boards which are tested by NVIDIA's CI farm. Tegra30 is now couple degrees cooler on Nexus 7 and stays cool on Ouya (instead of becoming burning hot) while system is idling. It should be possible to improve this further by implementing a more advanced power management features for the kernel drivers. The DVFS support is opt-in for all boards, meaning that older DTBs will continue to work like they did it before this series. It should be possible to easily add the core voltage scaling support for Tegra114+ SoCs based on this grounding work later on, if anyone will want to implement it. Changelog: v2: - Replaced Core voltage regulator with a Core power domain. The voltage control is now done using GENPD API. This was suggested by Ulf Hansson. - Added basic runtime PM and GENPD support to 2d, 3d, host1x and clk drivers. - Added new core-power-domain and clk-device drivers. Some high-freq PLLs and clocks require a higher minimum core voltage and the new clk-device driver manages the voltage for these clocks based on the clock state. - Moved voltage scaling entirely to the new clk-device driver for devices which don't require advanced power management, like PWM for example. - Added devm_tegra_core_dev_init_opp_table() common helper which sets up OPP table for Tegra drivers. - Added resource-managed version for OPP API functions, as it was discussed previously in the comments to v1. - Added new APIs, features and fixed various bugs related to voltage scaling and power management done via GENPD API. Dmitry Osipenko (48): dt-bindings: memory: tegra20: emc: Replace core regulator with power domain dt-bindings: memory: tegra30: emc: Replace core regulator with power domain dt-bindings: memory: tegra124: emc: Replace core regulator with power domain dt-bindings: host1x: Document OPP and power domain properties media: dt: bindings: tegra-vde: Document OPP and power domain properties dt-bindings: clock: tegra: Document clocks sub-node dt-bindings: arm: tegra: Add binding for core power domain regulator: Make regulator_sync_voltage() usable by coupled regulators opp: Add dev_pm_opp_sync_regulators() opp: Add dev_pm_opp_set_voltage() opp: Add dev_pm_opp_find_level_ceil() opp: Add dev_pm_opp_get_required_pstate() opp: Add resource-managed versions of OPP API functions opp: Filter out OPPs based on availability of a required-OPP opp: Support set_opp() customization without requiring to use regulators opp: Handle missing OPP table in dev_pm_opp_xlate_performance_state() opp: Correct debug message in _opp_add_static_v2() opp: Print OPP level in debug message of _opp_add_static_v2() opp: Fix adding OPP entries in a wrong order if rate is unavailable PM: domains: Make set_performance_state() callback optional PM: domains: Add "performance" column to debug summary soc/tegra: pmc: Fix imbalanced clock disabling in error code path soc/tegra: pmc: Pulse resets after removing power clamp soc/tegra: pmc: Ensure that clock rates aren't too high soc/tegra: pmc: Print out domain name when reset fails to acquire soc/tegra: Add devm_tegra_core_dev_init_opp_table() soc/tegra: Add CONFIG_SOC_TEGRA_COMMON and select PM_OPP by default soc/tegra: Introduce core power domain driver soc/tegra: pmc: Link domains to the parent Core domain soc/tegra: regulators: Fix locking up when voltage-spread is out of range soc/tegra: regulators: Support Core domain state syncing clk: tegra: Support runtime PM, power domain and OPP gpu: host1x: Add host1x_channel_stop() gpu: host1x: Support power management drm/tegra: dc: Support OPP and SoC core voltage scaling drm/tegra: gr2d: Correct swapped device-tree compatibles drm/tegra: gr2d: Support OPP and power management drm/tegra: g3d: Support OPP and power management drm/tegra: vic: Stop channel before suspending media: staging: tegra-vde: Support OPP and generic power domain memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table() memory: tegra30-emc: Use devm_tegra_core_dev_init_opp_table() ARM: tegra: Add OPP tables and power domains to Tegra20 device-tree ARM: tegra: Add OPP tables and power domains to Tegra30 device-tree ARM: tegra: acer-a500: Enable core voltage scaling ARM: tegra: ventana: Enable core voltage scaling ARM: tegra: ventana: Support CPU voltage scaling and thermal throttling ARM: tegra: cardhu: Support CPU voltage scaling and thermal throttling .../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 + .../bindings/clock/nvidia,tegra20-car.txt | 26 + .../bindings/clock/nvidia,tegra30-car.txt | 26 + .../display/tegra/nvidia,tegra20-host1x.txt | 49 + .../bindings/media/nvidia,tegra-vde.txt | 12 + .../nvidia,tegra124-emc.yaml | 6 +- .../memory-controllers/nvidia,tegra20-emc.txt | 4 +- .../nvidia,tegra30-emc.yaml | 6 +- .../boot/dts/tegra20-acer-a500-picasso.dts | 8 +- arch/arm/boot/dts/tegra20-colibri.dtsi | 6 +- arch/arm/boot/dts/tegra20-harmony.dts | 6 +- arch/arm/boot/dts/tegra20-paz00.dts | 46 +- .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 941 +++++++++++ arch/arm/boot/dts/tegra20-seaboard.dts | 6 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 6 +- arch/arm/boot/dts/tegra20-trimslice.dts | 12 + arch/arm/boot/dts/tegra20-ventana.dts | 78 +- arch/arm/boot/dts/tegra20.dtsi | 220 +++ .../tegra30-asus-nexus7-grouper-common.dtsi | 4 + arch/arm/boot/dts/tegra30-beaver.dts | 4 + arch/arm/boot/dts/tegra30-cardhu.dtsi | 81 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 20 +- arch/arm/boot/dts/tegra30-ouya.dts | 4 + .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 1412 +++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 358 +++++ drivers/base/power/domain.c | 33 +- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-device.c | 222 +++ drivers/clk/tegra/clk-divider.c | 2 +- drivers/clk/tegra/clk-periph-gate.c | 2 +- drivers/clk/tegra/clk-periph.c | 2 +- drivers/clk/tegra/clk-pll.c | 2 +- drivers/clk/tegra/clk-super.c | 4 +- drivers/clk/tegra/clk-tegra-periph.c | 140 +- drivers/clk/tegra/clk-tegra114.c | 1 + drivers/clk/tegra/clk-tegra124.c | 1 + drivers/clk/tegra/clk-tegra20-emc.c | 2 +- drivers/clk/tegra/clk-tegra20.c | 123 +- drivers/clk/tegra/clk-tegra210.c | 1 + drivers/clk/tegra/clk-tegra30.c | 133 +- drivers/clk/tegra/clk.c | 89 ++ drivers/clk/tegra/clk.h | 7 + drivers/gpu/drm/tegra/dc.c | 66 +- drivers/gpu/drm/tegra/gr2d.c | 77 +- drivers/gpu/drm/tegra/gr3d.c | 264 ++- drivers/gpu/drm/tegra/vic.c | 15 + drivers/gpu/host1x/channel.c | 8 + drivers/gpu/host1x/dev.c | 102 +- drivers/memory/tegra/tegra20-emc.c | 57 +- drivers/memory/tegra/tegra30-emc.c | 57 +- drivers/opp/core.c | 390 ++++- drivers/opp/of.c | 34 +- drivers/opp/opp.h | 2 +- drivers/regulator/core.c | 6 + drivers/soc/tegra/Kconfig | 19 + drivers/soc/tegra/Makefile | 1 + drivers/soc/tegra/common.c | 137 ++ drivers/soc/tegra/core-power-domain.c | 125 ++ drivers/soc/tegra/pmc.c | 122 +- drivers/soc/tegra/regulators-tegra20.c | 19 +- drivers/soc/tegra/regulators-tegra30.c | 20 +- drivers/staging/media/tegra-vde/vde.c | 63 +- include/linux/host1x.h | 1 + include/linux/pm_opp.h | 81 + include/soc/tegra/common.h | 41 + 65 files changed, 5458 insertions(+), 403 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml create mode 100644 drivers/clk/tegra/clk-device.c create mode 100644 drivers/soc/tegra/core-power-domain.c -- 2.29.2

7 120

[PATCH v1 0/2] Add MIPI rx DPI support
by Xin Ji 12 Jan '21

12 Jan '21

Hi all, this patch series implement MIPI rx DPI feature. Please help to review. This is the v1 version, any mistakes, please let me know, I'll fix it in the next series. Change history: v1: initial MIPI rx DPI feature support Xin Ji (2): dt-bindings: drm/bridge: anx7625: add DPI flag and swing setting drm/bridge: anx7625: add MIPI DPI input feature support .../bindings/display/bridge/analogix,anx7625.yaml | 19 ++ drivers/gpu/drm/bridge/analogix/anx7625.c | 352 +++++++++++++++++++-- drivers/gpu/drm/bridge/analogix/anx7625.h | 24 +- 3 files changed, 375 insertions(+), 20 deletions(-) -- 2.7.4

4 11

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dri-devel December 2020