dri-devel December 2020

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278 participants
659 discussions

[PATCH] drm/msm/dsi: save PLL registers across first PHY reset
by benl-kernelpatches＠squareup.com 15 May '21

15 May '21

From: Benjamin Li <benl(a)squareup.com> Take advantage of previously-added support for persisting PLL registers across DSI PHY disable/enable cycles (see 328e1a6 'drm/msm/dsi: Save/Restore PLL status across PHY reset') to support persisting across the very first DSI PHY enable at boot. The bootloader may have left the PLL registers in a non-default state. For example, for dsi_pll_28nm.c on 8x16/8x39, the byte clock mux's power-on reset configuration is to bypass DIV1, but depending on … [View More]bandwidth requirements[1] the bootloader may have set the DIV1 path. When the byte clock mux is registered with the generic clock framework at probe time, the framework reads & caches the value of the mux bit field (the initial clock parent). After PHY enable, when clk_set_rate is called on the byte clock, the framework assumes there is no need to reparent, and doesn't re-write the mux bit field. But PHY enable resets PLL registers, so the mux bit field actually silently reverted to the DIV1 bypass path. This causes the byte clock to be off by a factor of e.g. 2 for our tested WXGA panel. The above issue manifests as the display not working and a constant stream of FIFO/LP0 contention errors. [1] The specific requirement for triggering the DIV1 path (and thus this issue) on 28nm is a panel with pixel clock <116.7MHz (one-third the minimum VCO setting). FHD/1080p (~145MHz) is fine, WXGA/1280x800 (~75MHz) is not. Signed-off-by: Benjamin Li <benl(a)squareup.com> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 009f5b843dd1..139b4a5aaf86 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -621,6 +621,22 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) phy->pll = NULL; } + /* + * As explained in msm_dsi_phy_enable, resetting the DSI PHY (as done + * in dsi_mgr_phy_enable) silently changes its PLL registers to power-on + * defaults, but the generic clock framework manages and caches several + * of the PLL registers. It initializes these caches at registration + * time via register read. + * + * As a result, we need to save DSI PLL registers once at probe in order + * for the first call to msm_dsi_phy_enable to successfully bring PLL + * registers back in line with what the generic clock framework expects. + * + * Subsequent PLL restores during msm_dsi_phy_enable will always be + * paired with PLL saves in msm_dsi_phy_disable. + */ + msm_dsi_pll_save_state(phy->pll); + dsi_phy_disable_resource(phy); platform_set_drvdata(pdev, phy); -- 2.17.1 [View Less]

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[Bug 51381] New: [drm:atom_op_jump] *ERROR* atombios stuck in loop for more than 5secs aborting, when disabled via vgaswitcheroo
by bugzilla-daemon＠bugzilla.kernel.org 11 May '21

11 May '21

https://bugzilla.kernel.org/show_bug.cgi?id=51381 Summary: [drm:atom_op_jump] *ERROR* atombios stuck in loop for more than 5secs aborting, when disabled via vgaswitcheroo Product: Drivers Version: 2.5 Kernel Version: Linux version 3.6.9-1-ARCH (tobias@T-POWA-LX) (gcc version 4.7.2 (GCC) ) #1 SMP PREEMPT Tue Dec 4 08:04:10 CET 2012 Platform: All OS/Version: … [View More]

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[PATCH 1/3] drm/exynos: Init the DSIM PHY in samsung_dsim_enable()
by Marek Vasut 10 May '21

10 May '21

In case the PHY is not initialized, do it in samsung_dsim_enable(), otherwise the link configuration registers are not programmed at all. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Guido Günther <agx(a)sigxcpu.org> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Lucas Stach <l.stach(a)pengutronix.de> Cc: Marek Szyprowski <m.szyprowski(a)samsung.com> Cc: Michael Tretter <m.tretter(a)pengutronix.de> Cc: NXP … [View More]

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[PATCH v3 0/4] drm/bridge: ti-sn65dsi86: Support EDID reading
by Stephen Boyd 07 May '21

07 May '21

This patch series cleans up the DDC code a little bit so that it is more efficient time wise and supports grabbing the EDID of the eDP panel over the aux channel. I timed this on a board I have on my desk and it takes about 20ms to grab the EDID out of the panel and make sure it is valid. The first two patches seem less controversial so I stuck them at the beginning. The third patch does the EDID reading and caches it so we don't have to keep grabbing it over and over again. And finally the … [View More]

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[Bug 207833] New: Brightness control not working on ASUS TUF FA506IU (AMD Ryzen 7 4800H / Nvidia GTX 1660 Ti)
by bugzilla-daemon＠bugzilla.kernel.org 06 May '21

06 May '21

https://bugzilla.kernel.org/show_bug.cgi?id=207833 Bug ID: 207833 Summary: Brightness control not working on ASUS TUF FA506IU (AMD Ryzen 7 4800H / Nvidia GTX 1660 Ti) Product: Drivers Version: 2.5 Kernel Version: 5.6.12-1 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: high Priority: P1 Component: Video(DRI - non Intel) … [View More]Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: julen.pardo(a)outlook.es Regression: No Hello, I've just bought an ASUS TUF FA506IU with and AMD Ryzen 7 4800H / Nvidia GTX 1660 Ti setup. Even if this is quite new hardware, I'd say that the only thing that is not working at all is the brightness control. It's not working with the function keys, nor from the energy settings, nor with xbacklight. Actually, it's working a little; I can find a subtle difference between the max value and the last 5 values, but that's it. Setting it to the minimum still makes it way too bright. I've noticed that this could be a range mismatch between "brightness" and "max_brightness", and "actual_brightness". First are in 8 bit ranges, whereas the actual brightness is in 16 bit range. I've tried some luck patching the kernel to return an 8-bit value (https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/amd/display/d…), but doing just that doesn't work (even if the "actual_brightness" was showing an 8 bit value). In my case, the full path is "/sys/class/backlight/amdgpu_bl1/". I've also tried different acpi_backlight parameters with no luck. I leave the output of lsmod | grep asus: asus_wmi 40960 0 sparse_keymap 16384 1 asus_wmi rfkill 28672 9 asus_wmi,bluetooth,cfg80211 battery 24576 1 asus_wmi wmi 36864 2 asus_wmi,wmi_bmof asus_wireless 20480 0 inxi -F: System: Host: TUF-FA506IU Kernel: 5.6.12-1-MANJARO x86_64 bits: 64 Desktop: KDE Plasma 5.18.5 Distro: Manjaro Linux Machine: Type: Laptop System: ASUSTeK product: TUF Gaming FA506IU_FA506IU v: 1.0 serial: <root required> Mobo: ASUSTeK model: FA506IU v: 1.0 serial: <root required> UEFI: American Megatrends v: FA506IU.302 date: 03/04/2020 Battery: ID-1: BAT1 charge: 47.9 Wh condition: 47.9/48.1 Wh (100%) CPU: Topology: 8-Core model: AMD Ryzen 7 4800H with Radeon Graphics bits: 64 type: MT MCP L2 cache: 4096 KiB Speed: 2405 MHz min/max: 1400/2900 MHz Core speeds (MHz): 1: 1875 2: 2497 3: 1397 4: 1397 5: 1397 6: 1397 7: 1397 8: 1397 9: 1397 10: 1396 11: 2963 12: 1673 13: 1800 14: 1548 15: 1397 16: 1396 Graphics: Device-1: NVIDIA TU116M [GeForce GTX 1660 Ti Mobile] driver: nvidia v: 440.82 Device-2: Advanced Micro Devices [AMD/ATI] Renoir driver: amdgpu v: kernel Display: x11 server: X.Org 1.20.8 driver: amdgpu,nvidia resolution: 1920x1080~144Hz, 2560x1440~60Hz OpenGL: renderer: AMD RENOIR (DRM 3.36.0 5.6.12-1-MANJARO LLVM 10.0.0) v: 4.6 Mesa 20.0.6 Audio: Device-1: NVIDIA TU116 High Definition Audio driver: snd_hda_intel Device-2: Advanced Micro Devices [AMD/ATI] driver: snd_hda_intel Device-3: Advanced Micro Devices [AMD] Raven/Raven2/FireFlight/Renoir Audio Processor driver: N/A Device-4: Advanced Micro Devices [AMD] Family 17h HD Audio driver: snd_hda_intel Sound Server: ALSA v: k5.6.12-1-MANJARO Network: Device-1: Realtek RTL8111/8168/8411 PCI Express Gigabit Ethernet driver: r8169 IF: enp2s0 state: down mac: a8:5e:45:36:94:32 Device-2: Realtek RTL8822CE 802.11ac PCIe Wireless Network Adapter driver: rtw_pci IF: wlp3s0 state: up mac: 70:66:55:09:8c:e3 Drives: Local Storage: total: 476.94 GiB used: 32.41 GiB (6.8%) ID-1: /dev/nvme0n1 vendor: Kingston model: OM8PCP3512F-AB size: 476.94 GiB Partition: ID-1: / size: 48.97 GiB used: 25.95 GiB (53.0%) fs: ext4 dev: /dev/nvme0n1p5 ID-2: /home size: 108.67 GiB used: 6.46 GiB (5.9%) fs: ext4 dev: /dev/nvme0n1p7 ID-3: swap-1 size: 3.03 GiB used: 0 KiB (0.0%) fs: swap dev: /dev/nvme0n1p8 Sensors: Message: No sensors data was found. Is sensors configured? Info: Processes: 349 Uptime: 27m Memory: 7.20 GiB used: 3.04 GiB (42.2%) Shell: zsh inxi: 3.0.37 -- You are receiving this mail because: You are watching the assignee of the bug. [View Less]

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[Bug 203905] New: amdgpu:actual_brightness has unreal/wrong value
by bugzilla-daemon＠bugzilla.kernel.org 06 May '21

06 May '21

https://bugzilla.kernel.org/show_bug.cgi?id=203905 Bug ID: 203905 Summary: amdgpu:actual_brightness has unreal/wrong value Product: Drivers Version: 2.5 Kernel Version: 5.1.9 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org … [View More]

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[PATCH 1/2] mm: cma: export functions to get CMA base and size
by Lucas Stach 03 May '21

03 May '21

Make them usable in modules. Some drivers want to know where their device CMA area is located to make better decisions about the DMA programming. Signed-off-by: Lucas Stach <l.stach(a)pengutronix.de> --- mm/cma.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/mm/cma.c b/mm/cma.c index 3340ef34c154..191c89bf038d 100644 --- a/mm/cma.c +++ b/mm/cma.c @@ -44,11 +44,13 @@ phys_addr_t cma_get_base(const struct cma *cma) { return PFN_PHYS(cma->base_pfn); } +EXPORT_SYMBOL_GPL(… [View More]

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[PATCH] ASoC: fsl: imx-pcm-dma: Don't request dma channel in probe
by Shengjiu Wang 22 Apr '21

22 Apr '21

There are two requirements that we need to move the request of dma channel from probe to open. - When dma device binds with power-domains, the power will be enabled when we request dma channel. If the request of dma channel happen on probe, then the power-domains will be always enabled after kernel boot up, which is not good for power saving, so we need to move the request of dma channel to .open(); - With FE-BE case, if the dma channel is requested in probe, then there will be below issue, … [View More]which is caused by that the dma channel will be requested duplicately [ 638.906268] sysfs: cannot create duplicate filename '/devices/soc0/soc/2000000.bus/2000000.spba-bus/2024000.esai/dma:tx' [ 638.919061] CPU: 1 PID: 673 Comm: aplay Not tainted 5.7.0-rc1-12956-gfc64b2585593 #287 [ 638.927113] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) [ 638.933690] [<c0110dd8>] (unwind_backtrace) from [<c010b8ec>] (show_stack+0x10/0x14) [ 638.941464] [<c010b8ec>] (show_stack) from [<c0557fc0>] (dump_stack+0xe4/0x118) [ 638.948808] [<c0557fc0>] (dump_stack) from [<c032aeb4>] (sysfs_warn_dup+0x50/0x64) [ 638.956406] [<c032aeb4>] (sysfs_warn_dup) from [<c032b1a8>] (sysfs_do_create_link_sd+0xc8/0xd4) [ 638.965134] [<c032b1a8>] (sysfs_do_create_link_sd) from [<c05dc668>] (dma_request_chan+0xb0/0x210) [ 638.974120] [<c05dc668>] (dma_request_chan) from [<c05dc7d0>] (dma_request_slave_channel+0x8/0x14) [ 638.983111] [<c05dc7d0>] (dma_request_slave_channel) from [<c09d5548>] (fsl_asrc_dma_hw_params+0x1e0/0x438) [ 638.992881] [<c09d5548>] (fsl_asrc_dma_hw_params) from [<c09c1654>] (soc_pcm_hw_params+0x4a0/0x6a8) [ 639.001952] [<c09c1654>] (soc_pcm_hw_params) from [<c09c39d4>] (dpcm_fe_dai_hw_params+0x70/0xe4) [ 639.010765] [<c09c39d4>] (dpcm_fe_dai_hw_params) from [<c099b274>] (snd_pcm_hw_params+0x158/0x418) [ 639.019750] [<c099b274>] (snd_pcm_hw_params) from [<c099c5a0>] (snd_pcm_ioctl+0x734/0x183c) [ 639.028129] [<c099c5a0>] (snd_pcm_ioctl) from [<c029ff94>] (ksys_ioctl+0x2ac/0xb98) [ 639.035812] [<c029ff94>] (ksys_ioctl) from [<c0100080>] (ret_fast_syscall+0x0/0x28) [ 639.043490] Exception stack(0xec529fa8 to 0xec529ff0) [ 639.048565] 9fa0: bee84650 01321870 00000004 c25c4111 bee84650 0002000f [ 639.056766] 9fc0: bee84650 01321870 01321820 00000036 00001f40 00000000 0002c2f8 00000003 [ 639.064964] 9fe0: b6f483fc bee8451c b6ee2655 b6e1dcf8 [ 639.070339] fsl-esai-dai 2024000.esai: Cannot create DMA dma:tx symlink Signed-off-by: Shengjiu Wang <shengjiu.wang(a)nxp.com> --- sound/soc/fsl/imx-pcm-dma.c | 173 +++++++++++++++++++++++++++++++++--- 1 file changed, 159 insertions(+), 14 deletions(-) diff --git a/sound/soc/fsl/imx-pcm-dma.c b/sound/soc/fsl/imx-pcm-dma.c index 04a9bc749016..dae53b384df4 100644 --- a/sound/soc/fsl/imx-pcm-dma.c +++ b/sound/soc/fsl/imx-pcm-dma.c @@ -11,6 +11,7 @@ #include <linux/dmaengine.h> #include <linux/types.h> #include <linux/module.h> +#include <linux/dma-mapping.h> #include <sound/core.h> #include <sound/pcm.h> @@ -29,24 +30,168 @@ static bool filter(struct dma_chan *chan, void *param) return true; } -static const struct snd_dmaengine_pcm_config imx_dmaengine_pcm_config = { - .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, - .compat_filter_fn = filter, -}; +static int imx_pcm_hw_params(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + struct snd_dmaengine_dai_dma_data *dma_data; + struct dma_slave_config config; + struct dma_chan *chan; + int ret = 0; -int imx_pcm_dma_init(struct platform_device *pdev, size_t size) + snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); + runtime->dma_bytes = params_buffer_bytes(params); + + chan = snd_dmaengine_pcm_get_chan(substream); + if (!chan) + return -EINVAL; + + ret = snd_hwparams_to_dma_slave_config(substream, params, &config); + if (ret) + return ret; + + dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); + if (!dma_data) + return -EINVAL; + + snd_dmaengine_pcm_set_config_from_dai_data(substream, + dma_data, + &config); + return dmaengine_slave_config(chan, &config); +} + +static int imx_pcm_hw_free(struct snd_soc_component *component, + struct snd_pcm_substream *substream) { - struct snd_dmaengine_pcm_config *config; + snd_pcm_set_runtime_buffer(substream, NULL); + return 0; +} + +static snd_pcm_uframes_t imx_pcm_pointer(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + return snd_dmaengine_pcm_pointer(substream); +} + +static int imx_pcm_trigger(struct snd_soc_component *component, + struct snd_pcm_substream *substream, int cmd) +{ + return snd_dmaengine_pcm_trigger(substream, cmd); +} + +static int imx_pcm_open(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + struct snd_dmaengine_dai_dma_data *dma_data; + struct device *dev = component->dev; + struct snd_pcm_hardware hw; + struct dma_chan *chan; + int ret; + + ret = snd_pcm_hw_constraint_integer(substream->runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) { + dev_err(dev, "failed to set pcm hw params periods\n"); + return ret; + } + + dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); + if (!dma_data) + return -EINVAL; + + chan = dma_request_slave_channel(cpu_dai->dev, tx ? "tx" : "rx"); + if (!chan) { + /* Try to request channel using compat_filter_fn */ + chan = snd_dmaengine_pcm_request_channel(filter, + dma_data->filter_data); + if (!chan) + return -ENXIO; + } - config = devm_kzalloc(&pdev->dev, - sizeof(struct snd_dmaengine_pcm_config), GFP_KERNEL); - if (!config) - return -ENOMEM; - *config = imx_dmaengine_pcm_config; + ret = snd_dmaengine_pcm_open(substream, chan); + if (ret) + goto pcm_open_fail; - return devm_snd_dmaengine_pcm_register(&pdev->dev, - config, - SND_DMAENGINE_PCM_FLAG_COMPAT); + memset(&hw, 0, sizeof(hw)); + hw.info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED; + hw.periods_min = 2; + hw.periods_max = UINT_MAX; + hw.period_bytes_min = 256; + hw.period_bytes_max = dma_get_max_seg_size(chan->device->dev); + hw.buffer_bytes_max = IMX_DEFAULT_DMABUF_SIZE; + hw.fifo_size = dma_data->fifo_size; + + /* Refine the hw according to caps of DMA. */ + ret = snd_dmaengine_pcm_refine_runtime_hwparams(substream, + dma_data, + &hw, + chan); + if (ret < 0) + goto refine_runtime_hwparams_fail; + + snd_soc_set_runtime_hwparams(substream, &hw); + + /* Support allocate memory from IRAM */ + ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_IRAM, + chan->device->dev, + hw.buffer_bytes_max, + &substream->dma_buffer); + if (ret < 0) + goto alloc_pagas_fail; + + return 0; + +alloc_pagas_fail: +refine_runtime_hwparams_fail: + snd_dmaengine_pcm_close(substream); +pcm_open_fail: + dma_release_channel(chan); + + return ret; +} + +static int imx_pcm_close(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + if (substream) { + snd_dma_free_pages(&substream->dma_buffer); + substream->dma_buffer.area = NULL; + substream->dma_buffer.addr = 0; + } + + return snd_dmaengine_pcm_close_release_chan(substream); +} + +static int imx_pcm_new(struct snd_soc_component *component, + struct snd_soc_pcm_runtime *rtd) +{ + struct snd_card *card = rtd->card->snd_card; + + return dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32)); +} + +static const struct snd_soc_component_driver imx_pcm_component = { + .name = "imx-pcm-dma", + .pcm_construct = imx_pcm_new, + .open = imx_pcm_open, + .close = imx_pcm_close, + .hw_params = imx_pcm_hw_params, + .hw_free = imx_pcm_hw_free, + .trigger = imx_pcm_trigger, + .pointer = imx_pcm_pointer, +}; + +int imx_pcm_dma_init(struct platform_device *pdev, size_t size) +{ + return devm_snd_soc_register_component(&pdev->dev, + &imx_pcm_component, NULL, 0); } EXPORT_SYMBOL_GPL(imx_pcm_dma_init); -- 2.21.0 [View Less]

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[PATCH v2 00/16] drm/exynos: Convert driver to drm bridge
by Michael Tretter 20 Apr '21

20 Apr '21

This is v2 of the series to convert the Exynos MIPI DSI driver into a drm bridge and make it usable with other drivers. Although the driver is converted, it still supports the component framework API to stay compliant with the Exynos DRM driver. The Exynos MIPI DSI Phy is also found on the i.MX8M Mini. However, on the i.MX8M Mini, the bridge is driven by an LCDIF display controller instead of the Exynos Decon. The driver for the LCDIF does not use the component framework, but uses drm bridges. … [View More] I don't have any Exynos SoC to actually test the series. I build a dummy to test the bridge with a component driver, to make sure that at least the initialization is working. Furthermore, tested the driver as a bridge with a few additional unfinished patches on the i.MX8M Mini EVK. However, somebody should verify that the driver is still working on Exynos hardware. I also changed the order of the patches to first make the driver more platform independent (patches 2 to 8), then convert to a drm bridge driver (patches 10 to 13) and finally expose the API, split the code and move the platform independent driver to the bridges (patches 14 - 16). Hopefully this simplifies testing/bisecting and helps me to understand potential error reports. Also I added host_ops for attach/detach and the tearing effect handler to make the calls into the platform code more visible. Furthermore, the series should now apply to linux-next and correctly build the exynos_defconfig. Thanks, Michael Changelog: v2: - rebase on linux-next - verify with exynos_defconfig - fix crashes reported by Marek Szyprowski Exynos3250-based Rinato - reorder patches - add host_ops for platform specific code - roughly test component framework integration with dummy Michael Tretter (16): drm/encoder: remove obsolete documentation of bridge drm/exynos: remove in_bridge_node from exynos_dsi drm/exynos: use exynos_dsi as drvdata drm/exynos: extract helper functions for probe drm/exynos: move dsi host registration to probe drm/exynos: shift register values to fields on write drm/exynos: use identifier instead of register offsets drm/exynos: add host_ops callback for platform drivers drm/exynos: add callback for tearing effect handler drm/exynos: implement a drm bridge drm/exynos: convert encoder functions to bridge function drm/exynos: configure mode on drm bridge drm/exynos: get encoder from bridge whenever possible drm/exynos: add API functions for platform drivers drm/exynos: split out platform specific code drm/exynos: move bridge driver to bridges drivers/gpu/drm/bridge/Kconfig | 9 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/samsung-dsim.c | 1790 +++++++++++++++++++++ drivers/gpu/drm/exynos/Kconfig | 5 +- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 1927 ++--------------------- include/drm/bridge/samsung-dsim.h | 64 + include/drm/drm_encoder.h | 1 - 7 files changed, 2027 insertions(+), 1770 deletions(-) create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c create mode 100644 include/drm/bridge/samsung-dsim.h -- 2.20.1 [View Less]

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[PATCH V2] drm/bridge: lvds-codec: Add support for pixel data sampling edge select
by Marek Vasut 16 Apr '21

16 Apr '21

The OnSemi FIN3385 Parallel-to-LVDS encoder has a dedicated input line to select input pixel data sampling edge. Add DT property "pixelclk-active", same as the one used by display timings, and configure bus flags based on this DT property. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Alexandre Torgue <alexandre.torgue(a)st.com> Cc: Andrzej Hajda <a.hajda(a)samsung.com> Cc: Antonio Borneo <antonio.borneo(a)st.com> Cc: Benjamin Gaignard <benjamin.gaignard(a)st.com&… [View More]gt; Cc: Biju Das <biju.das.jz(a)bp.renesas.com> Cc: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Cc: Maxime Coquelin <mcoquelin.stm32(a)gmail.com> Cc: Philippe Cornu <philippe.cornu(a)st.com> Cc: Sam Ravnborg <sam(a)ravnborg.org> Cc: Vincent Abriou <vincent.abriou(a)st.com> Cc: Yannick Fertre <yannick.fertre(a)st.com> Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-stm32(a)st-md-mailman.stormreply.com To: dri-devel(a)lists.freedesktop.org --- V2: - Limit the pixelclk-active to encoders only - Update DT binding document --- .../bindings/display/bridge/lvds-codec.yaml | 7 +++ drivers/gpu/drm/bridge/lvds-codec.c | 52 +++++++++++++------ 2 files changed, 44 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml index e5e3c72630cf..399a6528780a 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml @@ -74,6 +74,13 @@ properties: additionalProperties: false + pixelclk-active: + description: | + Data sampling on rising or falling edge. + Use 0 to sample pixel data on rising edge and + Use 1 to sample pixel data on falling edge and + enum: [0, 1] + powerdown-gpios: description: The GPIO used to control the power down line of this device. diff --git a/drivers/gpu/drm/bridge/lvds-codec.c b/drivers/gpu/drm/bridge/lvds-codec.c index dcf579a4cf83..cab81ccd895d 100644 --- a/drivers/gpu/drm/bridge/lvds-codec.c +++ b/drivers/gpu/drm/bridge/lvds-codec.c @@ -15,13 +15,18 @@ #include <drm/drm_bridge.h> #include <drm/drm_panel.h> +struct lvds_codec_data { + u32 connector_type; + bool is_encoder; +}; + struct lvds_codec { struct device *dev; struct drm_bridge bridge; struct drm_bridge *panel_bridge; + struct drm_bridge_timings timings; struct regulator *vcc; struct gpio_desc *powerdown_gpio; - u32 connector_type; }; static inline struct lvds_codec *to_lvds_codec(struct drm_bridge *bridge) @@ -76,17 +81,20 @@ static const struct drm_bridge_funcs funcs = { static int lvds_codec_probe(struct platform_device *pdev) { + const struct lvds_codec_data *data; struct device *dev = &pdev->dev; struct device_node *panel_node; struct drm_panel *panel; struct lvds_codec *lvds_codec; + u32 val; lvds_codec = devm_kzalloc(dev, sizeof(*lvds_codec), GFP_KERNEL); if (!lvds_codec) return -ENOMEM; + data = of_device_get_match_data(dev); + lvds_codec->dev = &pdev->dev; - lvds_codec->connector_type = (uintptr_t)of_device_get_match_data(dev); lvds_codec->vcc = devm_regulator_get(lvds_codec->dev, "power"); if (IS_ERR(lvds_codec->vcc)) @@ -115,10 +123,22 @@ static int lvds_codec_probe(struct platform_device *pdev) lvds_codec->panel_bridge = devm_drm_panel_bridge_add_typed(dev, panel, - lvds_codec->connector_type); + data->connector_type); if (IS_ERR(lvds_codec->panel_bridge)) return PTR_ERR(lvds_codec->panel_bridge); + /* + * Encoder might sample data on different clock edge than the display, + * for example OnSemi FIN3385 has a dedicated strapping pin to select + * the sampling edge. + */ + if (data->is_encoder && + !of_property_read_u32(dev->of_node, "pixelclk-active", &val)) { + lvds_codec->timings.input_bus_flags = val ? + DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE : + DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE; + } + /* * The panel_bridge bridge is attached to the panel's of_node, * but we need a bridge attached to our of_node for our user @@ -126,6 +146,7 @@ static int lvds_codec_probe(struct platform_device *pdev) */ lvds_codec->bridge.of_node = dev->of_node; lvds_codec->bridge.funcs = &funcs; + lvds_codec->bridge.timings = &lvds_codec->timings; drm_bridge_add(&lvds_codec->bridge); platform_set_drvdata(pdev, lvds_codec); @@ -142,19 +163,20 @@ static int lvds_codec_remove(struct platform_device *pdev) return 0; } +static const struct lvds_codec_data decoder_data = { + .connector_type = DRM_MODE_CONNECTOR_DPI, + .is_encoder = false, +}; + +static const struct lvds_codec_data encoder_data = { + .connector_type = DRM_MODE_CONNECTOR_LVDS, + .is_encoder = true, +}; + static const struct of_device_id lvds_codec_match[] = { - { - .compatible = "lvds-decoder", - .data = (void *)DRM_MODE_CONNECTOR_DPI, - }, - { - .compatible = "lvds-encoder", - .data = (void *)DRM_MODE_CONNECTOR_LVDS, - }, - { - .compatible = "thine,thc63lvdm83d", - .data = (void *)DRM_MODE_CONNECTOR_LVDS, - }, + { .compatible = "lvds-decoder", .data = &decoder_data, }, + { .compatible = "lvds-encoder", .data = &encoder_data, }, + { .compatible = "thine,thc63lvdm83d", .data = &encoder_data, }, {}, }; MODULE_DEVICE_TABLE(of, lvds_codec_match); -- 2.29.2 [View Less]

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dri-devel December 2020