dri-devel February 2020

dri-devel@lists.freedesktop.org

302 participants
679 discussions

[PATCH v2 0/2] ASoC hdmi-codec: fix HDMI jack reporting
by Tzung-Bi Shih 17 Feb '20

17 Feb '20

With proper unbinding audio components and inserting the HDMI external display, kernel crashes as the following messages: Unable to handle kernel NULL pointer dereference at virtual address ... [snip] Call trace: plugged_cb+0x1c/0x74 mtk_hdmi_update_plugged_status+0x48/0x6c hdmi_conn_detect+0x1c/0x28 drm_helper_probe_detect+0x110/0x170 drm_helper_probe_single_connector_modes+0xd4/0x608 drm_mode_getconnector+0x1e8/0x418 The 1st patch fixes the crash by notifying hdmi-codec's consumers to … [View More]

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[Bug 206577] New: Periodic screen blanking at a high refresh rate and resolution
by bugzilla-daemon＠bugzilla.kernel.org 17 Feb '20

17 Feb '20

https://bugzilla.kernel.org/show_bug.cgi?id=206577 Bug ID: 206577 Summary: Periodic screen blanking at a high refresh rate and resolution Product: Drivers Version: 2.5 Kernel Version: 5.5 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)… [View More]

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[drm-intel:drm-intel-next-queued 1/2] drivers/gpu/drm/i915/gt/intel_lrc.c:1224:3: note: in expansion of macro 'I915_SELFTEST_ONLY'
by kbuild test robot 17 Feb '20

17 Feb '20

Hi Tvrtko, FYI, the error/warning still remains. tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued head: d194314da04eb965c651dcef6d692dc83821a414 commit: 1883a0a4658eaba354db2179b4d3395247d27582 [1/2] drm/i915: Track hw reported context runtime config: i386-defconfig (attached as .config) compiler: gcc-7 (Debian 7.5.0-4) 7.5.0 reproduce: git checkout 1883a0a4658eaba354db2179b4d3395247d27582 # save the attached .config to linux build tree make ARCH=… [View More]i386 If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp(a)intel.com> All warnings (new ones prefixed by >>): In file included from drivers/gpu/drm/i915/gt/intel_engine_types.h:24:0, from drivers/gpu/drm/i915/gt/intel_context_types.h:18, from drivers/gpu/drm/i915/gem/i915_gem_context_types.h:20, from drivers/gpu/drm/i915/i915_request.h:31, from drivers/gpu/drm/i915/i915_active.h:13, from drivers/gpu/drm/i915/gem/i915_gem_object_types.h:13, from drivers/gpu/drm/i915/display/intel_frontbuffer.h:30, from drivers/gpu/drm/i915/i915_drv.h:72, from drivers/gpu/drm/i915/gt/intel_lrc.c:136: drivers/gpu/drm/i915/gt/intel_lrc.c: In function 'intel_context_update_runtime': drivers/gpu/drm/i915/i915_selftest.h:118:31: warning: statement with no effect [-Wunused-value] #define I915_SELFTEST_ONLY(x) 0 ^ >> drivers/gpu/drm/i915/gt/intel_lrc.c:1224:3: note: in expansion of macro 'I915_SELFTEST_ONLY' I915_SELFTEST_ONLY(ce->runtime.num_underflow += dt < 0); ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/i915_selftest.h:118:31: warning: statement with no effect [-Wunused-value] #define I915_SELFTEST_ONLY(x) 0 ^ drivers/gpu/drm/i915/gt/intel_lrc.c:1225:3: note: in expansion of macro 'I915_SELFTEST_ONLY' I915_SELFTEST_ONLY(ce->runtime.max_underflow = ^~~~~~~~~~~~~~~~~~ vim +/I915_SELFTEST_ONLY +1224 drivers/gpu/drm/i915/gt/intel_lrc.c 1208 1209 static void intel_context_update_runtime(struct intel_context *ce) 1210 { 1211 u32 old; 1212 s32 dt; 1213 1214 if (intel_context_is_barrier(ce)) 1215 return; 1216 1217 old = ce->runtime.last; 1218 ce->runtime.last = intel_context_get_runtime(ce); 1219 dt = ce->runtime.last - old; 1220 1221 if (unlikely(dt <= 0)) { 1222 CE_TRACE(ce, "runtime underflow: last=%u, new=%u, delta=%d\n", 1223 old, ce->runtime.last, dt); > 1224 I915_SELFTEST_ONLY(ce->runtime.num_underflow += dt < 0); 1225 I915_SELFTEST_ONLY(ce->runtime.max_underflow = 1226 max_t(u32, ce->runtime.max_underflow, -dt)); 1227 return; 1228 } 1229 1230 ewma_runtime_add(&ce->runtime.avg, dt); 1231 ce->runtime.total += dt; 1232 } 1233 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org [View Less]

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[RFC PATCH 0/6] do not store GPU address in TTM
by Nirmoy Das 17 Feb '20

17 Feb '20

With this patch series I am trying to remove GPU address dependency in TTM and moving GPU address calculation to individual drm drivers. I tested this patch series on qxl, bochs and amdgpu. Christian tested it on radeon HW. It would be nice if someone test this for nouveau and vmgfx. Nirmoy Das (7): drm/amdgpu: move ttm bo->offset to amdgpu_bo drm/radeon: don't use ttm bo->offset drm/vmwgfx: don't use ttm bo->offset drm/nouveau: don't use ttm bo->offset drm/qxl: don't … [View More]use ttm bo->offset drm/bochs: don't use ttm bo->offset drm/ttm: do not keep GPU dependent addresses drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 22 ++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 29 ++++++++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 + drivers/gpu/drm/bochs/bochs_kms.c | 3 ++- drivers/gpu/drm/drm_gem_vram_helper.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 6 ++--- drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/overlay.c | 6 ++--- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/core507d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 +- drivers/gpu/drm/nouveau/nouveau_abi16.c | 8 +++--- drivers/gpu/drm/nouveau/nouveau_bo.c | 1 + drivers/gpu/drm/nouveau/nouveau_bo.h | 3 +++ drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +- drivers/gpu/drm/nouveau/nouveau_dmem.c | 2 +- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 10 +++---- drivers/gpu/drm/qxl/qxl_drv.h | 5 ++-- drivers/gpu/drm/qxl/qxl_kms.c | 5 ++-- drivers/gpu/drm/qxl/qxl_object.h | 5 ---- drivers/gpu/drm/qxl/qxl_ttm.c | 9 ------- drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_object.h | 16 +++++++++++- drivers/gpu/drm/radeon/radeon_ttm.c | 4 +-- drivers/gpu/drm/ttm/ttm_bo.c | 7 ----- drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 4 +-- drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 -- include/drm/ttm/ttm_bo_api.h | 2 -- include/drm/ttm/ttm_bo_driver.h | 1 - 35 files changed, 100 insertions(+), 75 deletions(-) -- 2.25.0 [View Less]

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[v1] drm/msm/dsi/pll: call vco set rate explicitly
by Harigovindan P 17 Feb '20

17 Feb '20

For a given byte clock, if VCO recalc value is exactly same as vco set rate value, vco_set_rate does not get called assuming VCO is already set to required value. But Due to GDSC toggle, VCO values are erased in the HW. To make sure VCO is programmed correctly, we forcefully call set_rate from vco_prepare. Signed-off-by: Harigovindan P <harigovi(a)codeaurora.org> --- Changes in v1: - Calling set rate from vco_prepare drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 6 ++++++ 1 file … [View More]

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[PATCH 1/3] gpu/drm: ingenic: Add trick to support 16bpp on 24-bit panels
by Paul Cercueil 17 Feb '20

17 Feb '20

If the panel interface is 24-bit but our primary plane is 16bpp, configure as if the panel was 18-bit. This tricks permits the display of 16bpp data on a 24-bit panel by wiring each color component to the MSBs of the 24-bit interface. Signed-off-by: Paul Cercueil <paul(a)crapouillou.net> --- drivers/gpu/drm/ingenic/ingenic-drm.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-… [View More]

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[PATCH] dma-buf: Fix a typo in Kconfig
by Christophe JAILLET 17 Feb '20

17 Feb '20

A 'h' ismissing in' syncronization' Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> --- drivers/dma-buf/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma-buf/Kconfig b/drivers/dma-buf/Kconfig index 0613bb7770f5..e7d820ce0724 100644 --- a/drivers/dma-buf/Kconfig +++ b/drivers/dma-buf/Kconfig @@ -6,7 +6,7 @@ config SYNC_FILE default n select DMA_SHARED_BUFFER ---help--- - The Sync File Framework adds explicit syncronization … [View More]

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[PATCH] Correct typos in comments
by Maya Rashish 17 Feb '20

17 Feb '20

Signed-off-by: Maya Rashish <maya(a)NetBSD.org> Co-authored-by: Thomas Klausner <wiz(a)NetBSD.org> --- drivers/gpu/drm/amd/include/atombios.h | 20 ++++++++++---------- drivers/gpu/drm/amd/include/atomfirmware.h | 4 ++-- drivers/gpu/drm/radeon/atombios.h | 8 ++++---- drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 2 +- 4 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h … [View More]index 8ba21747b40a..2f124c1a9c8e 100644 --- a/drivers/gpu/drm/amd/include/atombios.h +++ b/drivers/gpu/drm/amd/include/atombios.h @@ -1987,9 +1987,9 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V6 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 -#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) +#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1) #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 -#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) +#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4) #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 @@ -2420,7 +2420,7 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 { USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below + UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx definitions below UCHAR ucAction; // 0: turn off encoder // 1: setup and turn on encoder UCHAR ucTruncate; // bit0=0: Disable truncate @@ -2873,7 +2873,7 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO // Structures used in FirmwareInfoTable /****************************************************************************/ -// usBIOSCapability Defintion: +// usBIOSCapability Definition: // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; @@ -4213,7 +4213,7 @@ typedef struct _ATOM_DPCD_INFO #define ATOM_DPCD_MAX_LANE_MASK 0x1F /**************************************************************************/ -// VRAM usage and their defintions +// VRAM usage and their definitions // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. @@ -6753,7 +6753,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 -//Byte aligned defintion for BIOS usage +//Byte aligned definition for BIOS usage #define ATOM_S0_CRT1_MONOb0 0x01 #define ATOM_S0_CRT1_COLORb0 0x02 #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) @@ -6819,7 +6819,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L -//Byte aligned defintion for BIOS usage +//Byte aligned definition for BIOS usage #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 @@ -6871,7 +6871,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 -//Byte aligned defintion for BIOS usage +//Byte aligned definition for BIOS usage #define ATOM_S3_CRT1_ACTIVEb0 0x01 #define ATOM_S3_LCD1_ACTIVEb0 0x02 #define ATOM_S3_TV1_ACTIVEb0 0x04 @@ -6910,7 +6910,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L #define ATOM_S4_LCD1_REFRESH_SHIFT 8 -//Byte aligned defintion for BIOS usage +//Byte aligned definition for BIOS usage #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 @@ -6989,7 +6989,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L -//Byte aligned defintion for BIOS usage +//Byte aligned definition for BIOS usage #define ATOM_S6_DEVICE_CHANGEb0 0x01 #define ATOM_S6_SCALER_CHANGEb0 0x02 #define ATOM_S6_LID_CHANGEb0 0x04 diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 70146518174c..f9dcf67b3517 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -445,7 +445,7 @@ struct atom_dtd_format uint8_t refreshrate; }; -/* atom_dtd_format.modemiscinfo defintion */ +/* atom_dtd_format.modemiscinfo definition */ enum atom_dtd_format_modemiscinfo{ ATOM_HSYNC_POLARITY = 0x0002, ATOM_VSYNC_POLARITY = 0x0004, @@ -597,7 +597,7 @@ struct lcd_info_v2_1 uint32_t reserved1[8]; }; -/* lcd_info_v2_1.panel_misc defintion */ +/* lcd_info_v2_1.panel_misc definition */ enum atom_lcd_info_panel_misc{ ATOM_PANEL_MISC_FPDI =0x0002, }; diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h index 4b86e8b45009..e118d4bec807 100644 --- a/drivers/gpu/drm/radeon/atombios.h +++ b/drivers/gpu/drm/radeon/atombios.h @@ -1711,9 +1711,9 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V6 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 -#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) +#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1) #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 -#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) +#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4) #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 @@ -2036,7 +2036,7 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 { USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below + UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx definitions below UCHAR ucAction; // 0: turn off encoder // 1: setup and turn on encoder UCHAR ucTruncate; // bit0=0: Disable truncate @@ -3732,7 +3732,7 @@ typedef struct _ATOM_DPCD_INFO #define ATOM_DPCD_MAX_LANE_MASK 0x1F /**************************************************************************/ -// VRAM usage and their defintions +// VRAM usage and their definitions // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index f47d5710cc95..5195c19d25a4 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -2016,7 +2016,7 @@ void vmw_disable_vblank(struct drm_device *dev, unsigned int pipe) * plugin and generate DRM uevent * @dev_priv: device private * @num_rects: number of drm_rect in rects - * @rects: toplogy to update + * @rects: topology to update */ static int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned int num_rects, struct drm_rect *rects) -- 2.21.0 [View Less]

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[PATCH v1 1/3] arm64: dts: mt8183: Add gce setting in display node
by Bibby Hsieh 17 Feb '20

17 Feb '20

In order to use GCE function, we need add some information into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events). Signed-off-by: Bibby Hsieh <bibby.hsieh(a)mediatek.com> Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> --- This patch depends on ptach: [RESEND,v6,02/17] arm64: dts: add display nodes for mt8183 https://patchwork.kernel.org/patch/11316277/ --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+… [View More]) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index be4428c92f35..8b522b039a37 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/mt8183-power.h> +#include <dt-bindings/gce/mt8183-gce.h> #include "mt8183-pinfunc.h" / { @@ -664,6 +665,9 @@ reg = <0 0x14000000 0 0x1000>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; #clock-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; ovl0: ovl@14008000 { @@ -672,6 +676,7 @@ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; }; ovl_2l0: ovl@14009000 { @@ -680,6 +685,7 @@ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; ovl_2l1: ovl@1400a000 { @@ -688,6 +694,7 @@ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; rdma0: rdma@1400b000 { @@ -697,6 +704,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_RDMA0>; mediatek,rdma_fifo_size = <5120>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; rdma1: rdma@1400c000 { @@ -706,6 +714,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_RDMA1>; mediatek,rdma_fifo_size = <2048>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; color0: color@1400e000 { @@ -715,6 +724,7 @@ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; ccorr0: ccorr@1400f000 { @@ -723,6 +733,7 @@ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; aal0: aal@14010000 { @@ -732,6 +743,7 @@ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; }; gamma0: gamma@14011000 { @@ -741,6 +753,7 @@ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; dither0: dither@14012000 { @@ -749,6 +762,7 @@ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; mutex: mutex@14016000 { @@ -756,6 +770,8 @@ reg = <0 0x14016000 0 0x1000>; interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, + <CMDQ_EVENT_MUTEX_STREAM_DONE1>; }; smi_common: smi@14019000 { -- 2.18.0 [View Less]

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nouveau-fixes 5.6
by Ben Skeggs 17 Feb '20

17 Feb '20

Hey, Nothing major here, another TU1xx modesetting fix, and hooking up ACR/GR support on TU11x now that NVIDIA have made the firmware available. Thanks, Ben. The following changes since commit 137c4ba7163ad9d5696b9fde78b1c0898a9c115b: drm/nouveau/kms/gv100-: avoid sending a core update until the first modeset (2020-02-03 21:36:54 +1000) are available in the Git repository at: git://github.com/skeggsb/linux linux-5.6 for you to fetch changes up to … [View More]

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dri-devel February 2020