dri-devel June 2020

dri-devel@lists.freedesktop.org

315 participants
731 discussions

[PATCH v3 00/22] drm: mxsfb: Add i.MX7 support
by Laurent Pinchart 17 Jun '20

17 Jun '20

Hello, This patch series adds i.MX7 support to the mxsfb driver. The eLCDIF instance found in the i.MX7 is backward-compatible with the already supported LCDC v4, but has extended features amongst which the most notable one is a second plane. The first 10 patches (01/22 to 10/22) contain miscellaneous cleanups and refactoring to prepare for what is to come. Patch 11/22 starts the real work with removal of the DRM simple display pipeline helper, as it doesn't support multiple planes. The next patch (12/22) is an additional cleanup. Patches 13/22 to 15/22 fix vblank handling that I found to be broken when testing on my device. Patch 16/22 then performs an additional small cleanup, and patch 17/22 starts official support for i.MX7 by mentioning it in Kconfig. Patch 18/22 adds a new device model for the i.MX6SX and i.MX7 eLCDIF. After three additional cleanups in patches 19/22 to 21/22, patch 22/22 finally adds support for the second plane. The second plane suffers from an issue whose root cause hasn't been found, which results in the first 64 bytes of the first line to contain data of unknown origin. Help from NXP to diagnose this issue would be useful and appreciated. Compared to v2, the patches incorporate various review feedback, without major modifications. See individual changelogs for details. The code is based on drm-misc-next and has been tested on an i.MX7D platform with a DPI panel. Stefan, the series has been fully reviewed, could you merge it ? Laurent Pinchart (22): drm: mxsfb: Remove fbdev leftovers drm: mxsfb: Use drm_panel_bridge drm: mxsfb: Use BIT() macro to define register bitfields drm: mxsfb: Remove unused macros from mxsfb_regs.h drm: mxsfb: Clarify format and bus width configuration drm: mxsfb: Pass mxsfb_drm_private pointer to mxsfb_reset_block() drm: mxsfb: Use LCDC_CTRL register name explicitly drm: mxsfb: Remove register definitions from mxsfb_crtc.c drm: mxsfb: Remove unneeded includes drm: mxsfb: Rename mxsfb_crtc.c to mxsfb_kms.c drm: mxsfb: Stop using DRM simple display pipeline helper drm: mxsfb: Move vblank event arm to CRTC .atomic_flush() drm: mxsfb: Don't touch AXI clock in IRQ context drm: mxsfb: Enable vblank handling drm: mxsfb: Remove mxsfb_devdata unused fields drm: mxsfb: Add i.MX7 and i.MX8M to the list of supported SoCs in Kconfig drm: mxsfb: Update internal IP version number for i.MX6SX drm: mxsfb: Drop non-OF support drm: mxsfb: Turn mxsfb_set_pixel_fmt() into a void function drm: mxsfb: Merge mxsfb_set_pixel_fmt() and mxsfb_set_bus_fmt() drm: mxsfb: Remove unnecessary spaces after tab drm: mxsfb: Support the alpha plane drivers/gpu/drm/mxsfb/Kconfig | 8 +- drivers/gpu/drm/mxsfb/Makefile | 2 +- drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 343 ----------------- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 249 ++++--------- drivers/gpu/drm/mxsfb/mxsfb_drv.h | 42 ++- drivers/gpu/drm/mxsfb/mxsfb_kms.c | 565 +++++++++++++++++++++++++++++ drivers/gpu/drm/mxsfb/mxsfb_out.c | 99 ----- drivers/gpu/drm/mxsfb/mxsfb_regs.h | 103 +++--- 8 files changed, 733 insertions(+), 678 deletions(-) delete mode 100644 drivers/gpu/drm/mxsfb/mxsfb_crtc.c create mode 100644 drivers/gpu/drm/mxsfb/mxsfb_kms.c delete mode 100644 drivers/gpu/drm/mxsfb/mxsfb_out.c -- Regards, Laurent Pinchart

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[PATCH 0/5] Suspend and resume fixes for omapdrm pdata removal
by Tony Lindgren 17 Jun '20

17 Jun '20

Hi all, Recent omapdrm related changes to drop legacy platform data caused a suspend and resume regression. I must have only tested suspend and resume only with the changes preparing to drop the platform data, but looks like I forgot to test suspend after dropping the platform data. There seem to be other longer term DSS regressions remaining too. Looks like at least panel-simple currently does not probe. It fails with "panel-simple display: Reject override mode: panel has a fixed mode". I think the solution there is to drop the board specific panel-timing related dts lines, but that still seems to be pending. Anyways, no luck getting the LCD enabled on am437x-sk-evm with v5.6 or v5.7-rc kernels. Regards, Tony Tony Lindgren (5): drm/omap: Fix suspend resume regression after platform data removal bus: ti-sysc: Use optional clocks on for enable and wait for softreset bit bus: ti-sysc: Ignore clockactivity unless specified as a quirk bus: ti-sysc: Fix uninitialized framedonetv_irq ARM: OMAP2+: Fix legacy mode dss_reset arch/arm/mach-omap2/omap_hwmod.c | 2 +- drivers/bus/ti-sysc.c | 93 ++++++++++++++++++------ drivers/gpu/drm/omapdrm/dss/dispc.c | 6 +- drivers/gpu/drm/omapdrm/dss/dsi.c | 6 +- drivers/gpu/drm/omapdrm/dss/dss.c | 6 +- drivers/gpu/drm/omapdrm/dss/venc.c | 6 +- drivers/gpu/drm/omapdrm/omap_dmm_tiler.c | 4 +- 7 files changed, 79 insertions(+), 44 deletions(-) -- 2.26.2

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[PATCH v5 0/2] mfd: Add ENE KB3930 Embedded Controller driver
by Lubomir Rintel 17 Jun '20

17 Jun '20

Hi, please consider applying the patches chained to this message. It's the fifth version of the driver for the ENE KB3930 Embedded Controller. This version is essentially a resend of v4. The only actual change is the addition of the Rob's Reviewed-by tag which I failed to do previously. Detailed change logs are in the individual patch descriptions. Thanks, Lubo

2 4

[PATCH] drm/rockchip: Add per-pixel alpha support for the PX30 VOP
by Paul Kocialkowski 17 Jun '20

17 Jun '20

Compared to its predecessors, the PX30 VOP has a different register layout for enabling per-pixel alpha. Instead of src_alpha_ctl and dst_alpha_ctl, there is a single alpha control register. This register takes some fields from src_alpha_ctl, but with a different layout. Add support for the required fields to the PX30 VOP window descriptions, which makes per-pixel-alpha formats behave correctly. Signed-off-by: Paul Kocialkowski <paul.kocialkowski(a)bootlin.com> --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++++ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 3 +++ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 9 +++++++++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index d04b3492bdac..ac1b1923c4bc 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -906,6 +906,10 @@ static void vop_plane_atomic_update(struct drm_plane *plane, SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | SRC_FACTOR_M0(ALPHA_ONE); VOP_WIN_SET(vop, win, src_alpha_ctl, val); + + VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); + VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); + VOP_WIN_SET(vop, win, alpha_en, 1); } else { VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 0b3d18c457b2..562b127d120b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -151,6 +151,9 @@ struct vop_win_phy { struct vop_reg dst_alpha_ctl; struct vop_reg src_alpha_ctl; + struct vop_reg alpha_pre_mul; + struct vop_reg alpha_mode; + struct vop_reg alpha_en; struct vop_reg channel; }; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 7a9d979c8d5d..67bb2625db68 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -244,6 +244,9 @@ static const struct vop_win_phy px30_win0_data = { .uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0), .yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0), .uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16), + .alpha_pre_mul = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 2), + .alpha_mode = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 1), + .alpha_en = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 0), }; static const struct vop_win_phy px30_win1_data = { @@ -256,6 +259,9 @@ static const struct vop_win_phy px30_win1_data = { .dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0), .yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0), .yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0), + .alpha_pre_mul = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 2), + .alpha_mode = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 1), + .alpha_en = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 0), }; static const struct vop_win_phy px30_win2_data = { @@ -269,6 +275,9 @@ static const struct vop_win_phy px30_win2_data = { .dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0), .yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0), .yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0), + .alpha_pre_mul = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 2), + .alpha_mode = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 1), + .alpha_en = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 0), }; static const struct vop_win_data px30_vop_big_win_data[] = { -- 2.26.0

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[PATCH][next] drm/i915/selftests: fix spelling mistake "submited" -> "submitted"
by Colin King 17 Jun '20

17 Jun '20

From: Colin Ian King <colin.king(a)canonical.com> There is a spelling mistake in a pr_err message. Fix it. Signed-off-by: Colin Ian King <colin.king(a)canonical.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index b8b7b91019f4..547edf3d902b 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -482,7 +482,7 @@ static int live_unlite_ring(void *arg) err = wait_for_submit(engine, rq, HZ / 2); i915_request_put(rq); if (err) { - pr_err("%s: preemption request was not submited\n", + pr_err("%s: preemption request was not submitted\n", engine->name); err = -ETIME; } -- 2.27.0.rc0

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[PATCH 0/3] ast cleanups
by Thomas Zimmermann 17 Jun '20

17 Jun '20

Ast still has to be converted to managed initialization, and embed the DRM device in the ast structure. In preparation of these changes, add some cleanups to the driver. Tested on ast HW. Thomas Zimmermann (3): drm/ast: Remove unused code paths for AST 1180 drm/ast: Upcast from DRM device to ast structure via to_ast_private() drm/ast: Use per-device logging macros drivers/gpu/drm/ast/ast_dp501.c | 24 +++---- drivers/gpu/drm/ast/ast_drv.c | 1 - drivers/gpu/drm/ast/ast_drv.h | 7 +- drivers/gpu/drm/ast/ast_main.c | 115 +++++++++++++++----------------- drivers/gpu/drm/ast/ast_mode.c | 59 +++++++--------- drivers/gpu/drm/ast/ast_post.c | 28 ++++---- drivers/gpu/drm/ast/ast_ttm.c | 2 +- 7 files changed, 107 insertions(+), 129 deletions(-) -- 2.26.2

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[PATCH] gpu/drm: remove drm_modeset_lock protection for drm_error
by Bernard Zhao 17 Jun '20

17 Jun '20

In function drm_atomic_helper_shutdown, maybe there is no need to protect DRM_ERROR log in DRM_MODESET_LOCK_ALL_BEGIN & DRM_MODESET_LOCK_ALL_END. This change is to make code run a bit fast. Signed-off-by: Bernard Zhao <bernard(a)vivo.com> --- drivers/gpu/drm/drm_atomic_helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 85d163f16801..8902fd6316fc 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -3100,12 +3100,10 @@ void drm_atomic_helper_shutdown(struct drm_device *dev) int ret; DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); - ret = drm_atomic_helper_disable_all(dev, &ctx); + DRM_MODESET_LOCK_ALL_END(ctx, ret); if (ret) DRM_ERROR("Disabling all crtc's during unload failed with %i\n", ret); - - DRM_MODESET_LOCK_ALL_END(ctx, ret); } EXPORT_SYMBOL(drm_atomic_helper_shutdown); -- 2.17.1

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[Bug 208209] New: [amdgpu] driver crash -- enable_link_dp -- RX 570
by bugzilla-daemon＠bugzilla.kernel.org 17 Jun '20

17 Jun '20

https://bugzilla.kernel.org/show_bug.cgi?id=208209 Bug ID: 208209 Summary: [amdgpu] driver crash -- enable_link_dp -- RX 570 Product: Drivers Version: 2.5 Kernel Version: 5.3.0-55-generic Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: max.bruce12(a)gmail.com Regression: No This crash was nonfatal to the system, but seems to break video playback. Happens randomly. Let me know if more information needed. Dmesg log: [901929.410695] WARNING: CPU: 11 PID: 123042 at drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1720 decide_link_settings+0x107/0x270 [amdgpu] [901929.410696] Modules linked in: ufs qnx4 hfsplus hfs minix ntfs msdos jfs xfs cpuid rfcomm xt_CHECKSUM xt_MASQUERADE xt_conntrack ipt_REJECT nf_reject_ipv4 xt_tcpudp ip6table_mangle ip6table_nat iptable_mangle iptable_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 ebtable_filter ebtables ip6table_filter ip6_tables bridge stp llc rpcsec_gss_krb5 auth_rpcgss edac_mce_amd kvm_amd ashmem_linux(CE) binder_linux iptable_filter bpfilter cmac bnep binfmt_misc input_leds snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio snd_hda_codec_hdmi snd_hda_intel snd_intel_dspcfg btusb btrtl snd_hda_codec btbcm snd_hda_core btintel snd_hwdep snd_pcm bluetooth snd_seq_midi snd_seq_midi_event ecdh_generic ecc kvm snd_rawmidi irqbypass snd_seq iwlmvm snd_seq_device mac80211 snd_timer libarc4 iwlwifi wmi_bmof snd cfg80211 soundcore k10temp ccp mac_hid sch_fq_codel parport_pc ppdev lp parport ip_tables x_tables autofs4 btrfs zstd_compress hid_logitech_hidpp hid_logitech_dj dm_crypt raid10 raid456 [901929.410732] async_raid6_recov async_memcpy async_pq async_xor async_tx xor hid_generic usbhid hid raid6_pq libcrc32c raid1 raid0 multipath linear nfsv4 nfsv3 nfs_acl nfs lockd grace sunrpc fscache bonding amdgpu crct10dif_pclmul amd_iommu_v2 crc32_pclmul gpu_sched ghash_clmulni_intel ttm aesni_intel drm_kms_helper aes_x86_64 syscopyarea sysfillrect crypto_simd igb sysimgblt nvme cryptd fb_sys_fops dca i2c_algo_bit mxm_wmi drm glue_helper nvme_core ahci i2c_piix4 libahci gpio_amdpt wmi gpio_generic [901929.410759] CPU: 11 PID: 123042 Comm: kworker/11:0 Kdump: loaded Tainted: G WC E 5.3.0-55-generic #49-Ubuntu [901929.410760] Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./X399 Taichi, BIOS P3.50 12/24/2018 [901929.410865] Workqueue: events dm_irq_work_func [amdgpu] [901929.410965] RIP: 0010:decide_link_settings+0x107/0x270 [amdgpu] [901929.410968] Code: c0 83 fa 0e 77 07 8b 04 95 80 c6 73 c0 89 44 24 14 c7 44 24 10 01 00 00 00 39 43 5c 73 bd 48 c7 c7 e8 d3 77 c0 e8 cc 9c a7 c0 <0f> 0b 83 7b 58 00 0f 85 7d 50 02 00 e9 6a 50 02 00 80 bb e4 00 00 [901929.410969] RSP: 0018:ffffc900165777d0 EFLAGS: 00010246 [901929.410971] RAX: 0000000000000024 RBX: ffff888849ecc400 RCX: 0000000000000000 [901929.410972] RDX: 0000000000000000 RSI: ffff88905ead7448 RDI: ffff88905ead7448 [901929.410973] RBP: ffffc90016577818 R08: ffff88905ead7448 R09: 0000000000000004 [901929.410974] R10: 0000000000000000 R11: 0000000000000001 R12: ffffc900165777e0 [901929.410975] R13: 0000000000c34830 R14: ffffc90016577838 R15: 0000000000000000 [901929.410977] FS: 0000000000000000(0000) GS:ffff88905eac0000(0000) knlGS:0000000000000000 [901929.410978] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [901929.410979] CR2: 00005564ed8d0730 CR3: 0000001016bb0000 CR4: 00000000003406e0 [901929.410980] Call Trace: [901929.411082] enable_link_dp+0x51/0x260 [amdgpu] [901929.411180] core_link_enable_stream+0x63c/0x8f0 [amdgpu] [901929.411284] ? set_pixel_encoding.isra.0+0x6d/0x160 [amdgpu] [901929.411381] dce110_apply_ctx_to_hw+0x501/0x580 [amdgpu] [901929.411479] ? dce110_apply_ctx_to_hw+0x501/0x580 [amdgpu] [901929.411552] dc_commit_state_no_check+0x228/0x580 [amdgpu] [901929.411624] dc_commit_state+0x96/0xb0 [amdgpu] [901929.411699] amdgpu_dm_atomic_commit_tail+0x3bf/0xfb0 [amdgpu] [901929.411768] ? amdgpu_cgs_read_register+0x14/0x20 [amdgpu] [901929.411838] ? dm_read_reg_func+0x25/0x90 [amdgpu] [901929.411844] ? _cond_resched+0x19/0x30 [901929.411894] ? amdgpu_bo_pin_restricted+0x61/0x2a0 [amdgpu] [901929.411969] ? dm_plane_helper_prepare_fb+0x1b3/0x290 [amdgpu] [901929.411972] ? _cond_resched+0x19/0x30 [901929.411973] ? wait_for_completion_timeout+0x3a/0x120 [901929.411975] ? wait_for_completion_interruptible+0x37/0x160 [901929.411983] commit_tail+0x41/0x70 [drm_kms_helper] [901929.411990] ? commit_tail+0x41/0x70 [drm_kms_helper] [901929.411997] drm_atomic_helper_commit+0x118/0x120 [drm_kms_helper] [901929.412070] amdgpu_dm_atomic_commit+0xb1/0xf0 [amdgpu] [901929.412085] drm_atomic_commit+0x4a/0x50 [drm] [901929.412158] dm_restore_drm_connector_state+0xe9/0x140 [amdgpu] [901929.412231] handle_hpd_irq+0xc1/0x100 [amdgpu] [901929.412304] dm_irq_work_func+0x4e/0x60 [amdgpu] [901929.412308] process_one_work+0x1db/0x380 [901929.412310] worker_thread+0x4d/0x400 [901929.412313] kthread+0x104/0x140 [901929.412314] ? process_one_work+0x380/0x380 [901929.412316] ? kthread_park+0x80/0x80 [901929.412317] ret_from_fork+0x22/0x40 [901929.412320] ---[ end trace ec78da1ed7d7751b ]--- -- You are receiving this mail because: You are watching the assignee of the bug.

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[PATCH v3 0/5] Add support for PinePhone LCD panel
by Ondrej Jirman 17 Jun '20

17 Jun '20

This patchset adds support for the LCD panel of PinePhone. The first 3 patches are for the panel itself, and the last 2 patches are for enabling it on PinePhone. I've tested this on PinePhone 1.0 and 1.2. Please take a look. thank you and regards, Ondrej Jirman Changes in v3: - Panel driver renamed to the name of the LCD controller - Re-organize the driver slightly to more easily support more panels based on the same controller. - Add patch to enable the touchscreen to complete the LCD support on PinePhone. - Dropped the "DSI fix" patch (the driver seems to work for me without it) - Improved brightness levels handling: - PinePhone 1.0 uses default levels generated by the driver - On PinePhone 1.1 duty cycles < 20% lead to black screen, so default levels can't be used. Martijn Braam came up with a list of duty cycle values that lead to perception of linear brigtness level <-> light intensity on PinePhone 1.1 - There was some feedback on v2 about this being similar to st7701. It's only similar in name. Most of the "user commands" are different, so I opted to keep this in a new driver instead of creating st770x. Anyone who likes to check the differences, here are datasheets: - https://megous.com/dl/tmp/ST7703_DS_v01_20160128.pdf - https://megous.com/dl/tmp/ST7701.pdf Changes in v2: - DT Example fix. - DT Format fix. - Raised copyright info to 2020. - Sort panel operation functions. - Sort inclusion. -- For phone owners: -- There's an open question on how to set the backlight brightness values on post 1.0 revision phone, since lower duty cycles (< 10-20%) lead to backlight being black. It would be nice if more people can test the various backlight levels on 1.1 and 1.2 revision with this change in dts: brightness-levels = <0 1000>; num-interpolated-steps = <1000>; and report at what brightness level the backlight turns on. So far it seems this has a wide range. Lowest useable duty cycle for me is ~7% on 1.2 and for Martijn ~20% on 1.1. Icenowy Zheng (4): dt-bindings: vendor-prefixes: Add Xingbangda dt-bindings: panel: Add binding for Xingbangda XBD599 panel drm: panel: Add Xingbangda XBD599 panel (ST7703 controller) arm64: dts: sun50i-a64-pinephone: Enable LCD support on PinePhone Ondrej Jirman (1): arm64: dts: sun50i-a64-pinephone: Add touchscreen support .../display/panel/sitronix,st7703.yaml | 63 +++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + .../allwinner/sun50i-a64-pinephone-1.1.dts | 19 + .../dts/allwinner/sun50i-a64-pinephone.dtsi | 54 +++ drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-sitronix-st7703.c | 386 ++++++++++++++++++ 7 files changed, 535 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/sitronix,st7703.yaml create mode 100644 drivers/gpu/drm/panel/panel-sitronix-st7703.c -- 2.26.2

6 12

[PATCH v3 00/15] drm/mgag200: Convert to atomic modesetting
by Thomas Zimmermann 17 Jun '20

17 Jun '20

This patchset converts mgag200 to atomic modesetting. It uses simple KMS helpers and SHMEM. I'm posting v3 mostly for reference. These patches will land soon if no one objects. Patch 1 removes cursor support. The HW cursor is not usable with the way universal planes work. Patches 2 to 11 untangle the existing modesetting code into smaller functions. Specifically, mode setting and plane updates are being separated from each other. Patch 12 to 14 convert mgag200 to simple KMS helpers and enables atomic mode setting. Atomically switching plane framebuffers, requires either source or target buffer to be located at a non-0 offet. As some HW revisions seem to require a framebuffer offset of 0 within the video memory, they do not work with atomic modesetting. To resolve this problem, patch 15 converts mgag200 from VRAM helpers to SHMEM helpers. During plane updates, the content of the SHMEM BO is memcpy'd to VRAM. From my observation, performance is not nuch different from the original code. The patchset has been tested on MGA G200EH hardware. v3: * update commit messages * remove unused defines v2: * rebase patchset * replace uint{8,32}_t with u{8,32} through-out patchset * define additional register constants * use helper functions around bpp-shift computations * split conversion patch * keep busy-waiting in DPMS code * cleanups Thomas Zimmermann (15): drm/mgag200: Remove HW cursor drm/mgag200: Clean up mga_set_start_address() drm/mgag200: Clean up mga_crtc_do_set_base() drm/mgag200: Move mode-setting code into separate helper function drm/mgag200: Split MISC register update into PLL selection, SYNC and I/O drm/mgag200: Update mode registers after plane registers drm/mgag200: Set pitch in a separate helper function drm/mgag200: Set primary plane's format in separate helper function drm/mgag200: Move TAGFIFO reset into separate function drm/mgag200: Move hiprilvl setting into separate functions drm/mgag200: Move register initialization into separate function drm/mgag200: Remove out-commented suspend/resume helpers drm/mgag200: Use simple-display data structures drm/mgag200: Convert to simple KMS helper drm/mgag200: Replace VRAM helpers with SHMEM helpers drivers/gpu/drm/mgag200/Kconfig | 4 +- drivers/gpu/drm/mgag200/Makefile | 2 +- drivers/gpu/drm/mgag200/mgag200_drv.c | 51 +- drivers/gpu/drm/mgag200/mgag200_drv.h | 45 +- drivers/gpu/drm/mgag200/mgag200_main.c | 5 - drivers/gpu/drm/mgag200/mgag200_mode.c | 871 ++++++++++++++----------- drivers/gpu/drm/mgag200/mgag200_reg.h | 11 +- drivers/gpu/drm/mgag200/mgag200_ttm.c | 28 +- 8 files changed, 528 insertions(+), 489 deletions(-) -- 2.26.2

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dri-devel June 2020