dri-devel October 2021

dri-devel@lists.freedesktop.org

347 participants
825 discussions

[PATCH v2] drm/edid: In connector_bad_edid() cap num_of_ext by num_blocks read
by Douglas Anderson 06 Oct '21

06 Oct '21

In commit e11f5bd8228f ("drm: Add support for DP 1.4 Compliance edid corruption test") the function connector_bad_edid() started assuming that the memory for the EDID passed to it was big enough to hold `edid[0x7e] + 1` blocks of data (1 extra for the base block). It completely ignored the fact that the function was passed `num_blocks` which indicated how much memory had been allocated for the EDID. Let's fix this by adding a bounds check. This is important for handling the case where there's an error in the first block of the EDID. In that case we will call connector_bad_edid() without having re-allocated memory based on `edid[0x7e]`. Fixes: e11f5bd8228f ("drm: Add support for DP 1.4 Compliance edid corruption test") Reported-by: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Reviewed-by: Ville Syrjälä <ville.syrjala(a)linux.intel.com> --- This problem report came up in the context of a patch I sent out [1] and this is my attempt at a fix. The problem predates my patch, though. I don't personally know anything about DP compliance testing and what should be happening here, nor do I apparently have any hardware that actually reports a bad EDID. Thus this is just compile tested. I'm hoping that someone here can test this and make sure it seems OK to them. Changes in v2: - Added a comment/changed math to help make it easier to grok. drivers/gpu/drm/drm_edid.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 9c9463ec5465..0383d97c306f 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1840,11 +1840,20 @@ static void connector_bad_edid(struct drm_connector *connector, u8 *edid, int num_blocks) { int i; - u8 num_of_ext = edid[0x7e]; + u8 last_block; + + /* + * 0x7e in the EDID is the number of extension blocks. The EDID + * is 1 (base block) + num_ext_blocks big. That means we can think + * of 0x7e in the EDID of the _index_ of the last block in the + * combined chunk of memory. + */ + last_block = edid[0x7e]; /* Calculate real checksum for the last edid extension block data */ - connector->real_edid_checksum = - drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); + if (last_block < num_blocks) + connector->real_edid_checksum = + drm_edid_block_checksum(edid + last_block * EDID_LENGTH); if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) return; -- 2.33.0.800.g4c38ced690-goog

3 2

[PATCH i-g-t 1/1] tests/i915_pxp: Use ioctl_wrapper for DRM_IOCTL_PRIME_HANDLE_TO_FD
by Alan Previn 06 Oct '21

06 Oct '21

Replace private helper with call to ioctl_wrapper for DRM_IOCTL_PRIME_HANDLE_TO_FD. Signed-off-by: Alan Previn <alan.previn.teres.alexis(a)intel.com> --- tests/i915/gem_pxp.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c index 79040165..0430f4b8 100644 --- a/tests/i915/gem_pxp.c +++ b/tests/i915/gem_pxp.c @@ -622,23 +622,6 @@ static void test_render_pxp_protsrc_to_protdest(int i915) buf_ops_destroy(bops); } -static int export_handle(int fd, uint32_t handle, int *outfd) -{ - struct drm_prime_handle args; - int ret; - - args.handle = handle; - args.flags = DRM_CLOEXEC; - args.fd = -1; - - ret = drmIoctl(fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &args); - if (ret) - ret = errno; - *outfd = args.fd; - - return ret; -} - static void test_pxp_dmabuffshare_refcnt(void) { uint32_t ctx[2], sbo[2], dbo[2]; @@ -659,8 +642,7 @@ static void test_pxp_dmabuffshare_refcnt(void) dbo[0] = alloc_and_fill_dest_buff(fd[0], true, TSTSURF_SIZE, TSTSURF_INITCOLOR1); } else { - ret = export_handle(fd[0], dbo[0], &dmabuf_fd); - igt_assert(ret == 0); + dmabuf_fd = prime_handle_to_fd(fd[0], dbo[0]); dbo[1] = prime_fd_to_handle(fd[1], dmabuf_fd); igt_assert(dbo[1]); } -- 2.25.1

3 2

[pull] amdgpu, amdkfd drm-fixes-5.15
by Alex Deucher 06 Oct '21

06 Oct '21

Hi Dave, Daniel, Fixes for 5.15. The following changes since commit 9e1ff307c779ce1f0f810c7ecce3d95bbae40896: Linux 5.15-rc4 (2021-10-03 14:08:47 -0700) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-5.15-2021-10-06 for you to fetch changes up to 5a1fef027846e7635b9d320b2cc0b416fd11a3be: drm/amd/display: Fix detection of 4 lane for DPALT (2021-10-06 16:14:17 -0400) ---------------------------------------------------------------- amd-drm-fixes-5.15-2021-10-06: amdgpu: - DCN 3.1 DP alt mode fixes - S0ix gfxoff fix - Fix DRM_AMD_DC_SI dependencies - PCIe DPC handling fix - DCN 3.1 scaling fix - Documentation fix amdkfd: - Fix potential memory leak - IOMMUv2 init fixes ---------------------------------------------------------------- Alex Deucher (2): Documentation/gpu: remove spurious "+" in amdgpu.rst drm/amdgpu/display: fix dependencies for DRM_AMD_DC_SI George Shen (1): drm/amd/display: Skip override for preferred link settings during link training Guchun Chen (1): drm/amdgpu: handle the case of pci_channel_io_frozen only in amdgpu_pci_resume Hansen (1): drm/amd/display: Fix detection of 4 lane for DPALT Jude Shih (1): drm/amd/display: USB4 bring up set correct address Lang Yu (1): drm/amdkfd: fix a potential ttm->sg memory leak Lijo Lazar (1): drm/amdgpu: During s0ix don't wait to signal GFXOFF Liu, Zhan (2): drm/amd/display: Fix B0 USB-C DP Alt mode drm/amd/display: Fix DCN3 B0 DP Alt Mapping Nikola Cornij (1): drm/amd/display: Limit display scaling to up to 4k for DCN 3.1 Yifan Zhang (2): drm/amdkfd: remove redundant iommu cleanup code drm/amdgpu: init iommu after amdkfd device init Documentation/gpu/amdgpu.rst | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 14 ++++- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 8 +-- drivers/gpu/drm/amd/display/Kconfig | 2 + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 6 -- .../drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 1 + .../amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 66 +++++++++++++++++++++- .../amd/display/dc/dcn31/dcn31_dio_link_encoder.h | 14 ++++- .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 8 ++- drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 +- .../amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h | 27 +++++++++ 14 files changed, 142 insertions(+), 26 deletions(-)

1 0

[PATCH v2 2/3] dt-bindings: drm/bridge: ps8640: Add aux-bus child
by Philip Chen 06 Oct '21

06 Oct '21

dp-aux-bus.yaml says we can list an eDP panel as a child of an eDP controller node to represent the fact that the panel is connected to the controller's DP AUX bus. Let's add it to the ps8640 bindings. Signed-off-by: Philip Chen <philipchen(a)chromium.org> --- (no changes since v1) .../bindings/display/bridge/ps8640.yaml | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.yaml b/Documentation/devicetree/bindings/display/bridge/ps8640.yaml index fce82b605c8b..cdaf7a7a8f88 100644 --- a/Documentation/devicetree/bindings/display/bridge/ps8640.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ps8640.yaml @@ -40,6 +40,9 @@ properties: vdd33-supply: description: Regulator for 3.3V digital core power. + aux-bus: + $ref: /schemas/display/dp-aux-bus.yaml# + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -98,7 +101,21 @@ examples: reg = <1>; ps8640_out: endpoint { remote-endpoint = <&panel_in>; - }; + }; + }; + }; + + aux-bus { + panel { + compatible = "boe,nv133fhm-n62"; + power-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&ps8640_out>; + }; + }; }; }; }; -- 2.33.0.685.g46640cef36-goog

4 3

[PATCH] drm/tegra: Bump VIC/NVDEC clock rates to Fmax
by Mikko Perttunen 06 Oct '21

06 Oct '21

To get full performance out of these engines, bump their clock rates to maximum. In the future we may want something smarter but this should be fine for now. Signed-off-by: Mikko Perttunen <mperttunen(a)nvidia.com> --- drivers/gpu/drm/tegra/nvdec.c | 6 ++++++ drivers/gpu/drm/tegra/vic.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm/tegra/nvdec.c index c3b6fe7fb454..48c90e26e90a 100644 --- a/drivers/gpu/drm/tegra/nvdec.c +++ b/drivers/gpu/drm/tegra/nvdec.c @@ -374,6 +374,12 @@ static int nvdec_probe(struct platform_device *pdev) return PTR_ERR(nvdec->clk); } + err = clk_set_rate(nvdec->clk, ULONG_MAX); + if (err < 0) { + dev_err(&pdev->dev, "failed to set clock rate\n"); + return err; + } + err = of_property_read_u32(dev->of_node, "nvidia,host1x-class", &host_class); if (err < 0) host_class = HOST1X_CLASS_NVDEC; diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c index c02010ff2b7f..dec5e56f6780 100644 --- a/drivers/gpu/drm/tegra/vic.c +++ b/drivers/gpu/drm/tegra/vic.c @@ -441,6 +441,12 @@ static int vic_probe(struct platform_device *pdev) return PTR_ERR(vic->clk); } + err = clk_set_rate(vic->clk, ULONG_MAX); + if (err < 0) { + dev_err(&pdev->dev, "failed to set clock rate\n"); + return err; + } + if (!dev->pm_domain) { vic->rst = devm_reset_control_get(dev, "vic"); if (IS_ERR(vic->rst)) { -- 2.32.0

2 1

[PATCH] dt-bindings: display/bridge: sil, sii8620: Convert to YAML binding
by AngeloGioacchino Del Regno 06 Oct '21

06 Oct '21

Convert the Silicon Image SiI8620 MIPI-DSI to LVDS bridge documentation to YAML. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno(a)collabora.com> --- .../bindings/display/bridge/sil,sii8620.yaml | 96 +++++++++++++++++++ .../bindings/display/bridge/sil-sii8620.txt | 33 ------- 2 files changed, 96 insertions(+), 33 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/sil,sii8620.yaml delete mode 100644 Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt diff --git a/Documentation/devicetree/bindings/display/bridge/sil,sii8620.yaml b/Documentation/devicetree/bindings/display/bridge/sil,sii8620.yaml new file mode 100644 index 000000000000..4e32409eff17 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/sil,sii8620.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/sil,sii8620.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Image SiI8620 MIPI-DSI to LVDS bridge + +maintainers: + - Andrzej Hajda <a.hajda(a)samsung.com> + +description: | + The SiI8620 is bridge device which converts MIPI DSI or MIPI DPI to DP/eDP. + +properties: + compatible: + const: sil,sii8620 + + reg: + description: I2C address of the bridge + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xtal + + cvcc10-supply: + description: Digital Core Supply Voltage, 1.0V + + iovcc18-supply: + description: I/O voltage supply, 1.8V + + interrupts: + maxItems: 1 + + reset-gpios: + description: GPIO connected to the reset pin. + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for HDMI input + + required: + - port@0 + +required: + - compatible + - reg + - cvcc10-supply + - iovcc18-supply + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@39 { + compatible = "sil,sii8620"; + reg = <0x39>; + cvcc10-supply = <&ldo36_reg>; + iovcc18-supply = <&ldo34_reg>; + interrupt-parent = <&gpf0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpv7 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mhl_to_hdmi: endpoint { + remote-endpoint = <&hdmi_to_mhl>; + }; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt b/Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt deleted file mode 100644 index b05052f7d62f..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt +++ /dev/null @@ -1,33 +0,0 @@ -Silicon Image SiI8620 HDMI/MHL bridge bindings - -Required properties: - - compatible: "sil,sii8620" - - reg: i2c address of the bridge - - cvcc10-supply: Digital Core Supply Voltage (1.0V) - - iovcc18-supply: I/O Supply Voltage (1.8V) - - interrupts: interrupt specifier of INT pin - - reset-gpios: gpio specifier of RESET pin - - clocks, clock-names: specification and name of "xtal" clock - - video interfaces: Device node can contain video interface port - node for HDMI encoder according to [1]. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - sii8620@39 { - reg = <0x39>; - compatible = "sil,sii8620"; - cvcc10-supply = <&ldo36_reg>; - iovcc18-supply = <&ldo34_reg>; - interrupt-parent = <&gpf0>; - interrupts = <2 0>; - reset-gpio = <&gpv7 0 0>; - clocks = <&pmu_system_controller 0>; - clock-names = "xtal"; - - port { - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; - }; - }; - }; -- 2.33.0

1 0

[PATCH v1 0/5] mxsfb/nwl/panels: media bus format fixes
by Guido Günther 06 Oct '21

06 Oct '21

commit b776b0f00f24 ("drm: mxsfb: Use bus_format from the nearest bridge if present") added bus format probing to mxsfb this exposed several issues in the display stack as used on the Librem 5: The nwl bridge and the panels didn't bother to set any media bus formats and in that case mxsfb would not pick a reasonable default. This series aims to fix this. This series includes the patch from https://lore.kernel.org/dri-devel/YVLYh%2FSgBritG%2FRJ@qwark.sigxcpu.org/ with a `dev_warn` added. The patches are against 5.15-rc3. I've marked a single patch with a 'fixes' which is enough to unbreak the display stack in 5.15. Guido Günther (5): drm: mxsfb: Print failed bus format in hex drm: mxsfb: Set proper default bus format when using a bridge drm/bridge: nwl-dsi: Add atomic_get_input_bus_fmts drm/panel: mantix: Add media bus format drm/panel: st7703: Add media bus format drivers/gpu/drm/bridge/nwl-dsi.c | 35 +++++++++++++++++++ drivers/gpu/drm/mxsfb/mxsfb_kms.c | 7 +++- .../gpu/drm/panel/panel-mantix-mlaf057we51.c | 9 +++++ drivers/gpu/drm/panel/panel-sitronix-st7703.c | 8 +++++ 4 files changed, 58 insertions(+), 1 deletion(-) -- 2.33.0

3 7

AW: (EXT) Re: [PATCH 2/3] dt-bindings: drm/bridge: ti-sn65dsi83: Add vcc supply bindings
by Alexander Stein 06 Oct '21

06 Oct '21

On Wed, Oct 6, 2021 at 3:21 PM Rob Herring <robh+dt(a)kernel.org> wrote: > On Wed, Oct 6, 2021 at 2:47 AM Alexander Stein > <alexander.stein(a)ew.tq-group.com> wrote: > > > > Add a VCC regulator which needs to be enabled before the EN pin is > > released. > > > > Signed-off-by: Alexander Stein <alexander.stein(a)ew.tq-group.com> > > --- > > .../devicetree/bindings/display/bridge/ti,sn65dsi83.yaml | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml > b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml > > index 07b20383cbca..149cff3233c2 100644 > > --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml > > +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml > > @@ -32,6 +32,9 @@ properties: > > maxItems: 1 > > description: GPIO specifier for bridge_en pin (active high). > > > > + vcc-supply: > > + description: A 1.8V power supply (see regulator/regulator.yaml). > > + > > ports: > > $ref: /schemas/graph.yaml#/properties/ports > > > > @@ -94,6 +97,7 @@ required: > > - compatible > > - reg > > - enable-gpios > > + - vcc-supply > > You generally can't make added properties required unless all DT files > already had this property. It breaks compatibility. I agree, but AFAICS none of the in-kernel DT files uses this binding. I used 'grep -re "ti,sn65dsi8[34]" arch/*/boot/dts' to check. Only ti,sn65dsi86 is used on some qcom boards, but this is a completly different binding and driver. Best regards, Alexander

1 0

[PATCH 1/2] dma-buf: add dma_resv_for_each_fence v3
by Christian König 06 Oct '21

06 Oct '21

A simpler version of the iterator to be used when the dma_resv object is locked. v2: fix index check here as well v3: minor coding improvement, some documentation cleanup Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/dma-buf/dma-resv.c | 51 ++++++++++++++++++++++++++++++++++++++ include/linux/dma-resv.h | 20 +++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index a480af9581bd..2f98caa68ae5 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -423,6 +423,57 @@ struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor) } EXPORT_SYMBOL(dma_resv_iter_next_unlocked); +/** + * dma_resv_iter_first - first fence from a locked dma_resv object + * @cursor: cursor to record the current position + * + * Return the first fence in the dma_resv object while holding the + * &dma_resv.lock. + */ +struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor) +{ + struct dma_fence *fence; + + dma_resv_assert_held(cursor->obj); + + cursor->index = 0; + if (cursor->all_fences) + cursor->fences = dma_resv_shared_list(cursor->obj); + else + cursor->fences = NULL; + + fence = dma_resv_excl_fence(cursor->obj); + if (!fence) + fence = dma_resv_iter_next(cursor); + + cursor->is_restarted = true; + return fence; +} +EXPORT_SYMBOL_GPL(dma_resv_iter_first); + +/** + * dma_resv_iter_next - next fence from a locked dma_resv object + * @cursor: cursor to record the current position + * + * Return the next fences from the dma_resv object while holding the + * &dma_resv.lock. + */ +struct dma_fence *dma_resv_iter_next(struct dma_resv_iter *cursor) +{ + unsigned int idx; + + dma_resv_assert_held(cursor->obj); + + cursor->is_restarted = false; + if (!cursor->fences || cursor->index >= cursor->fences->shared_count) + return NULL; + + idx = cursor->index++; + return rcu_dereference_protected(cursor->fences->shared[idx], + dma_resv_held(cursor->obj)); +} +EXPORT_SYMBOL_GPL(dma_resv_iter_next); + /** * dma_resv_copy_fences - Copy all fences from src to dst. * @dst: the destination reservation object diff --git a/include/linux/dma-resv.h b/include/linux/dma-resv.h index 764138ad8583..491359cea54c 100644 --- a/include/linux/dma-resv.h +++ b/include/linux/dma-resv.h @@ -179,6 +179,8 @@ struct dma_resv_iter { struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter *cursor); struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor); +struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor); +struct dma_fence *dma_resv_iter_next(struct dma_resv_iter *cursor); /** * dma_resv_iter_begin - initialize a dma_resv_iter object @@ -244,6 +246,24 @@ static inline bool dma_resv_iter_is_restarted(struct dma_resv_iter *cursor) for (fence = dma_resv_iter_first_unlocked(cursor); \ fence; fence = dma_resv_iter_next_unlocked(cursor)) +/** + * dma_resv_for_each_fence - fence iterator + * @cursor: a struct dma_resv_iter pointer + * @obj: a dma_resv object pointer + * @all_fences: true if all fences should be returned + * @fence: the current fence + * + * Iterate over the fences in a struct dma_resv object while holding the + * &dma_resv.lock. @all_fences controls if the shared fences are returned as + * well. The cursor initialisation is part of the iterator and the fence stays + * valid as long as the lock is held and so no extra reference to the fence is + * taken. + */ +#define dma_resv_for_each_fence(cursor, obj, all_fences, fence) \ + for (dma_resv_iter_begin(cursor, obj, all_fences), \ + fence = dma_resv_iter_first(cursor); fence; \ + fence = dma_resv_iter_next(cursor)) + #define dma_resv_held(obj) lockdep_is_held(&(obj)->lock.base) #define dma_resv_assert_held(obj) lockdep_assert_held(&(obj)->lock.base) -- 2.25.1

2 3

[PATCH 00/11] drm/msm: Add Display Stream Compression Support
by Vinod Koul 06 Oct '21

06 Oct '21

Display Stream Compression (DSC) compresses the display stream in host which is later decoded by panel. This series enables this for Qualcomm msm driver. This was tested on Google Pixel3 phone which use LGE SW43408 panel. The changes include adding DT properties for DSC then hardware blocks support required in DPU1 driver and support in encoder. We also add support in DSI and introduce required topology changes. In order for panel to set the DSC parameters we add dsc in drm_panel and set it from the msm driver. Complete changes which enable this for Pixel3 along with panel driver (not part of this series) and DT changes can be found at: git.linaro.org/people/vinod.koul/kernel.git pixel/dsc_v1 Comments welcome! Changes since RFC: - Drop the DT binding patch as we derive the configuration from panel - Drop the drm api patch as we no longer need it (use pps drm api) - Fix comments raised by Dimitry - Add dsc parameters calculation from downstream Vinod Koul (11): drm/msm/dsi: add support for dsc data drm/msm/disp/dpu1: Add support for DSC drm/msm/disp/dpu1: Add support for DSC in pingpong block drm/msm/disp/dpu1: Add DSC support in RM drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog drm/msm/disp/dpu1: Add DSC support in hw_ctl drm/msm/disp/dpu1: Don't use DSC with mode_3d drm/msm/disp/dpu1: Add support for DSC in encoder drm/msm/disp/dpu1: Add support for DSC in topology drm/msm/dsi: Add support for DSC configuration drm/msm/dsi: Pass DSC params to drm_panel drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 158 +++++++++- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 + .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 22 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 221 ++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 77 +++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 + .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 32 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 + drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 + drivers/gpu/drm/msm/dsi/dsi_host.c | 289 +++++++++++++++++- drivers/gpu/drm/msm/msm_drv.h | 21 ++ include/drm/drm_panel.h | 7 + 20 files changed, 925 insertions(+), 14 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h -- 2.31.1

4 40

← Newer
1
...
67
68
69
70
71
72
73
...
83
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel October 2021