dri-devel October 2021

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825 discussions

[drm/i915/uncore] 5716c8c6f4: RIP:__x86_indirect_thunk_rax
by kernel test robot 03 Oct '21

03 Oct '21

Greeting, FYI, we noticed the following commit (built with gcc-9): commit: 5716c8c6f4b6a985acaf83a19d89131c113f7aeb ("drm/i915/uncore: split the fw get function into separate vfunc") git://anongit.freedesktop.org/drm-intel for-linux-next in testcase: xfstests version: xfstests-x86_64-76d2a91-1_20210918 with following parameters: disk: 4HDD fs: xfs test: xfs-reflink-12 ucode: 0x28 test-description: xfstests is a regression test suite for xfs and other files ystems. test-url: git://git.kernel.org/pub/scm/fs/xfs/xfstests-dev.git on test machine: 8 threads 1 sockets Intel(R) Core(TM) i7-4790 v3 @ 3.60GHz with 6G memory caused below changes (please refer to attached dmesg/kmsg for entire log/backtrace): If you fix the issue, kindly add following tag Reported-by: kernel test robot <oliver.sang(a)intel.com> [ 8.649161][ T254] ata4: DUMMY [ 8.652976][ T254] ata5: DUMMY [ 8.656197][ T254] ata6: DUMMY [ 8.746347][ C3] kernel stack overflow (double-fault): 0000 [#1] SMP PTI [ 8.746349][ C3] CPU: 3 PID: 234 Comm: systemd-udevd Not tainted 5.15.0-rc1-00163-g5716c8c6f4b6 #1 [ 8.746351][ C3] Hardware name: Dell Inc. OptiPlex 9020/03CPWF, BIOS A11 04/01/2015 [ 8.746352][ C3] RIP: 0010:__x86_indirect_thunk_rax+0x0/0x20 [ 8.746357][ C3] Code: e9 b0 aa c0 ff 31 c0 e9 f0 ab c0 ff 31 d2 e9 f2 ab c0 ff 31 c0 e9 ed ab c0 ff 31 c0 e9 fe ac c0 ff 31 c0 e9 00 ad c0 ff cc cc <e8> 07 00 00 00 f3 90 0f ae e8 eb f9 48 89 04 24 c3 66 66 2e 0f 1f [ 8.746358][ C3] RSP: 0018:ffffc900006f8000 EFLAGS: 00010046 [ 8.746361][ C3] RAX: ffffffffc0b588c0 RBX: ffff88818be807d0 RCX: ffff888185ada408 [ 8.746362][ C3] RDX: 0000000000000001 RSI: 0000000000000001 RDI: ffff88818be807d0 [ 8.746363][ C3] RBP: ffff88818be807d0 R08: 0000000000019e80 R09: 0000000000000000 [ 8.746364][ C3] R10: 0000000000000000 R11: 00000000f7bfffff R12: 000000000000911c [ 8.746365][ C3] R13: 0000000000000001 R14: ffff88818be807e8 R15: ffff88818be807d0 [ 8.746366][ C3] FS: 00007fe66957dd40(0000) GS:ffff888185ac0000(0000) knlGS:0000000000000000 [ 8.746368][ C3] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 8.746369][ C3] CR2: ffffc900006f7ff8 CR3: 0000000104220006 CR4: 00000000001706e0 [ 8.746370][ C3] Call Trace: [ 8.746372][ C3] fw_domains_get_with_thread_status+0x15/0x40 [i915] [ 8.746455][ C3] fw_domains_get_with_thread_status+0x15/0x40 [i915] [ 8.746510][ C3] fw_domains_get_with_thread_status+0x15/0x40 [i915] [ 8.746565][ C3] fw_domains_get_with_thread_status+0x15/0x40 [i915] [ 8.746620][ C3] fw_domains_get_with_thread_status+0x15/0x40 [i915] To reproduce: git clone https://github.com/intel/lkp-tests.git cd lkp-tests sudo bin/lkp install job.yaml # job file is attached in this email bin/lkp split-job --compatible job.yaml # generate the yaml file for lkp run sudo bin/lkp run generated-yaml-file # if come across any failure that blocks the test, # please remove ~/.lkp and /lkp dir to run from a clean state. --- 0DAY/LKP+ Test Infrastructure Open Source Technology Center https://lists.01.org/hyperkitty/list/lkp@lists.01.org Intel Corporation Thanks, Oliver Sang

1 0

[PATCH v2 0/8] dsi: rework clock parents and timing handling
by Dmitry Baryshkov 03 Oct '21

03 Oct '21

This patch series brings back several patches targeting assigning dispcc clock parents, that were removed from the massive dsi rework patchset earlier. Few notes: - assign-clock-parents is a mandatory proprety according to the current dsi.txt description. - There is little point in duplicating this functionality with the ad-hoc implementation in the dsi code. On top of that come few minor cleanups for the DSI PHY drivers. I'd kindly ask to bring all dts changes also through the drm tree, so that there won't be any breakage of the functionality. The patchset was tested on RB3 (single DSI), RB5 (single DSI, two independent DSI, bonded DSI, two last configs require additional patches which do not concern the DSI timings code). Changes since v1: - add dt-bindings change - drop the patch removing msm_dsi_dphy_timing The following changes since commit e88bbc91849b2bf57683119c339e52916d34433f: Revert "drm/msm/mdp5: provide dynamic bandwidth management" (2021-06-23 14:06:20 -0700) are available in the Git repository at: https://git.linaro.org/people/dmitry.baryshkov/kernel.git dsi-phy-update for you to fetch changes up to a79d84d8eac721a7ebaf3cfc65b200077b1d6947: drm/msm/dsi: drop msm_dsi_phy_get_shared_timings (2021-07-10 00:02:18 +0300) ---------------------------------------------------------------- Dmitry Baryshkov (8): dt-bindings: display: msm: dsi-controller-main: restore assigned-clocks arm64: dts: qcom: sc7180: assign DSI clock source parents arm64: dts: qcom: sdm845: assign DSI clock source parents arm64: dts: qcom: sdm845-mtp: assign DSI clock source parents arm64: dts: qcom: sm8250: assign DSI clock source parents drm/msm/dsi: stop setting clock parents manually drm/msm/dsi: phy: use of_device_get_match_data drm/msm/dsi: drop msm_dsi_phy_get_shared_timings .../bindings/display/msm/dsi-controller-main.yaml | 17 ++++++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 ++ arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 3 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++ drivers/gpu/drm/msm/dsi/dsi.h | 7 +-- drivers/gpu/drm/msm/dsi/dsi_host.c | 51 ---------------------- drivers/gpu/drm/msm/dsi/dsi_manager.c | 8 +--- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 34 ++++----------- 9 files changed, 47 insertions(+), 88 deletions(-)

2 10

[V2] drm: msm: adreno: use IS_ERR() instead of null pointer check
by Wang Qing 02 Oct '21

02 Oct '21

a6xx_gmu_get_mmio() never return null in case of error, but ERR_PTR(), so we should use IS_ERR() instead of null pointer check and IS_ERR_OR_NULL(). Signed-off-by: Wang Qing <wangqing(a)vivo.com> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 491fee4..82420f7 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -492,7 +492,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); uint32_t pdc_address_offset; - if (!pdcptr || !seqptr) + if (IS_ERR(pdcptr) || IS_ERR(seqptr)) goto err; if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu)) @@ -580,9 +580,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) wmb(); err: - if (!IS_ERR_OR_NULL(pdcptr)) + if (!IS_ERR(pdcptr)) iounmap(pdcptr); - if (!IS_ERR_OR_NULL(seqptr)) + if (!IS_ERR(seqptr)) iounmap(seqptr); } -- 2.7.4

2 2

[PATCH] drm/msm: delete conversion from bool value to bool return
by Bernard Zhao 02 Oct '21

02 Oct '21

Delete the conversion from bool value to bool function return. Signed-off-by: Bernard Zhao <bernard(a)vivo.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 8493d68ad841..411222f4cd6f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -37,7 +37,7 @@ static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc) { - return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false; + return (phys_enc->split_role != ENC_ROLE_SLAVE); } static bool dpu_encoder_phys_cmd_mode_fixup( -- 2.29.0

2 1

[PATCH] drm/msm: dsi: Remove redundant null check before clk_prepare_enable/clk_disable_unprepare
by Xu Wang 02 Oct '21

02 Oct '21

Because clk_prepare_enable() and clk_disable_unprepare() already checked NULL clock parameter, so the additional checks are unnecessary, just remove them. Signed-off-by: Xu Wang <vulab(a)iscas.ac.cn> --- drivers/gpu/drm/msm/dsi/dsi_host.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index ab281cba0f08..e7af90f045bf 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -565,13 +565,11 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) goto pixel_clk_err; } - if (msm_host->byte_intf_clk) { - ret = clk_prepare_enable(msm_host->byte_intf_clk); - if (ret) { - pr_err("%s: Failed to enable byte intf clk\n", - __func__); - goto byte_intf_clk_err; - } + ret = clk_prepare_enable(msm_host->byte_intf_clk); + if (ret) { + pr_err("%s: Failed to enable byte intf clk\n", + __func__); + goto byte_intf_clk_err; } return 0; @@ -667,8 +665,7 @@ void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); clk_disable_unprepare(msm_host->esc_clk); clk_disable_unprepare(msm_host->pixel_clk); - if (msm_host->byte_intf_clk) - clk_disable_unprepare(msm_host->byte_intf_clk); + clk_disable_unprepare(msm_host->byte_intf_clk); clk_disable_unprepare(msm_host->byte_clk); } -- 2.17.1

2 1

[PATCH] drm/msm/mdp5: Remove redundant null check before clk_prepare_enable/clk_disable_unprepare
by Xu Wang 02 Oct '21

02 Oct '21

Because clk_prepare_enable() and clk_disable_unprepare() already checked NULL clock parameter, so the additional checks are unnecessary, just remove them. Signed-off-by: Xu Wang <vulab(a)iscas.ac.cn> --- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 18 ++++++------------ drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 12 ++++-------- 2 files changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index 15aed45022bc..8d373d2ffd51 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -303,15 +303,12 @@ static int mdp5_disable(struct mdp5_kms *mdp5_kms) mdp5_kms->enable_count--; WARN_ON(mdp5_kms->enable_count < 0); - if (mdp5_kms->tbu_rt_clk) - clk_disable_unprepare(mdp5_kms->tbu_rt_clk); - if (mdp5_kms->tbu_clk) - clk_disable_unprepare(mdp5_kms->tbu_clk); + clk_disable_unprepare(mdp5_kms->tbu_rt_clk); + clk_disable_unprepare(mdp5_kms->tbu_clk); clk_disable_unprepare(mdp5_kms->ahb_clk); clk_disable_unprepare(mdp5_kms->axi_clk); clk_disable_unprepare(mdp5_kms->core_clk); - if (mdp5_kms->lut_clk) - clk_disable_unprepare(mdp5_kms->lut_clk); + clk_disable_unprepare(mdp5_kms->lut_clk); return 0; } @@ -325,12 +322,9 @@ static int mdp5_enable(struct mdp5_kms *mdp5_kms) clk_prepare_enable(mdp5_kms->ahb_clk); clk_prepare_enable(mdp5_kms->axi_clk); clk_prepare_enable(mdp5_kms->core_clk); - if (mdp5_kms->lut_clk) - clk_prepare_enable(mdp5_kms->lut_clk); - if (mdp5_kms->tbu_clk) - clk_prepare_enable(mdp5_kms->tbu_clk); - if (mdp5_kms->tbu_rt_clk) - clk_prepare_enable(mdp5_kms->tbu_rt_clk); + clk_prepare_enable(mdp5_kms->lut_clk); + clk_prepare_enable(mdp5_kms->tbu_clk); + clk_prepare_enable(mdp5_kms->tbu_rt_clk); return 0; } diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c index 09bd46ad820b..02c6c4b68c68 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c @@ -137,10 +137,8 @@ static int mdp5_mdss_enable(struct msm_mdss *mdss) DBG(""); clk_prepare_enable(mdp5_mdss->ahb_clk); - if (mdp5_mdss->axi_clk) - clk_prepare_enable(mdp5_mdss->axi_clk); - if (mdp5_mdss->vsync_clk) - clk_prepare_enable(mdp5_mdss->vsync_clk); + clk_prepare_enable(mdp5_mdss->axi_clk); + clk_prepare_enable(mdp5_mdss->vsync_clk); return 0; } @@ -150,10 +148,8 @@ static int mdp5_mdss_disable(struct msm_mdss *mdss) struct mdp5_mdss *mdp5_mdss = to_mdp5_mdss(mdss); DBG(""); - if (mdp5_mdss->vsync_clk) - clk_disable_unprepare(mdp5_mdss->vsync_clk); - if (mdp5_mdss->axi_clk) - clk_disable_unprepare(mdp5_mdss->axi_clk); + clk_disable_unprepare(mdp5_mdss->vsync_clk); + clk_disable_unprepare(mdp5_mdss->axi_clk); clk_disable_unprepare(mdp5_mdss->ahb_clk); return 0; -- 2.17.1

2 1

[PATCH] drm/msm/mdp4: Remove redundant null check before clk_prepare_enable/clk_disable_unprepare
by Xu Wang 02 Oct '21

02 Oct '21

2 1

[PATCH] drm/msm/a6xx: correct cx_debugbus_read arguments
by Dmitry Baryshkov 02 Oct '21

02 Oct '21

First argument of cx_debugbus_read() should be 'void __iomem *' rather than 'void * __iomem' to make sparse happy. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov(a)linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index e8f65cd8eca6..7501849ed15d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -180,7 +180,7 @@ static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, msm_readl((ptr) + ((offset) << 2)) /* read a value from the CX debug bus */ -static int cx_debugbus_read(void *__iomem cxdbg, u32 block, u32 offset, +static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset, u32 *data) { u32 reg = A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) | -- 2.33.0

1 0

Handling DRM master transitions cooperatively
by Dennis Filder 02 Oct '21

02 Oct '21

Hans de Goede asked me to take a topic from a private discussion here. I must also preface that I'm not a graphics person and my knowledge of DRI/DRM is cursory at best. I initiated the conversation with de Goede after learning that the X server now supports being started with an open DRM file descriptor (this was added for Keith Packard's xlease project). I wondered if that could be used to smoothen the Plymouth->X transition somehow and asked de Goede if there were any such plans. He denied, but mentioned that a new ioctl is in the works to prevent the kernel from wiping the contents of a frame buffer after a device is closed, and that this would help to keep transitions smooth. I am a bit disappointed with this being considered a desirable way of handling that transfer of control over a shared DRM device as it shows a lack of ambition. Sure, it's probably easy to implement, but it will also greatly limit how such transitions can be presented to the user. In practice it would mean plymouthd closing the DRM device and exiting so that systemd can start the display manager which then starts an X server to present the login screen. If for that several shared libraries have to first be loaded and relocated while the system is under heavy load then there will be a noticeable delay manifesting as a frozen screen. After that the best you can hope for is blending the still-frame over into the login screen (or whatever comes then). The VT-API-based switching mechanism currently en vogue suffers from similar limitations. If the approach to transferring control were to be changed to a scheme that involves both donor and recipient process connecting to each other on a unix socket and actively coordinating the transfer (i.e. the calls to drmSetMaster and drmDropMaster) then this would open the door to a host of possibilities. Not only could the transition be kept infinitesimally short since both processes are already up, but it could also involve e.g. the recipient continuing an animation the donor had going reusing state that is transferred as a memfd. This way there wouldn't be any noticeable freezes on the display making for a far more polished, and thus impressive experience. It would be a feat a program alone cannot achieve on its own. Another option made possible would be implementing a watchdog. If the recipient transfers e.g. file descriptors for a pipe and a pidfd of itself, then the donor could monitor those for a heartbeat/process termination and take back control over the device if something goes awry (deadlock/crash) and initiate a recovery mechanism. With the other approach implementing such features is simply not possible. Making processes talk to each other and work together like this would also be a far more accurate software representation of what is actually going on: different subsystems passing control over a shared device around to work towards the common goal of a good user experience. A bit of context: The idea underlying this came from my experience with accessibility technology under Linux where uncoordinated fighting over the audio device among all kinds of processes led to countless ways in which things would break with no hope of ever fixing anything. It instilled in me the conviction that user-facing programs are broken if they are not written to talk to each other to coordinate access to shared resources for the goal of rendering a good user experience, but instead leave it to the distro maintainer/user to set things up into a static, brittle working order. Seeing a much-needed cultural shift begin somewhere would be nice. The Plymouth->X transition would lend itself well as a starting point since many building blocks are already there. Regards

6 22

[PATCH v3] drm/msm/dsi: do not enable irq handler before powering up the host
by Dmitry Baryshkov 02 Oct '21

02 Oct '21

The DSI host might be left in some state by the bootloader. If this state generates an IRQ, it might hang the system by holding the interrupt line before the driver sets up the DSI host to the known state. Move the request_irq into msm_dsi_host_init and pass IRQF_NO_AUTOEN to it. Call enable/disable_irq after msm_dsi_host_power_on/_off() functions, so that we can be sure that the interrupt is delivered when the host is in the known state. It is not possible to defer the interrupt enablement to a later point, because drm_panel_prepare might need to communicate with the panel over the DSI link and that requires working interrupt. Fixes: a689554ba6ed ("drm/msm: Initial add DSI connector support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov(a)linaro.org> --- drivers/gpu/drm/msm/dsi/dsi.h | 2 ++ drivers/gpu/drm/msm/dsi/dsi_host.c | 48 +++++++++++++++++---------- drivers/gpu/drm/msm/dsi/dsi_manager.c | 16 +++++++++ 3 files changed, 49 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index b50db91cb8a7..569c8ff062ba 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -107,6 +107,8 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, u32 len); int msm_dsi_host_enable(struct mipi_dsi_host *host); int msm_dsi_host_disable(struct mipi_dsi_host *host); +void msm_dsi_host_enable_irq(struct mipi_dsi_host *host); +void msm_dsi_host_disable_irq(struct mipi_dsi_host *host); int msm_dsi_host_power_on(struct mipi_dsi_host *host, struct msm_dsi_phy_shared_timings *phy_shared_timings, bool is_bonded_dsi, struct msm_dsi_phy *phy); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index e269df285136..ce26eb78cb6c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1898,6 +1898,23 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) return ret; } + msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); + if (msm_host->irq < 0) { + ret = msm_host->irq; + dev_err(&pdev->dev, "failed to get irq: %d\n", ret); + return ret; + } + + /* do not autoenable, will be enabled later */ + ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT | IRQF_NO_AUTOEN, + "dsi_isr", msm_host); + if (ret < 0) { + dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", + msm_host->irq, ret); + return ret; + } + init_completion(&msm_host->dma_comp); init_completion(&msm_host->video_comp); mutex_init(&msm_host->dev_mutex); @@ -1941,25 +1958,8 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; - struct platform_device *pdev = msm_host->pdev; int ret; - msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); - if (msm_host->irq < 0) { - ret = msm_host->irq; - DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret); - return ret; - } - - ret = devm_request_irq(&pdev->dev, msm_host->irq, - dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "dsi_isr", msm_host); - if (ret < 0) { - DRM_DEV_ERROR(&pdev->dev, "failed to request IRQ%u: %d\n", - msm_host->irq, ret); - return ret; - } - msm_host->dev = dev; ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); if (ret) { @@ -2315,6 +2315,20 @@ void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, clk_req->escclk_rate = msm_host->esc_clk_rate; } +void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + enable_irq(msm_host->irq); +} + +void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + disable_irq(msm_host->irq); +} + int msm_dsi_host_enable(struct mipi_dsi_host *host) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index c41d39f5b7cf..fb4ccffdcfe1 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -377,6 +377,14 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) } } + /* + * Enable before preparing the panel, disable after unpreparing, so + * that the panel can communicate over the DSI link. + */ + msm_dsi_host_enable_irq(host); + if (is_bonded_dsi && msm_dsi1) + msm_dsi_host_enable_irq(msm_dsi1->host); + /* Always call panel functions once, because even for dual panels, * there is only one drm_panel instance. */ @@ -411,6 +419,10 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) if (panel) drm_panel_unprepare(panel); panel_prep_fail: + msm_dsi_host_disable_irq(host); + if (is_bonded_dsi && msm_dsi1) + msm_dsi_host_disable_irq(msm_dsi1->host); + if (is_bonded_dsi && msm_dsi1) msm_dsi_host_power_off(msm_dsi1->host); host1_on_fail: @@ -523,6 +535,10 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge) id, ret); } + msm_dsi_host_disable_irq(host); + if (is_bonded_dsi && msm_dsi1) + msm_dsi_host_disable_irq(msm_dsi1->host); + /* Save PHY status if it is a clock source */ msm_dsi_phy_pll_save_state(msm_dsi->phy); -- 2.33.0

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dri-devel October 2021