dri-devel March 2021

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867 discussions

[PATCH v2] drm/msm: a6xx: Make sure the SQE microcode is safe
by Jordan Crouse 31 Mar '21

31 Mar '21

Most a6xx targets have security issues that were fixed with new versions of the microcode(s). Make sure that we are booting with a safe version of the microcode for the target and print a message and error if not. v2: Add more informative error messages and fix typos Signed-off-by: Jordan Crouse <jcrouse(a)codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 77 ++++++++++++++++++++++----- 1 file changed, 64 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index ba8e9d3cf0fe..064b7face504 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -522,28 +522,73 @@ static int a6xx_cp_init(struct msm_gpu *gpu) return a6xx_idle(gpu, ring) ? 0 : -EINVAL; } -static void a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, +/* + * Check that the microcode version is new enough to include several key + * security fixes. Return true if the ucode is safe. + */ +static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, struct drm_gem_object *obj) { + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + struct msm_gpu *gpu = &adreno_gpu->base; u32 *buf = msm_gem_get_vaddr(obj); + bool ret = false; if (IS_ERR(buf)) - return; + return false; /* - * If the lowest nibble is 0xa that is an indication that this microcode - * has been patched. The actual version is in dword [3] but we only care - * about the patchlevel which is the lowest nibble of dword [3] - * - * Otherwise check that the firmware is greater than or equal to 1.90 - * which was the first version that had this fix built in + * Targets up to a640 (a618, a630 and a640) need to check for a + * microcode version that is patched to support the whereami opcode or + * one that is new enough to include it by default. */ - if (((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) - a6xx_gpu->has_whereami = true; - else if ((buf[0] & 0xfff) > 0x190) - a6xx_gpu->has_whereami = true; + if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) || + adreno_is_a640(adreno_gpu)) { + /* + * If the lowest nibble is 0xa that is an indication that this + * microcode has been patched. The actual version is in dword + * [3] but we only care about the patchlevel which is the lowest + * nibble of dword [3] + * + * Otherwise check that the firmware is greater than or equal + * to 1.90 which was the first version that had this fix built + * in + */ + if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) || + (buf[0] & 0xfff) >= 0x190) { + a6xx_gpu->has_whereami = true; + ret = true; + goto out; + } + DRM_DEV_ERROR(&gpu->pdev->dev, + "a630 SQE ucode is too old. Have version %x need at least %x\n", + buf[0] & 0xfff, 0x190); + } else { + /* + * a650 tier targets don't need whereami but still need to be + * equal to or newer than 1.95 for other security fixes + */ + if (adreno_is_a650(adreno_gpu)) { + if ((buf[0] & 0xfff) >= 0x195) { + ret = true; + goto out; + } + + DRM_DEV_ERROR(&gpu->pdev->dev, + "a650 SQE ucode is too old. Have version %x need at least %x\n", + buf[0] & 0xfff, 0x195); + } + + /* + * When a660 is added those targets should return true here + * since those have all the critical security fixes built in + * from the start + */ + } +out: msm_gem_put_vaddr(obj); + return ret; } static int a6xx_ucode_init(struct msm_gpu *gpu) @@ -566,7 +611,13 @@ static int a6xx_ucode_init(struct msm_gpu *gpu) } msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); - a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo); + if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) { + msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); + drm_gem_object_put(a6xx_gpu->sqe_bo); + + a6xx_gpu->sqe_bo = NULL; + return -EPERM; + } } gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO, -- 2.25.1

3 4

[PATCH][next] drm/amd/display: remove redundant initialization of variable status
by Colin King 31 Mar '21

31 Mar '21

From: Colin Ian King <colin.king(a)canonical.com> The variable status is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Also clean up an indentation. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king(a)canonical.com> --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index b092627bd661..4c226db777dc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1729,12 +1729,11 @@ bool perform_link_training_with_retries( dc_link_dp_perform_link_training_skip_aux(link, link_setting); return true; } else { - enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0; + enum link_training_result status; - status = dc_link_dp_perform_link_training( - link, - link_setting, - skip_video_pattern); + status = dc_link_dp_perform_link_training(link, + link_setting, + skip_video_pattern); if (status == LINK_TRAINING_SUCCESS) return true; } -- 2.30.2

1 0

[PATCH v3 1/1] dt-bindings: display: sitronix, st7789v-dbi: Add Waveshare 2inch LCD module
by Carlis 31 Mar '21

31 Mar '21

From: "Xuezhi Zhang" <zhangxuezhi1(a)yulong.com> Document support for the Waveshare 2inch LCD module display, which is a 240x320 2" TFT display driven by a Sitronix ST7789V TFT Controller. Signed-off-by: Xuezhi Zhang <zhangxuezhi1(a)yulong.com> --- v2:change compatible name. v3:change auther name. --- .../display/sitronix,st7789v-dbi.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/sitronix,st7789v-dbi.yaml diff --git a/Documentation/devicetree/bindings/display/sitronix,st7789v-dbi.yaml b/Documentation/devicetree/bindings/display/sitronix,st7789v-dbi.yaml new file mode 100644 index 000000000000..6abf82966230 --- /dev/null +++ b/Documentation/devicetree/bindings/display/sitronix,st7789v-dbi.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sitronix,st7789v-dbi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sitronix ST7789V Display Panels Device Tree Bindings + +maintainers: + - Carlis <zhangxuezhi1(a)yulong.com> + +description: + This binding is for display panels using a Sitronix ST7789V + controller in SPI mode. + +allOf: + - $ref: panel/panel-common.yaml# + +properties: + compatible: + oneOf: + - description: + Waveshare 2" 240x320 Color TFT LCD + items: + - enum: + - waveshare,ws2inch + - const: sitronix,st7789v-dbi + + spi-max-frequency: + maximum: 32000000 + + dc-gpios: + maxItems: 1 + description: Display data/command selection (D/CX) + + backlight: true + reg: true + reset-gpios: true + rotation: true + +required: + - compatible + - reg + - dc-gpios + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + + display@0{ + compatible = "waveshare,ws2inch", "sitronix,st7789v-dbi"; + reg = <0>; + spi-max-frequency = <32000000>; + dc-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; + rotation = <270>; + }; + }; + +... -- 2.25.1

2 1

[PATCH] msm/disp: dpu_plane cleanup-coding-style-a-bit
by Bernard Zhao 31 Mar '21

31 Mar '21

Fix sparse warning: drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:1195:41: warning: Using plain integer as NULL pointer Signed-off-by: Bernard Zhao <bernard(a)vivo.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index f898a8f67b7f..687a57850405 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1223,7 +1223,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct drm_plane_state *state = plane->state; - struct dpu_plane_state *pstate = to_dpu_plane_state(state); + struct dpu_plane_state *pstate = (struct dpu_plane_state *)to_dpu_plane_state(state); trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane), pstate->multirect_mode); -- 2.31.0

1 0

[PATCH] drm/nouveau: cleanup-coding-style-a-bit
by Bernard Zhao 31 Mar '21

31 Mar '21

This change is to make the code a bit readable. Signed-off-by: Bernard Zhao <bernard(a)vivo.com> --- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 44 ++++++++++----------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 57df997c5ff3..053e86845d63 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -41,9 +41,9 @@ static int wndwc37e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { struct nvif_push *push = wndw->wndw.push; - int ret; + int ret = PUSH_WAIT(push, 13); - if ((ret = PUSH_WAIT(push, 13))) + if (ret) return ret; PUSH_MTHD(push, NVC37E, SET_CSC_RED2RED, asyw->csc.matrix, 12); @@ -54,9 +54,9 @@ static int wndwc37e_ilut_clr(struct nv50_wndw *wndw) { struct nvif_push *push = wndw->wndw.push; - int ret; + int ret = PUSH_WAIT(push, 2); - if ((ret = PUSH_WAIT(push, 2))) + if (ret) return ret; PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_INPUT_LUT, 0x00000000); @@ -67,9 +67,9 @@ static int wndwc37e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { struct nvif_push *push = wndw->wndw.push; - int ret; + int ret = PUSH_WAIT(push, 4); - if ((ret = PUSH_WAIT(push, 4))) + if (ret) return ret; PUSH_MTHD(push, NVC37E, SET_CONTROL_INPUT_LUT, @@ -100,9 +100,9 @@ int wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { struct nvif_push *push = wndw->wndw.push; - int ret; + int ret = PUSH_WAIT(push, 8); - if ((ret = PUSH_WAIT(push, 8))) + if (ret) return ret; PUSH_MTHD(push, NVC37E, SET_COMPOSITION_CONTROL, @@ -145,9 +145,9 @@ int wndwc37e_image_clr(struct nv50_wndw *wndw) { struct nvif_push *push = wndw->wndw.push; - int ret; + int ret = PUSH_WAIT(push, 4); - if ((ret = PUSH_WAIT(push, 4))) + if (ret) return ret; PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL, @@ -162,9 +162,9 @@ static int wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { struct nvif_push *push = wndw->wndw.push; - int ret; + int ret = PUSH_WAIT(push, 17); - if ((ret = PUSH_WAIT(push, 17))) + if (ret) return ret; PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL, @@ -215,9 +215,9 @@ int wndwc37e_ntfy_clr(struct nv50_wndw *wndw) { struct nvif_push *push = wndw->wndw.push; - int ret; + int ret = PUSH_WAIT(push, 2); - if ((ret = PUSH_WAIT(push, 2))) + if (ret) return ret; PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, 0x00000000); @@ -228,9 +228,9 @@ int wndwc37e_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { struct nvif_push *push = wndw->wndw.push; - int ret; + int ret = PUSH_WAIT(push, 3); - if ((ret = PUSH_WAIT(push, 3))) + if (ret) return ret; PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, asyw->ntfy.handle, @@ -245,9 +245,9 @@ int wndwc37e_sema_clr(struct nv50_wndw *wndw) { struct nvif_push *push = wndw->wndw.push; - int ret; + int ret = PUSH_WAIT(push, 2); - if ((ret = PUSH_WAIT(push, 2))) + if (ret) return ret; PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000); @@ -258,9 +258,9 @@ int wndwc37e_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { struct nvif_push *push = wndw->wndw.push; - int ret; + int ret = PUSH_WAIT(push, 5); - if ((ret = PUSH_WAIT(push, 5))) + if (ret) return ret; PUSH_MTHD(push, NVC37E, SET_SEMAPHORE_CONTROL, asyw->sema.offset, @@ -274,9 +274,9 @@ int wndwc37e_update(struct nv50_wndw *wndw, u32 *interlock) { struct nvif_push *push = wndw->wndw.push; - int ret; + int ret = PUSH_WAIT(push, 5); - if ((ret = PUSH_WAIT(push, 5))) + if (ret) return ret; PUSH_MTHD(push, NVC37E, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS] << 1 | -- 2.31.0

1 0

[PATCH v6 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs
by Liu Ying 31 Mar '21

31 Mar '21

Hi, This is the v6 series to add some DRM bridge drivers support for i.MX8qm/qxp SoCs. The bridges may chain one by one to form display pipes to support LVDS displays. The relevant display controller is DPU embedded in i.MX8qm/qxp SoCs. The DPU KMS driver can be found at: https://www.spinics.net/lists/arm-kernel/msg878542.html This series supports the following display pipes: 1) i.MX8qxp: prefetch eng -> DPU -> pixel combiner -> pixel link -> pixel link to DPI(PXL2DPI) -> LVDS display bridge(LDB) 2) i.MX8qm: prefetch eng -> DPU -> pixel combiner -> pixel link -> LVDS display bridge(LDB) This series dropped the patch 'phy: Add LVDS configuration options', as suggested by Robert Foss, because it has already been sent with the following series to add Mixel combo PHY found in i.MX8qxp: https://www.spinics.net/lists/arm-kernel/msg879957.html So, this version depends on that series. Patch 1/14 and 2/14 add bus formats used by pixel combiner. Patch 7/14 adds dt-binding for Control and Status Registers module(a syscon used by PXL2DPI and LDB), which references the PXL2DPI and LDB schemas. Patch 10/14 adds a helper for LDB bridge drivers. Patch 3/14 ~ 6/14, 8/14, 9/14 and 11/14 ~ 13/14 add drm bridge drivers and dt-bindings support for the bridges. Patch 14/14 updates MAINTAINERS. I've tested this series with a koe,tx26d202vm0bwa dual link LVDS panel and a LVDS to HDMI bridge(with a downstream drm bridge driver). Welcome comments, thanks. v5->v6: * Fix data organizations in documentation(patch 2/14) for MEDIA_BUS_FMT_RGB{666,888}_1X30-CPADLO. (Laurent) * Add Laurent's R-b tags on patch 1/14 and 2/14. * Drop 'select' schema from the CSR dt-binding documentation(patch 7/14). (Rob) * Add Rob's R-b tag on patch 8/14. v4->v5: * Drop the patch 'phy: Add LVDS configuration options'. (Robert) * Add Robert's R-b tags on patch 1/14, 2/14, 4/14 and 6/14. * Drop the 'PC_BUF_PARA_REG' register definition from the pixel combiner bridge driver(patch 4/14). (Robert) * Make a comment occupy a line in the pixel link bridge driver(patch 6/14). (Robert) * Introduce a new patch(patch 7/14) to add dt-binding for Control and Status Registers module. (Rob) * Make imx-ldb-helper be a pure object to be linked with i.MX8qxp LDB bridge driver and i.MX8qm LDB bridge driver, instead of a module. Correspondingly, rename 'imx8{qm, qxp}-ldb.c' to 'imx8{qm, qxp}-ldb-drv.c'. (Robert) * Move 'imx_ldb_helper.h' to 'drivers/gpu/drm/bridge/imx/imx-ldb-helper.h'. (Robert) * s/__FSL_IMX_LDB__/__IMX_LDB_HELPER__/ for 'imx-ldb-helper.h'. v3->v4: * Use 'fsl,sc-resource' DT property to get the SCU resource ID associated with the PXL2DPI instance instead of using alias ID. (Rob) * Add Rob's R-b tag on patch 11/14. v2->v3: * Drop 'fsl,syscon' DT properties from fsl,imx8qxp-ldb.yaml and fsl,imx8qxp-pxl2dpi.yaml. (Rob) * Mention the CSR module controls LDB and PXL2DPI in fsl,imx8qxp-ldb.yaml and fsl,imx8qxp-pxl2dpi.yaml. * Call syscon_node_to_regmap() to get regmaps from LDB bridge helper driver and PXL2DPI bridger driver instead of syscon_regmap_lookup_by_phandle(). * Drop two macros from pixel link bridge driver which help define functions and define them directly. * Properly disable all pixel link controls to POR value by calling imx8qxp_pixel_link_disable_all_controls() from imx8qxp_pixel_link_bridge_probe(). * Add Rob's R-b tags on patch 4/14 and 6/14. v1->v2: * Rebase the series upon the latest drm-misc-next branch(5.11-rc2 based). * Use graph schema in the dt-bindings of the bridges. (Laurent) * Require all four pixel link output ports in fsl,imx8qxp-pixel-link.yaml. (Laurent) * Side note i.MX8qm/qxp LDB official name 'pixel mapper' in fsl,imx8qxp-ldb.yaml. (Laurent) * Mention pixel link is accessed via SCU firmware in fsl,imx8qxp-pixel-link.yaml. (Rob) * Use enum instead of oneOf + const for the reg property of pixel combiner channels in fsl,imx8qxp-pixel-combiner.yaml. (Rob) * Rewrite the function to find the next bridge in pixel link bridge driver by properly using OF APIs and dropping unnecessary DT validation. (Rob) * Drop unnecessary port availability check in i.MX8qxp pixel link to DPI bridge driver. * Drop unnecessary DT validation from i.MX8qxp LDB bridge driver. * Use of_graph_get_endpoint_by_regs() and of_graph_get_remote_endpoint() to get the input remote endpoint in imx8qxp_ldb_set_di_id() of i.MX8qxp LDB bridge driver. * Avoid using companion_port OF node after putting it in imx8qxp_ldb_parse_dt_companion() of i.MX8qxp LDB bridge driver. * Drop unnecessary check for maximum available LDB channels from i.MX8qm LDB bridge driver. * Mention i.MX8qm/qxp LDB official name 'pixel mapper' in i.MX8qm/qxp LDB bridge drivers and Kconfig help messages. Liu Ying (14): media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner media: docs: Add some RGB bus formats for i.MX8qm/qxp pixel combiner dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding drm/bridge: imx: Add i.MX8qm/qxp display pixel link support dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module binding dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding drm/bridge: imx: Add i.MX8qxp pixel link to DPI support drm/bridge: imx: Add LDB driver helper support dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding drm/bridge: imx: Add LDB support for i.MX8qxp drm/bridge: imx: Add LDB support for i.MX8qm MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs .../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 173 +++++ .../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144 +++++ .../display/bridge/fsl,imx8qxp-pixel-link.yaml | 106 +++ .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 108 ++++ .../devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml | 192 ++++++ .../userspace-api/media/v4l/subdev-formats.rst | 156 +++++ MAINTAINERS | 10 + drivers/gpu/drm/bridge/Kconfig | 2 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/imx/Kconfig | 42 ++ drivers/gpu/drm/bridge/imx/Makefile | 9 + drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 232 +++++++ drivers/gpu/drm/bridge/imx/imx-ldb-helper.h | 98 +++ drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c | 586 +++++++++++++++++ drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c | 720 +++++++++++++++++++++ .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c | 448 +++++++++++++ drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 427 ++++++++++++ drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 485 ++++++++++++++ include/uapi/linux/media-bus-format.h | 6 +- 19 files changed, 3944 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig create mode 100644 drivers/gpu/drm/bridge/imx/Makefile create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.h create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c -- 2.7.4

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[PATCH v3 0/1] Fixes 30e2ae943c26 "drm/bridge: Introduce LT8912B DSI to HDMI"
by Adrien Grassein 31 Mar '21

31 Mar '21

Hi, This patch fixes issues found by a static checker. Thanks, Adrien Grassein (1): drm/bridge: lt8912b: Fix issues found during static analysis drivers/gpu/drm/bridge/lontium-lt8912b.c | 27 +++++++++++++++--------- 1 file changed, 17 insertions(+), 10 deletions(-) -- 2.25.1

2 3

[PATCH] drm/mediatek: Add missing MODULE_DEVICE_TABLE()
by Enric Balletbo i Serra 31 Mar '21

31 Mar '21

From: Boris Brezillon <boris.brezillon(a)collabora.com> This patch adds the missing MODULE_DEVICE_TABLE definitions on different Mediatek drivers which generates correct modalias for automatic loading when these drivers are compiled as an external module. Signed-off-by: Boris Brezillon <boris.brezillon(a)collabora.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo(a)collabora.com> --- drivers/gpu/drm/mediatek/mtk_cec.c | 2 ++ drivers/gpu/drm/mediatek/mtk_dpi.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + drivers/gpu/drm/mediatek/mtk_hdmi.c | 1 + drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c | 1 + 6 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c index cb29b649fcdb..3b86e626e459 100644 --- a/drivers/gpu/drm/mediatek/mtk_cec.c +++ b/drivers/gpu/drm/mediatek/mtk_cec.c @@ -7,6 +7,7 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/interrupt.h> +#include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/platform_device.h> @@ -247,6 +248,7 @@ static const struct of_device_id mtk_cec_of_ids[] = { { .compatible = "mediatek,mt8173-cec", }, {} }; +MODULE_DEVICE_TABLE(of, mtk_cec_of_ids); struct platform_driver mtk_cec_driver = { .probe = mtk_cec_probe, diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 52f11a63a330..2680370652fd 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -822,6 +822,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = { }, { }, }; +MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); struct platform_driver mtk_dpi_driver = { .probe = mtk_dpi_probe, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 5f49a809689b..e4645c8ae1c0 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -470,6 +470,7 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8183_mmsys_driver_data}, { } }; +MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); static int mtk_drm_probe(struct platform_device *pdev) { diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 0527480c07be..c71ce62d1bec 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1193,6 +1193,7 @@ static const struct of_device_id mtk_dsi_of_match[] = { .data = &mt8183_dsi_driver_data }, { }, }; +MODULE_DEVICE_TABLE(of, mtk_dsi_of_match); struct platform_driver mtk_dsi_driver = { .probe = mtk_dsi_probe, diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 8ee55f9e2954..b4696a9d73f7 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1818,6 +1818,7 @@ static const struct of_device_id mtk_drm_hdmi_of_ids[] = { }, {} }; +MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_of_ids); static struct platform_driver mtk_hdmi_driver = { .probe = mtk_drm_hdmi_probe, diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c index 62dbad5675bb..6207eac88550 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c @@ -335,6 +335,7 @@ static const struct of_device_id mtk_hdmi_ddc_match[] = { { .compatible = "mediatek,mt8173-hdmi-ddc", }, {}, }; +MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_match); struct platform_driver mtk_hdmi_ddc_driver = { .probe = mtk_hdmi_ddc_probe, -- 2.30.0

3 3

[PATCH v2 0/2] HDCP 2.2 DP errata
by Anshuman Gupta 31 Mar '21

31 Mar '21

HDCP DP 2.2 errata is part of HDCP DP 2.3 specs as well. Anshuman Gupta (2): drm/i915/hdcp: Add DP HDCP2.2 timeout to read entire msg drm/hdcp: DP HDCP2.2 errata LC_Send_L_Prime=16 drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 45 ++++++++++++++------ include/drm/drm_hdcp.h | 5 ++- 2 files changed, 36 insertions(+), 14 deletions(-) -- 2.26.2

3 6

[PATCH v2 0/1] Fixes 30e2ae943c26 "drm/bridge: Introduce LT8912B DSI to HDMI"
by Adrien Grassein 31 Mar '21

31 Mar '21

Hi, This patch fixes issues found by a static checker. Thanks, Adrien Grassein (1): drm/bridge: lt8912b: Fix issues found during static analysis drivers/gpu/drm/bridge/lontium-lt8912b.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) -- 2.25.1

2 2

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dri-devel March 2021