dri-devel June 2021

dri-devel@lists.freedesktop.org

341 participants
878 discussions

[PATCH v5 0/1] Document drm_mode_get_plane
by Leandro Ribeiro 11 Jun '21

11 Jun '21

v2: possible_crtcs field is a bitmask, not a pointer. Suggested by Ville Syrjälä <ville.syrjala(a)linux.intel.com> v3: document how userspace should find out CRTC index. Also, document that field 'gamma_size' represents the number of entries in the lookup table. Suggested by Pekka Paalanen <ppaalanen(a)gmail.com> and Daniel Vetter <daniel(a)ffwll.ch> v4: document IN and OUT fields and make the description more concise. Suggested by Pekka Paalanen <ppaalanen(a)gmail.com> v5: CRTC index patch already merged, only patch to document drm_mode_get_plane now. Added that gamma LUT size is deprecated and dropped incorrect text documenting that plane number of formats may change from one ioctl to the other. Suggested by Ville Syrjälä <ville.syrjala(a)linux.intel.com> Leandro Ribeiro (1): drm/doc: document drm_mode_get_plane include/uapi/drm/drm_mode.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 2.31.1

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[PATCH v10 00/11] drm: Fix EDID reading on ti-sn65dsi86 by introducing the DP AUX bus
by Douglas Anderson 11 Jun '21

11 Jun '21

The primary goal of this series is to try to properly fix EDID reading for eDP panels using the ti-sn65dsi86 bridge. Previously we had a patch that added EDID reading but it turned out not to work at bootup. This caused some extra churn at bootup as we tried (and failed) to read the EDID several times and also ended up forcing us to use the hardcoded mode at boot. With this patch series I believe EDID reading is reliable at boot now and we never use the hardcoded mode. High level note: in this series the EDID reading is driven by the panel driver, not by the bridge chip driver. I believe this makes a reasonable amount of sense since the panel driver already _could_ drive reading the EDID if provided with the DDC bus and in future planned work we'll want to give the panel driver the DDC bus (to make decisions based on EDID) and the AUX bus (to control the backlight). There are also planned patches from Laurent to make ti-sn65dsi86 able to drive full DP monitors. In that case the bridge chip will still be in charge of reading the EDID, but it's not hard to make this dynamic. This series is the logical successor to the 3-part series containing the patch ("drm/bridge: ti-sn65dsi86: Properly get the EDID, but only if refclk") [1]. This patch was tested against drm-misc-next commit f42498705965 ("drm/panfrost: Fix missing clk_disable_unprepare() on error in panfrost_clk_init()") on a sc7180-trogdor-lazor device. At v10 now, this is ready to land and I plan to commit it shortly. All patches have reviews and Laurent has said over IRC he doesn't object it it landing. Between v2 and v3, high-level view of changes: - stop doing the EDID caching in the core. Between v3 and v4, high-level view of changes: - EDID reading is actually driven by the panel driver now. See above. - Lots of chicken-and-egg problems solved w/ sub-devices. Between v4 and v5, high-level view of changes. - Some of the early patches landed, so dropped from series. - New pm_runtime_disable() fix (fixed a patch that already landed). - Added Bjorn's tags to most patches - Fixed problems when building as a module. - Reordered debugfs patch and fixed error handling there. - Dropped last patch. I'm not convinced it's safe w/out more work. Between v5 and v6, high-level view of changes: - Added the patch ("drm/dp: Allow an early call to register DDC i2c bus") - Many patches had been landed, so only a few "controversial" ones left. Between v6 and v7, high-level view of changes: - New AUX DP bus! Between v7 and v8, high-level view of changes: - More bindings work. - Fixed allmodconfig. Between v8 and v9, high-level view of changes: - Fixed error/remove in panel. - Properly handle of_node in sub-devices in sn65dsi86. - Tiny bindings touchup including dropping "Example" patch. - Added review tags. - Added error message cleanup patch at the end. - First patch (bugfix) dropped (it landed). Between v9 and v10, high-level view of changes: - Review/Ack tags added. - Check memory allocation result. [1] https://lore.kernel.org/r/20210304155144.3.I60a7fb23ce4589006bc95c64ab8d15c… Changes in v10: - Error-check kzalloc Changes in v9: - ("Improve probe errors") patch new for v9. - Commit message now notes aux-bus yaml won't have an "Example". - Fix error handling / remove case when using AUX bus for DDC. - Properly set the of_node of sn65dsi86 auxbus devices now. - Rebased atop v9 ("Promote the AUX channel") patch. - Use an absolute path to refer to aux-bus schema. Changes in v8: - Allow dp-aux-bus to be a module to fix allmodconfig builds - Explain better why HPD needs to be in panel-simple in commit msg. - Separate DP AUX bus binding is new for v8. - ti-sn65dsi86 references the new aux bus bindings. Changes in v7: - Adjusted commit message to talk about DP AUX bus. - Beefed up commit message in context of the DP AUX bus. - List hpd properties bindings patch new for v7. - Panel now under bridge chip instead of getting a link to ddc-i2c - Patch introducing the DP AUX bus is new for v7. - Patch to allow panel-simple to be DP AUX EP new for v7. - Patch to support for DP AUX bus on ti-sn65dsi86 new for v7. - Patch using the DP AUX for DDC new for v7. - Remove use of now-dropped drm_dp_aux_register_ddc() call. - Set the proper sub-device "dev" pointer in the AUX structure. - ti-sn65dsi86: Add aux-bus child patch new for v7. Changes in v6: - Use new drm_dp_aux_register_ddc() calls. Douglas Anderson (11): dt-bindings: display: simple: List hpd properties in panel-simple dt-bindings: drm: Introduce the DP AUX bus dt-bindings: drm/bridge: ti-sn65dsi86: Add aux-bus child drm: Introduce the DP AUX bus drm/panel: panel-simple: Allow panel-simple be a DP AUX endpoint device drm/panel: panel-simple: Stash DP AUX bus; allow using it for DDC drm/bridge: ti-sn65dsi86: Promote the AUX channel to its own sub-dev drm/bridge: ti-sn65dsi86: Add support for the DP AUX bus drm/bridge: ti-sn65dsi86: Don't read EDID blob over DDC drm/bridge: ti-sn65dsi86: Improve probe errors with dev_err_probe() arm64: dts: qcom: sc7180-trogdor: Move panel under the bridge chip .../bindings/display/bridge/ti,sn65dsi86.yaml | 20 +- .../bindings/display/dp-aux-bus.yaml | 37 ++ .../bindings/display/panel/panel-simple.yaml | 2 + arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 30 +- drivers/gpu/drm/Kconfig | 5 + drivers/gpu/drm/Makefile | 2 + drivers/gpu/drm/bridge/Kconfig | 1 + drivers/gpu/drm/bridge/ti-sn65dsi86.c | 129 +++---- drivers/gpu/drm/drm_dp_aux_bus.c | 328 ++++++++++++++++++ drivers/gpu/drm/panel/Kconfig | 1 + drivers/gpu/drm/panel/panel-simple.c | 68 +++- include/drm/drm_dp_aux_bus.h | 57 +++ 12 files changed, 596 insertions(+), 84 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/dp-aux-bus.yaml create mode 100644 drivers/gpu/drm/drm_dp_aux_bus.c create mode 100644 include/drm/drm_dp_aux_bus.h -- 2.32.0.272.g935e593368-goog

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[git pull] drm fixes for 5.13-rc6
by Dave Airlie 11 Jun '21

11 Jun '21

Hey Linus, Another week of fixes, nothing too crazy, but a few all over the place, two locking fixes in the core/ttm area, a couple of small driver fixes (radeon, sun4i, mcde, vc4). Then msm and amdgpu have a set of fixes each, mostly for smaller things, though the msm has a DSI fix for a black screen. I haven't seen any intel fixes next week so they may have a few that may or may not wait for next week. Dave. drm-fixes-2021-06-11: drm fixes for 5.13-rc6 drm: - auth locking fix ttm: - locking fix amdgpu: - Use kvzmalloc in amdgu_bo_create - Use drm_dbg_kms for reporting failure to get a GEM FB - Fix some register offsets for Sienna Cichlid - Fix fall-through warning radeon: - memcpy_to/from_io fixes msm: - NULL ptr deref fix - CP_PROTECT reg programming fix - incorrect register shift fix - DSI blank screen fix sun4i: - hdmi output probing fix mcde: - DSI pipeline calc fix vc4: - out of bounds fix The following changes since commit 614124bea77e452aa6df7a8714e8bc820b489922: Linux 5.13-rc5 (2021-06-06 15:47:27 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2021-06-11 for you to fetch changes up to 7de5c0d70c779454785dd2431707df5b841eaeaf: Merge tag 'amd-drm-fixes-5.13-2021-06-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes (2021-06-11 11:17:10 +1000) ---------------------------------------------------------------- drm fixes for 5.13-rc6 drm: - auth locking fix ttm: - locking fix amdgpu: - Use kvzmalloc in amdgu_bo_create - Use drm_dbg_kms for reporting failure to get a GEM FB - Fix some register offsets for Sienna Cichlid - Fix fall-through warning radeon: - memcpy_to/from_io fixes msm: - NULL ptr deref fix - CP_PROTECT reg programming fix - incorrect register shift fix - DSI blank screen fix sun4i: - hdmi output probing fix mcde: - DSI pipeline calc fix vc4: - out of bounds fix ---------------------------------------------------------------- Alexey Minnekhanov (1): drm/msm: Init mm_list before accessing it for use_vram path Changfeng (1): drm/amdgpu: switch kzalloc to kvzalloc in amdgpu_bo_create Chen Li (1): radeon: use memcpy_to/fromio for UVD fw upload Christian König (1): drm/ttm: fix deref of bo->ttm without holding the lock v2 Dave Airlie (3): Merge tag 'drm-msm-fixes-2021-06-10' of https://gitlab.freedesktop.org/drm/msm into drm-fixes Merge tag 'drm-misc-fixes-2021-06-10' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes Merge tag 'amd-drm-fixes-5.13-2021-06-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes Desmond Cheong Zhi Xi (2): drm: Fix use-after-free read in drm_getunique() drm: Lock pointer access in drm_master_release() Gustavo A. R. Silva (1): drm/amd/pm: Fix fall-through warning for Clang Jonathan Marek (3): drm/msm/a6xx: update/fix CP_PROTECT initialization drm/msm/a6xx: fix incorrectly set uavflagprd_inv field for A650 drm/msm/a6xx: avoid shadow NULL reference in failure path Linus Walleij (1): drm/mcde: Fix off by 10^3 in calculation Mark Rutland (1): drm/vc4: fix vc4_atomic_commit_tail() logic Michel Dänzer (1): drm/amdgpu: Use drm_dbg_kms for reporting failure to get a GEM FB Rohit Khaire (1): drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid Saravana Kannan (1): drm/sun4i: dw-hdmi: Make HDMI PHY into a platform device Stephen Boyd (1): drm/msm/dsi: Stash away calculated vco frequency on recalc drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +++- .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 1 + drivers/gpu/drm/drm_auth.c | 3 +- drivers/gpu/drm/drm_ioctl.c | 9 +- drivers/gpu/drm/mcde/mcde_dsi.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 155 +++++++++++++++------ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 1 + drivers/gpu/drm/msm/msm_gem.c | 7 + drivers/gpu/drm/radeon/radeon_uvd.c | 4 +- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 31 ++++- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 5 +- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 41 +++++- drivers/gpu/drm/ttm/ttm_bo.c | 5 +- drivers/gpu/drm/ttm/ttm_device.c | 8 +- drivers/gpu/drm/vc4/vc4_kms.c | 2 +- 19 files changed, 232 insertions(+), 79 deletions(-)

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[PATCH v4 00/24] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers
by Dmitry Baryshkov 11 Jun '21

11 Jun '21

Restructure MSM DSI PHY drivers. What started as an attempt to grok the overcomplicated PHY drivers, has lead up to the idea of merging PHY and PLL code, reducing abstractions, code duplication, dropping dead code, etc. The patches were mainly tested on RB5 (sm8250, 7nm) and DB410c (apq8016, 28nm-lp) and lightly tested on RB3 (sdm845, 10nm). This patchet depends on the patch "clk: fixed: add devm helper for clk_hw_register_fixed_factor()", which was merged in 5.12-rc1: https://lore.kernel.org/r/20210211052206.2955988-4-daniel@0x0f.com Changes since v3: - Rename save_state/restore_state functions/callbacks - Still mention DSI_1 when determining settings for slave PHYs in 14nm and 28nm drivers. - Stop including the external dependency merged upstream long ago. It is properly mentioned in the patchset description. Changes since v2: - Drop the 'stop setting clock parents manually' patch for now together with the dtsi changes. Unlike the rest of patchset it provides functional changes and might require additional discussion. The patchset will be resubmitted later. Changes since v1: - Rebase on top of msm/msm-next - Reorder patches to follow logical sequence - Add sc7180 clocks assignment - Drop sm8250 clocks assignment, as respective file is not updated in msm/msm-next Changes since RFC: - Reorder patches to move global clock patches in the beginning and dtsi patches where they are required. - remove msm_dsi_phy_set_src_pll() and guess src_pll_id using PHY usecase.

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[PATCH 00/13] Update firmware to v62.0.0
by Matthew Brost 11 Jun '21

11 Jun '21

As part of enabling GuC submission [1] we need to update to the latest and greatest firmware. This series does that. This is a destructive change. e.g. Without all the patches in this series it will break the i915 driver. As such, after we review all of these patches they will squashed into a single patch for merging. Signed-off-by: Matthew Brost <matthew.brost(a)intel.com> [1] https://patchwork.freedesktop.org/series/89844/ John Harrison (3): drm/i915/guc: Support per context scheduling policies drm/i915/guc: Unified GuC log drm/i915/guc: Update firmware to v62.0.0 Michal Wajdeczko (10): drm/i915/guc: Introduce unified HXG messages drm/i915/guc: Update MMIO based communication drm/i915/guc: Update CTB response status definition drm/i915/guc: Add flag for mark broken CTB drm/i915/guc: New definition of the CTB descriptor drm/i915/guc: New definition of the CTB registration action drm/i915/guc: New CTB based communication drm/i915/doc: Include GuC ABI documentation drm/i915/guc: Kill guc_clients.ct_pool drm/i915/guc: Kill ads.client_info Documentation/gpu/i915.rst | 8 + .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 107 ++++++ .../gt/uc/abi/guc_communication_ctb_abi.h | 130 +++++-- .../gt/uc/abi/guc_communication_mmio_abi.h | 63 ++-- .../gpu/drm/i915/gt/uc/abi/guc_messages_abi.h | 213 +++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc.c | 107 ++++-- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 45 +-- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 355 +++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 6 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 75 +--- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 29 +- drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 6 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 26 +- 13 files changed, 750 insertions(+), 420 deletions(-) -- 2.28.0

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[GIT PULL] drm/tegra: Changes for v5.14-rc1
by Thierry Reding 11 Jun '21

11 Jun '21

Hi Dave, The following changes since commit 671cc352acd3e2b2832b59787ed8027d9f80ccc9: drm/tegra: Correct DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT (2021-05-31 14:29:44 +0200) are available in the Git repository at: ssh://git.freedesktop.org/git/tegra/linux.git tags/drm/tegra/for-5.14-rc1 for you to fetch changes up to 46f99eebda08963e24efdacec5c95fc66b90f600: drm/tegra: Don't call SET_APPLICATION_ID in VIC boot (2021-06-11 18:48:36 +0200) Note that I've based this on the drm/tegra/for-5.13-rc5 fixes PR that I sent out last week for simplicity. Thanks, Thierry ---------------------------------------------------------------- drm/tegra: Changes for v5.14-rc1 The two major changes here are fixed YUV support as well as scaling on Tegra186 and later. This allows Tegra DRM to be used, for example, as a video sink for the kmssink gstreamer plugin. The remainder of the changes are minor fixes. ---------------------------------------------------------------- Mikko Perttunen (1): drm/tegra: Don't call SET_APPLICATION_ID in VIC boot Tan Zhongjun (1): drm/tegra: Remove superfluous error messages around platform_get_irq() Thierry Reding (2): drm/tegra: hub: Fix YUV support drm/tegra: hub: Implement basic scaling support drivers/gpu/drm/tegra/dc.c | 2 +- drivers/gpu/drm/tegra/dc.h | 26 ++++++ drivers/gpu/drm/tegra/dpaux.c | 4 +- drivers/gpu/drm/tegra/hub.c | 182 +++++++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/tegra/plane.c | 23 +++++- drivers/gpu/drm/tegra/plane.h | 3 +- drivers/gpu/drm/tegra/vic.c | 2 - drivers/gpu/drm/tegra/vic.h | 1 - 8 files changed, 223 insertions(+), 20 deletions(-)

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[PATCH v9 00/11] drm: Fix EDID reading on ti-sn65dsi86 by introducing the DP AUX bus
by Douglas Anderson 11 Jun '21

11 Jun '21

The primary goal of this series is to try to properly fix EDID reading for eDP panels using the ti-sn65dsi86 bridge. Previously we had a patch that added EDID reading but it turned out not to work at bootup. This caused some extra churn at bootup as we tried (and failed) to read the EDID several times and also ended up forcing us to use the hardcoded mode at boot. With this patch series I believe EDID reading is reliable at boot now and we never use the hardcoded mode. High level note: in this series the EDID reading is driven by the panel driver, not by the bridge chip driver. I believe this makes a reasonable amount of sense since the panel driver already _could_ drive reading the EDID if provided with the DDC bus and in future planned work we'll want to give the panel driver the DDC bus (to make decisions based on EDID) and the AUX bus (to control the backlight). There are also planned patches from Laurent to make ti-sn65dsi86 able to drive full DP monitors. In that case the bridge chip will still be in charge of reading the EDID, but it's not hard to make this dynamic. This series is the logical successor to the 3-part series containing the patch ("drm/bridge: ti-sn65dsi86: Properly get the EDID, but only if refclk") [1]. This patch was tested against drm-misc-next commit 24994b91ecc5 ("MAINTAINERS: Add maintainer for hyperv video device") on a sc7180-trogdor-lazor device. At v9 now this just had a few tiny tweaks / bugfixes. I also added a patch to the end to make deferred probe a bit prettier. I _think_ this series is now ready to land and seems to be fairly well-reviewed. I believe all that's left is Laurent's official blessing that it's OK for the panel to drive the EDID reading in this case. Between v2 and v3, high-level view of changes: - stop doing the EDID caching in the core. Between v3 and v4, high-level view of changes: - EDID reading is actually driven by the panel driver now. See above. - Lots of chicken-and-egg problems solved w/ sub-devices. Between v4 and v5, high-level view of changes. - Some of the early patches landed, so dropped from series. - New pm_runtime_disable() fix (fixed a patch that already landed). - Added Bjorn's tags to most patches - Fixed problems when building as a module. - Reordered debugfs patch and fixed error handling there. - Dropped last patch. I'm not convinced it's safe w/out more work. Between v5 and v6, high-level view of changes: - Added the patch ("drm/dp: Allow an early call to register DDC i2c bus") - Many patches had been landed, so only a few "controversial" ones left. Between v6 and v7, high-level view of changes: - New AUX DP bus! Between v7 and v8, high-level view of changes: - More bindings work. - Fixed allmodconfig. Between v8 and v9, high-level view of changes: - Fixed error/remove in panel. - Properly handle of_node in sub-devices in sn65dsi86. - Tiny bindings touchup including dropping "Example" patch. - Added review tags. - Added error message cleanup patch at the end. - First patch (bugfix) dropped (it landed). [1] https://lore.kernel.org/r/20210304155144.3.I60a7fb23ce4589006bc95c64ab8d15c… Changes in v9: - ("Improve probe errors") patch new for v9. - Commit message now notes aux-bus yaml won't have an "Example". - Fix error handling / remove case when using AUX bus for DDC. - Properly set the of_node of sn65dsi86 auxbus devices now. - Rebased atop v9 ("Promote the AUX channel") patch. - Use an absolute path to refer to aux-bus schema. Changes in v8: - Allow dp-aux-bus to be a module to fix allmodconfig builds - Explain better why HPD needs to be in panel-simple in commit msg. - Separate DP AUX bus binding is new for v8. - ti-sn65dsi86 references the new aux bus bindings. Changes in v7: - Adjusted commit message to talk about DP AUX bus. - Beefed up commit message in context of the DP AUX bus. - List hpd properties bindings patch new for v7. - Panel now under bridge chip instead of getting a link to ddc-i2c - Patch introducing the DP AUX bus is new for v7. - Patch to allow panel-simple to be DP AUX EP new for v7. - Patch to support for DP AUX bus on ti-sn65dsi86 new for v7. - Patch using the DP AUX for DDC new for v7. - Remove use of now-dropped drm_dp_aux_register_ddc() call. - Set the proper sub-device "dev" pointer in the AUX structure. - ti-sn65dsi86: Add aux-bus child patch new for v7. Changes in v6: - Use new drm_dp_aux_register_ddc() calls. Douglas Anderson (11): dt-bindings: display: simple: List hpd properties in panel-simple dt-bindings: drm: Introduce the DP AUX bus dt-bindings: drm/bridge: ti-sn65dsi86: Add aux-bus child drm: Introduce the DP AUX bus drm/panel: panel-simple: Allow panel-simple be a DP AUX endpoint device drm/panel: panel-simple: Stash DP AUX bus; allow using it for DDC drm/bridge: ti-sn65dsi86: Promote the AUX channel to its own sub-dev drm/bridge: ti-sn65dsi86: Add support for the DP AUX bus drm/bridge: ti-sn65dsi86: Don't read EDID blob over DDC drm/bridge: ti-sn65dsi86: Improve probe errors with dev_err_probe() arm64: dts: qcom: sc7180-trogdor: Move panel under the bridge chip .../bindings/display/bridge/ti,sn65dsi86.yaml | 20 +- .../bindings/display/dp-aux-bus.yaml | 37 ++ .../bindings/display/panel/panel-simple.yaml | 2 + arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 30 +- drivers/gpu/drm/Kconfig | 5 + drivers/gpu/drm/Makefile | 2 + drivers/gpu/drm/bridge/Kconfig | 1 + drivers/gpu/drm/bridge/ti-sn65dsi86.c | 129 +++---- drivers/gpu/drm/drm_dp_aux_bus.c | 326 ++++++++++++++++++ drivers/gpu/drm/panel/Kconfig | 1 + drivers/gpu/drm/panel/panel-simple.c | 68 +++- include/drm/drm_dp_aux_bus.h | 57 +++ 12 files changed, 594 insertions(+), 84 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/dp-aux-bus.yaml create mode 100644 drivers/gpu/drm/drm_dp_aux_bus.c create mode 100644 include/drm/drm_dp_aux_bus.h -- 2.32.0.rc1.229.g3e70b5a671-goog

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[PATCH] drm/i915: Document the Virtual Engine uAPI
by Tvrtko Ursulin 11 Jun '21

11 Jun '21

From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> A little bit of documentation covering the topics of engine discovery, context engine maps and virtual engines. It is not very detailed but supposed to be a starting point of giving a brief high level overview of general principles and intended use cases. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> --- Documentation/gpu/i915.rst | 184 +++++++++++++++++++++++++++++++++++++ 1 file changed, 184 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 42ce0196930a..8e5ab299c31f 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -335,6 +335,190 @@ for execution also include a list of all locations within buffers that refer to GPU-addresses so that the kernel can edit the buffer correctly. This process is dubbed relocation. +Engine Discovery uAPI +--------------------- + +Engine discovery uAPI is a way of enumerating physical engines present in a GPU +associated with an open i915 DRM file descriptor. This supersedes the old way of +using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like +`I915_PARAM_HAS_BLT`. + +The need for this interface came starting with Icelake and newer GPUs, which +started to establish a pattern of having multiple engines of a same class, where +not all instances were always completely functionally equivalent. + +Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the +`DRM_I915_QUERY_ENGINE_INFO` as the queried item id. + +Example for getting the list of engines: + +.. code-block:: C + + struct drm_i915_query_engine_info *info; + struct drm_i915_query_item item = { + .query_id = DRM_I915_QUERY_ENGINE_INFO; + }; + struct drm_i915_query query = { + .num_items = 1, + .items_ptr = (uintptr_t)&item, + }; + int err, i; + + // First query the size of the blob we need, this needs to be large + // enough to hold our array of engines. The kernel will fill out the + // item.length for us, which is the number of bytes we need. + // + // Alternatively a large buffer can be allocated straight away enabling + // querying in one pass, in which case item.length should contain the + // length of the provided buffer. + err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); + if (err) ... + + info = calloc(1, item.length); + // Now that we allocated the required number of bytes, we call the ioctl + // again, this time with the data_ptr pointing to our newly allocated + // blob, which the kernel can then populate with info on all engines. + item.data_ptr = (uintptr_t)&info, + + err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); + if (err) ... + + // We can now access each engine in the array + for (i = 0; i < info->num_engines; i++) { + struct drm_i915_engine_info einfo = info->engines[i]; + u16 class = einfo.engine.class; + u16 instance = einfo.engine.instance; + .... + } + + free(info); + +Each of the enumerated engines, apart from being defined by its class and +instance (see `struct i915_engine_class_instance`), also can have flags and +capabilities defined as documented in i915_drm.h. + +For instance video engines which support HEVC encoding will have the +`I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. + +Engine discovery only fully comes to its own when combined with the new way of +addressing engines when submitting batch buffers using contexts with engine +maps configured. + +Context Engine Map uAPI +----------------------- + +Context engine map is a new way of addressing engines when submitting batch- +buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` +inside the flags field of `struct drm_i915_gem_execbuffer2`. + +To use it created GEM contexts need to be configured with a list of engines +the user is intending to submit to. This is accomplished using the +`I915_CONTEXT_PARAM_ENGINES` parameter and `struct i915_context_param_engines`. + +For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the +configured map. + +Example of creating such context and submitting against it: + +.. code-block:: C + + I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { + .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, + { I915_ENGINE_CLASS_COPY, 0 } } + }; + struct drm_i915_gem_context_create_ext_setparam p_engines = { + .base = { + .name = I915_CONTEXT_CREATE_EXT_SETPARAM, + }, + .param = { + .param = I915_CONTEXT_PARAM_ENGINES, + .value = to_user_pointer(&engines), + .size = sizeof(engines), + }, + }; + struct drm_i915_gem_context_create_ext create = { + .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, + .extensions = to_user_pointer(&p_engines); + }; + + ctx_id = gem_context_create_ext(drm_fd, &create); + + // We have now created a GEM context with two engines in the map: + // Index 0 points to rcs0 while index 1 points to bcs0. Other engines + // will not be accessible from this context. + + ... + execbuf.rsvd1 = ctx_id; + execbuf.flags = 0; // Submits to index0, which is rcs0 for this context + gem_execbuf(drm_fd, &execbuf); + + ... + execbuf.rsvd1 = ctx_id; + execbuf.flags = 1; // Submits to index0, which is bcs0 for this context + gem_execbuf(drm_fd, &execbuf); + +Virtual Engine uAPI +------------------- + +Virtual engine is a concept where userspace is able to configure a set of +physical engines, submit a batch buffer, and let the driver execute it on any +engine from the set as it sees fit. + +This is primarily useful on parts which have multiple instances of a same class +engine, like for example GT3+ Skylake parts with their two VCS engines. + +For instance userspace can enumerate all engines of a certain class using the +previously described `Engine Discovery uAPI`_. After +that userspace can create a GEM context with a placeholder slot for the virtual +engine (using `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` +for class and instance respectively) and finally using the +`I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in the +same reserved slot. + +Example of creating a virtual engine and submitting a batch buffer to it: + +.. code-block:: C + + I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { + .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, + .engine_index = 0, // Place this virtual engine into engine map slot 0 + .num_siblings = 2, + .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, + { I915_ENGINE_CLASS_VIDEO, 1 }, }, + }; + I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { + .engines = { { I915_ENGINE_CLASS_INVALID, + I915_ENGINE_CLASS_INVALID_NONE } }, + .extensions = to_user_pointer(&virtual), // Chains with the load_balance extension + }; + struct drm_i915_gem_context_create_ext_setparam p_engines = { + .base = { + .name = I915_CONTEXT_CREATE_EXT_SETPARAM, + }, + .param = { + .param = I915_CONTEXT_PARAM_ENGINES, + .value = to_user_pointer(&engines), + .size = sizeof(engines), + }, + }; + struct drm_i915_gem_context_create_ext create = { + .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, + .extensions = to_user_pointer(&p_engines); + }; + + ctx_id = gem_context_create_ext(drm_fd, &create); + + // Now we have created a GEM context with its engine map containing a + // single virtual engine. Submissions to this slot can go either to + // vcs0 or vcs1, depending on the load balancing algorithm used inside + // the driver. The load balancing is dynamic from one batch buffer to + // another and transparent to userspace. + + ... + execbuf.rsvd1 = ctx_id; + execbuf.flags = 0; // Submits to index0 which is the virtual engine + gem_execbuf(drm_fd, &execbuf); + Locking Guidelines ------------------ -- 2.30.2

2 1

[PATCH v8 00/15] Restricted DMA
by Claire Chang 11 Jun '21

11 Jun '21

This series implements mitigations for lack of DMA access control on systems without an IOMMU, which could result in the DMA accessing the system memory at unexpected times and/or unexpected addresses, possibly leading to data leakage or corruption. For example, we plan to use the PCI-e bus for Wi-Fi and that PCI-e bus is not behind an IOMMU. As PCI-e, by design, gives the device full access to system memory, a vulnerability in the Wi-Fi firmware could easily escalate to a full system exploit (remote wifi exploits: [1a], [1b] that shows a full chain of exploits; [2], [3]). To mitigate the security concerns, we introduce restricted DMA. Restricted DMA utilizes the existing swiotlb to bounce streaming DMA in and out of a specially allocated region and does memory allocation from the same region. The feature on its own provides a basic level of protection against the DMA overwriting buffer contents at unexpected times. However, to protect against general data leakage and system memory corruption, the system needs to provide a way to restrict the DMA to a predefined memory region (this is usually done at firmware level, e.g. MPU in ATF on some ARM platforms [4]). [1a] https://googleprojectzero.blogspot.com/2017/04/over-air-exploiting-broadcom… [1b] https://googleprojectzero.blogspot.com/2017/04/over-air-exploiting-broadcom… [2] https://blade.tencent.com/en/advisories/qualpwn/ [3] https://www.bleepingcomputer.com/news/security/vulnerabilities-found-in-hig… [4] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/media… v8: - Fix reserved-memory.txt and add the reg property in example. - Fix sizeof for of_property_count_elems_of_size in drivers/of/address.c#of_dma_set_restricted_buffer. - Apply Will's suggestion to try the OF node having DMA configuration in drivers/of/address.c#of_dma_set_restricted_buffer. - Fix typo in the comment of drivers/of/address.c#of_dma_set_restricted_buffer. - Add error message for PageHighMem in kernel/dma/swiotlb.c#rmem_swiotlb_device_init and move it to rmem_swiotlb_setup. - Fix the message string in rmem_swiotlb_setup. v7: Fix debugfs, PageHighMem and comment style in rmem_swiotlb_device_init https://lore.kernel.org/patchwork/cover/1431031/ v6: Address the comments in v5 https://lore.kernel.org/patchwork/cover/1423201/ v5: Rebase on latest linux-next https://lore.kernel.org/patchwork/cover/1416899/ v4: - Fix spinlock bad magic - Use rmem->name for debugfs entry - Address the comments in v3 https://lore.kernel.org/patchwork/cover/1378113/ v3: Using only one reserved memory region for both streaming DMA and memory allocation. https://lore.kernel.org/patchwork/cover/1360992/ v2: Building on top of swiotlb. https://lore.kernel.org/patchwork/cover/1280705/ v1: Using dma_map_ops. https://lore.kernel.org/patchwork/cover/1271660/ Claire Chang (15): swiotlb: Refactor swiotlb init functions swiotlb: Refactor swiotlb_create_debugfs swiotlb: Add DMA_RESTRICTED_POOL swiotlb: Add restricted DMA pool initialization swiotlb: Add a new get_io_tlb_mem getter swiotlb: Update is_swiotlb_buffer to add a struct device argument swiotlb: Update is_swiotlb_active to add a struct device argument swiotlb: Bounce data from/to restricted DMA pool if available swiotlb: Move alloc_size to find_slots swiotlb: Refactor swiotlb_tbl_unmap_single dma-direct: Add a new wrapper __dma_direct_free_pages() swiotlb: Add restricted DMA alloc/free support. dma-direct: Allocate memory from restricted DMA pool if available dt-bindings: of: Add restricted DMA pool of: Add plumbing for restricted DMA pool .../reserved-memory/reserved-memory.txt | 36 ++- drivers/gpu/drm/i915/gem/i915_gem_internal.c | 2 +- drivers/gpu/drm/nouveau/nouveau_ttm.c | 2 +- drivers/iommu/dma-iommu.c | 12 +- drivers/of/address.c | 25 ++ drivers/of/device.c | 3 + drivers/of/of_private.h | 5 + drivers/pci/xen-pcifront.c | 2 +- drivers/xen/swiotlb-xen.c | 2 +- include/linux/device.h | 4 + include/linux/swiotlb.h | 41 ++- kernel/dma/Kconfig | 14 + kernel/dma/direct.c | 63 +++-- kernel/dma/direct.h | 9 +- kernel/dma/swiotlb.c | 242 +++++++++++++----- 15 files changed, 362 insertions(+), 100 deletions(-) -- 2.31.1.818.g46aad6cb9e-goog

2 13

[PATCH] drm/i915: Fix busy ioctl commentary
by Tvrtko Ursulin 11 Jun '21

11 Jun '21

From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Just tidy one instance of incorrect context parameter name and a stray sentence ending from before reporting was converted to be class based. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> --- include/uapi/drm/i915_drm.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index c2c7759b7d2e..a1cb4aa035a9 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1348,12 +1348,11 @@ struct drm_i915_gem_busy { * reading from the object simultaneously. * * The value of each engine class is the same as specified in the - * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e. + * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e. * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc. - * reported as active itself. Some hardware may have parallel - * execution engines, e.g. multiple media engines, which are - * mapped to the same class identifier and so are not separately - * reported for busyness. + * Some hardware may have parallel execution engines, e.g. multiple + * media engines, which are mapped to the same class identifier and so + * are not separately reported for busyness. * * Caveat emptor: * Only the boolean result of this query is reliable; that is whether -- 2.30.2

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dri-devel June 2021