dri-devel September 2021

dri-devel@lists.freedesktop.org

348 participants
817 discussions

[PATCH v2 00/12] MEMORY_DEVICE_PUBLIC for CPU-accessible coherent device memory
by Alex Sierra 01 Oct '21

01 Oct '21

v1: AMD is building a system architecture for the Frontier supercomputer with a coherent interconnect between CPUs and GPUs. This hardware architecture allows the CPUs to coherently access GPU device memory. We have hardware in our labs and we are working with our partner HPE on the BIOS, firmware and software for delivery to the DOE. The system BIOS advertises the GPU device memory (aka VRAM) as SPM (special purpose memory) in the UEFI system address map. The amdgpu driver registers the memory with devmap as MEMORY_DEVICE_PUBLIC using devm_memremap_pages. This patch series adds MEMORY_DEVICE_PUBLIC, which is similar to MEMORY_DEVICE_GENERIC in that it can be mapped for CPU access, but adds support for migrating this memory similar to MEMORY_DEVICE_PRIVATE. We also included and updated two patches from Ralph Campbell (Nvidia), which change ZONE_DEVICE reference counting as requested in previous reviews of this patch series (see https://patchwork.freedesktop.org/series/90706/). Finally, we extended hmm_test to cover migration of MEMORY_DEVICE_PUBLIC. This work is based on HMM and our SVM memory manager, which has landed in Linux 5.14 recently. v2: Major changes on this version: Fold patches: 'mm: call pgmap->ops->page_free for DEVICE_PUBLIC' and 'mm: add public type support to migrate_vma helpers' into 'mm: add zone device public type memory support' Condition added at migrate_vma_collect_pmd, for migrations from device public pages. Making sure pages are from device zone and with the proper MIGRATE_VMA_SELECT_DEVICE_PUBLIC flag. Patch: 'mm: add device public vma selection for memory migration' Fix logic in 'drm/amdkfd: add SPM support for SVM' to detect error in both DEVICE_PRIVATE and DEVICE_PUBLIC. Minor changes: Swap patch order 03 and 04. Addings Add VM_BUG_ON_PAGE(page_ref_count(page), page) to patch 'drm/amdkfd: ref count init for device pages', to make sure page hasn't been used Alex Sierra (10): mm: add zone device public type memory support mm: add device public vma selection for memory migration drm/amdkfd: ref count init for device pages drm/amdkfd: add SPM support for SVM drm/amdkfd: public type as sys mem on migration to ram lib: test_hmm add ioctl to get zone device type lib: test_hmm add module param for zone device type lib: add support for device public type in test_hmm tools: update hmm-test to support device public type tools: update test_hmm script to support SP config Ralph Campbell (2): ext4/xfs: add page refcount helper mm: remove extra ZONE_DEVICE struct page refcount arch/powerpc/kvm/book3s_hv_uvmem.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 40 ++-- drivers/gpu/drm/nouveau/nouveau_dmem.c | 2 +- fs/dax.c | 8 +- fs/ext4/inode.c | 5 +- fs/fuse/dax.c | 4 +- fs/xfs/xfs_file.c | 4 +- include/linux/dax.h | 10 + include/linux/memremap.h | 15 +- include/linux/migrate.h | 1 + include/linux/mm.h | 19 +- lib/test_hmm.c | 247 +++++++++++++++-------- lib/test_hmm_uapi.h | 16 ++ mm/internal.h | 8 + mm/memcontrol.c | 6 +- mm/memory-failure.c | 6 +- mm/memremap.c | 71 ++----- mm/migrate.c | 33 +-- mm/page_alloc.c | 3 + mm/swap.c | 45 +---- tools/testing/selftests/vm/hmm-tests.c | 142 +++++++++++-- tools/testing/selftests/vm/test_hmm.sh | 20 +- 22 files changed, 451 insertions(+), 256 deletions(-) -- 2.32.0

4 19

[PATCH] drm/i915/gt: move remaining debugfs interfaces into gt
by Andi Shyti 30 Sep '21

30 Sep '21

The following interfaces: i915_wedged i915_forcewake_user i915_gem_interrupt are dependent on gt values. Put them inside gt/ and drop the "i915_" prefix name. This would be the new structure: dri/0/gt | +-- forcewake_user | +-- interrupt_info | \-- reset Signed-off-by: Andi Shyti <andi.shyti(a)intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Cc: Chris Wilson <chris(a)chris-wilson.co.uk> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 47 ++++- .../gpu/drm/i915/gt/intel_gt_irq_debugfs.c | 178 ++++++++++++++++++ .../gpu/drm/i915/gt/intel_gt_irq_debugfs.h | 15 ++ drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 +++ drivers/gpu/drm/i915/i915_debugfs.c | 71 ------- 6 files changed, 271 insertions(+), 72 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 5c8e022a7383..770565c38448 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -100,6 +100,7 @@ gt-y += \ gt/intel_gt_debugfs.o \ gt/intel_gt_engines_debugfs.o \ gt/intel_gt_irq.o \ + gt/intel_gt_irq_debugfs.o \ gt/intel_gt_pm.o \ gt/intel_gt_pm_debugfs.o \ gt/intel_gt_pm_irq.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c index 03fb4aefbf90..2daff03a705a 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c @@ -8,10 +8,53 @@ #include "i915_drv.h" #include "intel_gt_debugfs.h" #include "intel_gt_engines_debugfs.h" +#include "intel_gt_irq_debugfs.h" +#include "intel_gt_pm.h" #include "intel_gt_pm_debugfs.h" +#include "intel_gt_requests.h" #include "intel_sseu_debugfs.h" #include "uc/intel_uc_debugfs.h" +static int reset_show(void *data, u64 *val) +{ + struct intel_gt *gt = data; + int ret = intel_gt_terminally_wedged(gt); + + switch (ret) { + case -EIO: + *val = 1; + return 0; + case 0: + *val = 0; + return 0; + default: + return ret; + } +} + +static int reset_store(void *data, u64 val) +{ + struct intel_gt *gt = data; + + /* Flush any previous reset before applying for a new one */ + wait_event(gt->reset.queue, + !test_bit(I915_RESET_BACKOFF, &gt->reset.flags)); + + intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE, + "Manually reset engine mask to %llx", val); + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n"); + +static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root) +{ + static const struct intel_gt_debugfs_file files[] = { + { "reset", &reset_fops, NULL }, + }; + + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); +} + void intel_gt_debugfs_register(struct intel_gt *gt) { struct dentry *root; @@ -23,10 +66,12 @@ void intel_gt_debugfs_register(struct intel_gt *gt) if (IS_ERR(root)) return; + gt_debugfs_register(gt, root); + intel_gt_engines_debugfs_register(gt, root); intel_gt_pm_debugfs_register(gt, root); + intel_gt_irq_debugfs_register(gt, root); intel_sseu_debugfs_register(gt, root); - intel_uc_debugfs_register(&gt->uc, root); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c new file mode 100644 index 000000000000..3cf9ae8437e5 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: MIT + +/* + * Copyright © 2020 Intel Corporation + */ + +#include "i915_drv.h" +#include "intel_gt_debugfs.h" +#include "intel_gt_irq_debugfs.h" + +static int interrupt_info_show(struct seq_file *m, void *data) +{ + struct intel_gt *gt = m->private; + struct drm_i915_private *i915 = gt->i915; + struct intel_uncore *uncore = gt->uncore; + struct intel_engine_cs *engine; + enum intel_engine_id id; + intel_wakeref_t wakeref; + int i; + + wakeref = intel_runtime_pm_get(uncore->rpm); + + if (IS_CHERRYVIEW(i915)) { + seq_printf(m, "Master Interrupt Control:\t%08x\n", + intel_uncore_read(uncore, GEN8_MASTER_IRQ)); + + for (i = 0; i < 4; i++) { + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IMR(i))); + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IIR(i))); + seq_printf(m, "GT Interrupt IER %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IER(i))); + } + + } else if (GRAPHICS_VER(i915) >= 11) { + seq_printf(m, "Master Interrupt Control: %08x\n", + intel_uncore_read(uncore, GEN11_GFX_MSTR_IRQ)); + + seq_printf(m, "Render/Copy Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_RENDER_COPY_INTR_ENABLE)); + seq_printf(m, "VCS/VECS Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_VCS_VECS_INTR_ENABLE)); + seq_printf(m, "GUC/SG Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUC_SG_INTR_ENABLE)); + seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_GPM_WGBOXPERF_INTR_ENABLE)); + seq_printf(m, "Crypto Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_CRYPTO_RSVD_INTR_ENABLE)); + seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUNIT_CSME_INTR_ENABLE)); + + } else if (GRAPHICS_VER(i915) >= 8) { + seq_printf(m, "Master Interrupt Control:\t%08x\n", + intel_uncore_read(uncore, GEN8_MASTER_IRQ)); + + for (i = 0; i < 4; i++) { + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IMR(i))); + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IIR(i))); + seq_printf(m, "GT Interrupt IER %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IER(i))); + } + + } else if (IS_VALLEYVIEW(i915)) { + seq_printf(m, "Master IER:\t%08x\n", + intel_uncore_read(uncore, VLV_MASTER_IER)); + + seq_printf(m, "Render IER:\t%08x\n", + intel_uncore_read(uncore, GTIER)); + seq_printf(m, "Render IIR:\t%08x\n", + intel_uncore_read(uncore, GTIIR)); + seq_printf(m, "Render IMR:\t%08x\n", + intel_uncore_read(uncore, GTIMR)); + + seq_printf(m, "PM IER:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIER)); + seq_printf(m, "PM IIR:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIIR)); + seq_printf(m, "PM IMR:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIMR)); + + } else if (!HAS_PCH_SPLIT(i915)) { + seq_printf(m, "Interrupt enable: %08x\n", + intel_uncore_read(uncore, GEN2_IER)); + seq_printf(m, "Interrupt identity: %08x\n", + intel_uncore_read(uncore, GEN2_IIR)); + seq_printf(m, "Interrupt mask: %08x\n", + intel_uncore_read(uncore, GEN2_IMR)); + } else { + seq_printf(m, "Graphics Interrupt enable: %08x\n", + intel_uncore_read(uncore, GTIER)); + seq_printf(m, "Graphics Interrupt identity: %08x\n", + intel_uncore_read(uncore, GTIIR)); + seq_printf(m, "Graphics Interrupt mask: %08x\n", + intel_uncore_read(uncore, GTIMR)); + } + + if (GRAPHICS_VER(i915) >= 11) { + seq_printf(m, "RCS Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_RCS0_RSVD_INTR_MASK)); + seq_printf(m, "BCS Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_BCS_RSVD_INTR_MASK)); + seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VCS0_VCS1_INTR_MASK)); + seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VCS2_VCS3_INTR_MASK)); + + if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) + seq_printf(m, "VCS4/VCS5 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN12_VCS4_VCS5_INTR_MASK)); + if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) + seq_printf(m, "VCS6/VCS7 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN12_VCS6_VCS7_INTR_MASK)); + + seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VECS0_VECS1_INTR_MASK)); + + if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) + seq_printf(m, "VECS2/VECS3 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN12_VECS2_VECS3_INTR_MASK)); + + seq_printf(m, "GUC/SG Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUC_SG_INTR_MASK)); + seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n", + intel_uncore_read(uncore, + GEN11_GPM_WGBOXPERF_INTR_MASK)); + seq_printf(m, "Crypto Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_CRYPTO_RSVD_INTR_MASK)); + seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUNIT_CSME_INTR_MASK)); + + } else if (GRAPHICS_VER(i915) >= 6) { + for_each_engine(engine, gt, id) { + seq_printf(m, + "Graphics Interrupt mask (%s): %08x\n", + engine->name, ENGINE_READ(engine, RING_IMR)); + } + } + + intel_runtime_pm_put(uncore->rpm, wakeref); + + return 0; +} +DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(interrupt_info); + +void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root) +{ + static const struct intel_gt_debugfs_file files[] = { + { "interrupt_info", &interrupt_info_fops, NULL }, + }; + + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); +} diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h new file mode 100644 index 000000000000..95e519705001 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ + +/* + * Copyright © 2020 Intel Corporation + */ + +#ifndef INTEL_GT_IRQ_DEBUGFS_H +#define INTEL_GT_IRQ_DEBUGFS_H + +struct intel_gt; +struct dentry; + +void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root); + +#endif /* INTEL_GT_IRQ_DEBUGFS_H */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 5f84ad602642..c75af6f97e7e 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -19,6 +19,36 @@ #include "intel_sideband.h" #include "intel_uncore.h" +static int forcewake_user_open(struct inode *inode, struct file *file) +{ + struct intel_gt *gt = inode->i_private; + + atomic_inc(&gt->user_wakeref); + intel_gt_pm_get(gt); + if (GRAPHICS_VER(gt->i915) >= 6) + intel_uncore_forcewake_user_get(gt->uncore); + + return 0; +} + +static int forcewake_user_release(struct inode *inode, struct file *file) +{ + struct intel_gt *gt = inode->i_private; + + if (GRAPHICS_VER(gt->i915) >= 6) + intel_uncore_forcewake_user_put(gt->uncore); + intel_gt_pm_put(gt); + atomic_dec(&gt->user_wakeref); + + return 0; +} + +static const struct file_operations forcewake_user_fops = { + .owner = THIS_MODULE, + .open = forcewake_user_open, + .release = forcewake_user_release, +}; + static int fw_domains_show(struct seq_file *m, void *data) { struct intel_gt *gt = m->private; @@ -627,6 +657,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root) { "drpc", &drpc_fops, NULL }, { "frequency", &frequency_fops, NULL }, { "forcewake", &fw_domains_fops, NULL }, + { "forcewake_user", &forcewake_user_fops, NULL}, { "llc", &llc_fops, llc_eval }, { "rps_boost", &rps_boost_fops, rps_eval }, }; diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index fdbd46ff59e0..5a2a9315c889 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -554,42 +554,6 @@ static int i915_wa_registers(struct seq_file *m, void *unused) return 0; } -static int -i915_wedged_get(void *data, u64 *val) -{ - struct drm_i915_private *i915 = data; - int ret = intel_gt_terminally_wedged(&i915->gt); - - switch (ret) { - case -EIO: - *val = 1; - return 0; - case 0: - *val = 0; - return 0; - default: - return ret; - } -} - -static int -i915_wedged_set(void *data, u64 val) -{ - struct drm_i915_private *i915 = data; - - /* Flush any previous reset before applying for a new one */ - wait_event(i915->gt.reset.queue, - !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags)); - - intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE, - "Manually set wedged engine mask = %llx", val); - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, - i915_wedged_get, i915_wedged_set, - "%llu\n"); - static int i915_perf_noa_delay_set(void *data, u64 val) { @@ -725,38 +689,6 @@ static int i915_sseu_status(struct seq_file *m, void *unused) return intel_sseu_status(m, gt); } -static int i915_forcewake_open(struct inode *inode, struct file *file) -{ - struct drm_i915_private *i915 = inode->i_private; - struct intel_gt *gt = &i915->gt; - - atomic_inc(&gt->user_wakeref); - intel_gt_pm_get(gt); - if (GRAPHICS_VER(i915) >= 6) - intel_uncore_forcewake_user_get(gt->uncore); - - return 0; -} - -static int i915_forcewake_release(struct inode *inode, struct file *file) -{ - struct drm_i915_private *i915 = inode->i_private; - struct intel_gt *gt = &i915->gt; - - if (GRAPHICS_VER(i915) >= 6) - intel_uncore_forcewake_user_put(&i915->uncore); - intel_gt_pm_put(gt); - atomic_dec(&gt->user_wakeref); - - return 0; -} - -static const struct file_operations i915_forcewake_fops = { - .owner = THIS_MODULE, - .open = i915_forcewake_open, - .release = i915_forcewake_release, -}; - static const struct drm_info_list i915_debugfs_list[] = { {"i915_capabilities", i915_capabilities, 0}, {"i915_gem_objects", i915_gem_object_info, 0}, @@ -775,7 +707,6 @@ static const struct i915_debugfs_files { const struct file_operations *fops; } i915_debugfs_files[] = { {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, - {"i915_wedged", &i915_wedged_fops}, {"i915_gem_drop_caches", &i915_drop_caches_fops}, #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) {"i915_error_state", &i915_error_state_fops}, @@ -790,8 +721,6 @@ void i915_debugfs_register(struct drm_i915_private *dev_priv) i915_debugfs_params(dev_priv); - debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root, - to_i915(minor->dev), &i915_forcewake_fops); for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { debugfs_create_file(i915_debugfs_files[i].name, S_IRUGO | S_IWUSR, -- 2.27.0

1 0

[PATCH 00/27] Parallel submission aka multi-bb execbuf
by Matthew Brost 30 Sep '21

30 Sep '21

As discussed in [1] we are introducing a new parallel submission uAPI for the i915 which allows more than 1 BB to be submitted in an execbuf IOCTL. This is the implemenation for both GuC and execlists. In addition to selftests in the series, an IGT is available implemented in the first 4 patches [2]. Media UMD changes to land soon. First patch in the series in a squashed patch of [3] and does not need to be reviewed here. The execbuf IOCTL changes have been done in a single large patch (#24) as all the changes flow together and I believe a single patch will be better if some one has to lookup this change in the future. Can split in a series of smaller patches if desired. This code is available in a public [4] repo for UMD teams to test there code on. v2: Drop complicated state machine to block in kernel if no guc_ids available, perma-pin parallel contexts, reworker execbuf IOCTL to be a series of loops inside the IOCTL rather than 1 large one on the outside, address Daniel Vetter's comments, rebase on [3] Signed-off-by: Matthew Brost <matthew.brost(a)intel.com> [1] https://patchwork.freedesktop.org/series/92028/ [2] https://patchwork.freedesktop.org/series/93071/ [3] https://patchwork.freedesktop.org/series/93704/ [4] https://gitlab.freedesktop.org/mbrost/mbrost-drm-intel/-/tree/drm-intel-par… Matthew Brost (27): drm/i915/guc: Squash Clean up GuC CI failures, simplify locking, and kernel DOC drm/i915/guc: Allow flexible number of context ids drm/i915/guc: Connect the number of guc_ids to debugfs drm/i915/guc: Take GT PM ref when deregistering context drm/i915: Add GT PM unpark worker drm/i915/guc: Take engine PM when a context is pinned with GuC submission drm/i915/guc: Don't call switch_to_kernel_context with GuC submission drm/i915: Add logical engine mapping drm/i915: Expose logical engine instance to user drm/i915/guc: Introduce context parent-child relationship drm/i915/guc: Implement parallel context pin / unpin functions drm/i915/guc: Add multi-lrc context registration drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids drm/i915/guc: Implement multi-lrc submission drm/i915/guc: Insert submit fences between requests in parent-child relationship drm/i915/guc: Implement multi-lrc reset drm/i915/guc: Update debugfs for GuC multi-lrc drm/i915: Fix bug in user proto-context creation that leaked contexts drm/i915/guc: Connect UAPI to GuC multi-lrc interface drm/i915/doc: Update parallel submit doc to point to i915_drm.h drm/i915/guc: Add basic GuC multi-lrc selftest drm/i915/guc: Implement no mid batch preemption for multi-lrc drm/i915: Multi-BB execbuf drm/i915/guc: Handle errors in multi-lrc requests drm/i915: Enable multi-bb execbuf drm/i915/execlists: Weak parallel submission support for execlists Documentation/gpu/rfc/i915_parallel_execbuf.h | 122 - Documentation/gpu/rfc/i915_scheduler.rst | 4 +- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 222 +- .../gpu/drm/i915/gem/i915_gem_context_types.h | 6 + .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 765 ++++-- drivers/gpu/drm/i915/gt/intel_context.c | 58 +- drivers/gpu/drm/i915/gt/intel_context.h | 52 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 148 +- drivers/gpu/drm/i915/gt/intel_engine.h | 12 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 66 +- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 9 + drivers/gpu/drm/i915/gt/intel_engine_pm.h | 20 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 + .../drm/i915/gt/intel_execlists_submission.c | 68 +- drivers/gpu/drm/i915/gt/intel_gt.c | 3 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8 + drivers/gpu/drm/i915/gt/intel_gt_pm.h | 23 + .../gpu/drm/i915/gt/intel_gt_pm_unpark_work.c | 35 + .../gpu/drm/i915/gt/intel_gt_pm_unpark_work.h | 40 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 10 + drivers/gpu/drm/i915/gt/intel_lrc.c | 7 + drivers/gpu/drm/i915/gt/selftest_execlists.c | 12 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 6 +- drivers/gpu/drm/i915/gt/selftest_lrc.c | 29 +- .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc.c | 21 + drivers/gpu/drm/i915/gt/uc/intel_guc.h | 61 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 30 +- .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c | 36 + drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 10 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2312 +++++++++++++---- drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 126 + .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 180 ++ drivers/gpu/drm/i915/i915_gpu_error.c | 39 +- drivers/gpu/drm/i915/i915_query.c | 2 + drivers/gpu/drm/i915/i915_request.c | 120 +- drivers/gpu/drm/i915/i915_request.h | 40 +- drivers/gpu/drm/i915/i915_trace.h | 12 +- drivers/gpu/drm/i915/i915_vma.c | 21 +- drivers/gpu/drm/i915/i915_vma.h | 13 +- drivers/gpu/drm/i915/intel_wakeref.c | 5 + drivers/gpu/drm/i915/intel_wakeref.h | 13 + .../drm/i915/selftests/i915_live_selftests.h | 2 + drivers/gpu/drm/i915/selftests/i915_request.c | 100 + .../i915/selftests/intel_scheduler_helpers.c | 12 + .../i915/selftests/intel_scheduler_helpers.h | 2 + include/uapi/drm/i915_drm.h | 136 +- 49 files changed, 3928 insertions(+), 1099 deletions(-) delete mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_pm_unpark_work.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_pm_unpark_work.h create mode 100644 drivers/gpu/drm/i915/gt/uc/selftest_guc.c create mode 100644 drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c -- 2.32.0

4 105

[Bug 214587] New: [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx timeout, signaled seq=5900910, emitted seq=5900912
by bugzilla-daemon＠bugzilla.kernel.org 30 Sep '21

30 Sep '21

https://bugzilla.kernel.org/show_bug.cgi?id=214587 Bug ID: 214587 Summary: [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx timeout, signaled seq=5900910, emitted seq=5900912 Product: Drivers Version: 2.5 Kernel Version: 5.14.7-arch1-1 Hardware: Intel OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: samy(a)lahfa.xyz Regression: No Hi, I've just recently hit this issue on ArchLinux kernel 5.14.7-arch1-1, linux-firmware 20210919.d526e04-1 with a Thinkpad T495 AMD Ryzen 7 3700U along a Vega Radeon RX 10 while using hashcat to brute-force hashes, hashcat was using OpenCL in order to use the GPU and then the computer just froze, and a GPU reset happened see the following logs. Logs from dmesg: [87507.678904] [drm] Fence fallback timer expired on ring gfx [87512.691933] [drm] Fence fallback timer expired on ring gfx [87517.572033] [drm] Fence fallback timer expired on ring gfx [87523.012214] [drm] Fence fallback timer expired on ring gfx [87533.129069] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx timeout, signaled seq=5900910, emitted seq=5900912 [87533.129518] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process information: process Xorg pid 2937 thread Xorg:cs0 pid 3143 [87533.129957] amdgpu 0000:06:00.0: amdgpu: GPU reset begin! [87533.138994] amdgpu 0000:06:00.0: amdgpu: Guilty job already signaled, skipping HW reset [87533.139056] amdgpu 0000:06:00.0: amdgpu: GPU reset(2) succeeded! -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

1 1

[PATCH] drm/msm/a6xx: Track current ctx by seqno
by Rob Clark 30 Sep '21

30 Sep '21

From: Rob Clark <robdclark(a)chromium.org> In theory a context can be destroyed and a new one allocated at the same address, making the pointer comparision to detect when we don't need to update the current pagetables invalid. Instead assign a sequence number to each context on creation, and use this for the check. Fixes: 84c31ee16f90 ("drm/msm/a6xx: Add support for per-instance pagetables") Signed-off-by: Rob Clark <robdclark(a)chromium.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++--- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 11 ++++++++++- drivers/gpu/drm/msm/msm_drv.c | 3 +++ drivers/gpu/drm/msm/msm_drv.h | 1 + 4 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 5e1ae3df42ba..e0a8b2fd1ff0 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -106,7 +106,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, u32 asid; u64 memptr = rbmemptr(ring, ttbr0); - if (ctx == a6xx_gpu->cur_ctx) + if (ctx->seqno == a6xx_gpu->cur_ctx_seqno) return; if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) @@ -139,7 +139,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, OUT_PKT7(ring, CP_EVENT_WRITE, 1); OUT_RING(ring, 0x31); - a6xx_gpu->cur_ctx = ctx; + a6xx_gpu->cur_ctx_seqno = ctx->seqno; } static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) @@ -1081,7 +1081,7 @@ static int hw_init(struct msm_gpu *gpu) /* Always come up on rb 0 */ a6xx_gpu->cur_ring = gpu->rb[0]; - a6xx_gpu->cur_ctx = NULL; + a6xx_gpu->cur_ctx_seqno = 0; /* Enable the SQE_to start the CP engine */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 0bc2d062f54a..8e5527c881b1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -19,7 +19,16 @@ struct a6xx_gpu { uint64_t sqe_iova; struct msm_ringbuffer *cur_ring; - struct msm_file_private *cur_ctx; + + /** + * cur_ctx_seqno: + * + * The ctx->seqno value of the context with current pgtables + * installed. Tracked by seqno rather than pointer value to + * avoid dangling pointers, and cases where a ctx can be freed + * and a new one created with the same address. + */ + int cur_ctx_seqno; struct a6xx_gmu gmu; diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 624078b3adf2..30c1efc3d8a0 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -711,6 +711,7 @@ static void load_gpu(struct drm_device *dev) static int context_init(struct drm_device *dev, struct drm_file *file) { + static atomic_t ident = ATOMIC_INIT(0); struct msm_drm_private *priv = dev->dev_private; struct msm_file_private *ctx; @@ -727,6 +728,8 @@ static int context_init(struct drm_device *dev, struct drm_file *file) ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); file->driver_priv = ctx; + ctx->seqno = atomic_inc_return(&ident); + return 0; } diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index de062450add4..8633d0059a3e 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -59,6 +59,7 @@ struct msm_file_private { int queueid; struct msm_gem_address_space *aspace; struct kref ref; + int seqno; }; enum msm_mdp_plane_property { -- 2.31.1

2 2

[PATCH] drm/amd: Guard IS_OLD_GCC assignment with CONFIG_CC_IS_GCC
by Nathan Chancellor 30 Sep '21

30 Sep '21

cc-ifversion only works for GCC, as clang pretends to be GCC 4.2.1 for glibc compatibility, which means IS_OLD_GCC will get set and unsupported flags will be passed to clang when building certain code within the DCN files: clang-14: error: unknown argument: '-mpreferred-stack-boundary=4' make[5]: *** [scripts/Makefile.build:277: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.o] Error 1 Guard the call to cc-ifversion with CONFIG_CC_IS_GCC so that everything continues to work properly. See commit 00db297106e8 ("drm/amdgpu: fix stack alignment ABI mismatch for GCC 7.1+") for more context. Fixes: ff7e396f822f ("drm/amd/display: add cyan_skillfish display support") Link: https://github.com/ClangBuiltLinux/linux/issues/1468 Signed-off-by: Nathan Chancellor <nathan(a)kernel.org> --- drivers/gpu/drm/amd/display/dc/dcn201/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile index d98d69705117..96cbd4ccd344 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile @@ -14,9 +14,11 @@ ifdef CONFIG_PPC64 CFLAGS_$(AMDDALPATH)/dc/dcn201/dcn201_resource.o := -mhard-float -maltivec endif +ifdef CONFIG_CC_IS_GCC ifeq ($(call cc-ifversion, -lt, 0701, y), y) IS_OLD_GCC = 1 endif +endif ifdef CONFIG_X86 ifdef IS_OLD_GCC base-commit: b47b99e30cca8906753c83205e8c6179045dd725 -- 2.33.0.591.gddb1055343

3 2

[PATCH] drm/amd: Return NULL instead of false in dcn201_acquire_idle_pipe_for_layer()
by Nathan Chancellor 30 Sep '21

30 Sep '21

Clang warns: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:1017:10: error: expression which evaluates to zero treated as a null pointer constant of type 'struct pipe_ctx *' [-Werror,-Wnon-literal-null-conversion] return false; ^~~~~ 1 error generated. Use NULL instead of false since the function is returning a pointer rather than a boolean. Fixes: ff7e396f822f ("drm/amd/display: add cyan_skillfish display support") Link: https://github.com/ClangBuiltLinux/linux/issues/1470 Signed-off-by: Nathan Chancellor <nathan(a)kernel.org> --- drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c index aec276e1db65..8523a048e6f6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c @@ -1014,7 +1014,7 @@ static struct pipe_ctx *dcn201_acquire_idle_pipe_for_layer( ASSERT(0); if (!idle_pipe) - return false; + return NULL; idle_pipe->stream = head_pipe->stream; idle_pipe->stream_res.tg = head_pipe->stream_res.tg; base-commit: b47b99e30cca8906753c83205e8c6179045dd725 -- 2.33.0.591.gddb1055343

3 3

[PATCH v3] drm/i915/bdb: Fix version check
by Lukasz Majczak 30 Sep '21

30 Sep '21

With patch "drm/i915/vbt: Fix backlight parsing for VBT 234+" the size of bdb_lfp_backlight_data structure has been increased, causing if-statement in the parse_lfp_backlight function that comapres this structure size to the one retrieved from BDB, always to fail for older revisions. This patch calculates expected size of the structure for a given BDB version and compares it with the value gathered from BDB. Tested on Chromebook Pixelbook (Nocturne) (reports bdb->version = 221) Tested-by: Lukasz Majczak <lma(a)semihalf.com> Signed-off-by: Lukasz Majczak <lma(a)semihalf.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 22 ++++++++++++++----- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 5 +++++ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 3c25926092de..f9776ca85de3 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -451,13 +451,23 @@ parse_lfp_backlight(struct drm_i915_private *i915, } i915->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI; - if (bdb->version >= 191 && - get_blocksize(backlight_data) >= sizeof(*backlight_data)) { - const struct lfp_backlight_control_method *method; + if (bdb->version >= 191) { + size_t exp_size; - method = &backlight_data->backlight_control[panel_type]; - i915->vbt.backlight.type = method->type; - i915->vbt.backlight.controller = method->controller; + if (bdb->version >= 236) + exp_size = sizeof(struct bdb_lfp_backlight_data); + else if (bdb->version >= 234) + exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234; + else + exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191; + + if (get_blocksize(backlight_data) >= exp_size) { + const struct lfp_backlight_control_method *method; + + method = &backlight_data->backlight_control[panel_type]; + i915->vbt.backlight.type = method->type; + i915->vbt.backlight.controller = method->controller; + } } i915->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 330077c2e588..a2108a8f544d 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -814,6 +814,11 @@ struct lfp_brightness_level { u16 reserved; } __packed; +#define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \ + offsetof(struct bdb_lfp_backlight_data, brightness_level) +#define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \ + offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits) + struct bdb_lfp_backlight_data { u8 entry_size; struct lfp_backlight_data_entry data[16]; -- 2.33.0.685.g46640cef36-goog

2 1

[PATCH] drm/amd: Initialize remove_mpcc in dcn201_update_mpcc()
by Nathan Chancellor 30 Sep '21

30 Sep '21

Clang warns: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hwseq.c:505:6: error: variable 'remove_mpcc' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized] if (mpc->funcs->get_mpcc_for_dpp_from_secondary) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hwseq.c:509:6: note: uninitialized use occurs here if (remove_mpcc != NULL && mpc->funcs->remove_mpcc_from_secondary) ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hwseq.c:505:2: note: remove the 'if' if its condition is always true if (mpc->funcs->get_mpcc_for_dpp_from_secondary) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hwseq.c:442:26: note: initialize the variable 'remove_mpcc' to silence this warning struct mpcc *remove_mpcc; ^ = NULL 1 error generated. The code already handles remove_mpcc being NULL just fine so initialize it to NULL at the beginning of the function so it is never used uninitialized. Fixes: ff7e396f822f ("drm/amd/display: add cyan_skillfish display support") Link: https://github.com/ClangBuiltLinux/linux/issues/1469 Signed-off-by: Nathan Chancellor <nathan(a)kernel.org> --- drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c index ceaaeeb8f2de..cfd09b3f705e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c @@ -439,7 +439,7 @@ void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; int mpcc_id, dpp_id; struct mpcc *new_mpcc; - struct mpcc *remove_mpcc; + struct mpcc *remove_mpcc = NULL; struct mpc *mpc = dc->res_pool->mpc; struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); base-commit: 30fc33064c846df29888c3c61e30a064aad3a342 -- 2.33.0.591.gddb1055343

2 1

[PATCH v2 0/4] drm/v3d: add multiple in/out syncobjs support
by Melissa Wen 30 Sep '21

30 Sep '21

Currently, v3d only supports single in/out syncobj per submission (in v3d_submit_cl, there are two in_sync, one for bin and another for render job); however, Vulkan queue submit operations expect multiples wait and signal semaphores. This series extends v3d interface and job dependency operations to handle more than one in/out syncobj. This version differs from the previous one by adding a prep work patch that synthesizes job memory allocation and initialization into a single function. Also, the design for ioctl extensions changed to subclass drm_v3d_extension (generic type) as base element of any specific extension (here is drm_v3d_multisync). Finally, in the multisync extension, flags was replaced by wait_stage and it uses v3d_queue to define sync stage (i.e. which queue to add wait semaphores) The first patch just decouples the steps to lookup and add job dependency from the job init code, since the operation repeats for every syncobj that a job should wait before starting. So, the fourth patch of this series will reuse it to handle multiples wait for semaphores. The second patch moves job memory allocation to v3d_job_init() for any type of v3d_job-based job. The main goal is to prevent errors when handling job initialization failures (doing a proper cleanup). The third patch extends our interface by using a generic extension. This approach was inspired by i915_user_extension[1] and amd_cs_chunks[2] to give a little more flexibility in adding other submission features in the future. Therefore, the list of extensions would work as a hub of features that use an id to determine the corresponding feature data type. With this base, the fourth patch adds multiple wait/signal semaphores support. For this, we add to the list of the generic extensions a new data type (drm_v3d_multi_sync) that points to two arrays of syncobjs (in/out) and also determines (wait_stage) the job to add wait dependencies (v3d_queue). An auxiliary struct (v3d_submit_ext) is used when parsing submission extensions. Finally, we reserve some space in the semaphore struct (drm_v3d_sem) to accommodate timeline semaphores that we aim to add support soon (same reason for already defining v3d_submit_outsync). [1] https://cgit.freedesktop.org/drm/drm-misc/commit/drivers/gpu/drm/i915/i915_… [2] https://cgit.freedesktop.org/drm/drm-misc/tree/include/uapi/drm/amdgpu_drm.… In the mesa side, the work related to this series is in progress at https://gitlab.freedesktop.org/mwen/mesa/-/commit/6c340bb35203a0418af87a792… v2: - move job mem alloc to v3d_job_init (Iago) - simplify and subclass the generic extension struct (Daniel) - make job dependency conditions more understandable (Iago) Melissa Wen (4): drm/v3d: decouple adding job dependencies steps from job init drm/v3d: alloc and init job in one shot drm/v3d: add generic ioctl extension drm/v3d: add multiple syncobjs support drivers/gpu/drm/v3d/v3d_drv.c | 10 +- drivers/gpu/drm/v3d/v3d_drv.h | 23 ++- drivers/gpu/drm/v3d/v3d_gem.c | 360 +++++++++++++++++++++++++--------- include/uapi/drm/v3d_drm.h | 78 ++++++++ 4 files changed, 368 insertions(+), 103 deletions(-) -- 2.30.2

2 12

← Newer
1
...
22
23
24
25
26
27
28
...
82
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel September 2021