dri-devel September 2021

dri-devel@lists.freedesktop.org

348 participants
817 discussions

[PATCH] drm: panel: tl070wsh30: Add a single error handling block at the end of the function.
by Cai Huoqing 07 Sep '21

07 Sep '21

A single error handling block at the end of the function could be brought in to make code a little more concise. Signed-off-by: Cai Huoqing <caihuoqing(a)baidu.com> --- drivers/gpu/drm/panel/panel-tdo-tl070wsh30.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-tdo-tl070wsh30.c b/drivers/gpu/drm/panel/panel-tdo-tl070wsh30.c index 820731be7147..5e54ef4b3a9c 100644 --- a/drivers/gpu/drm/panel/panel-tdo-tl070wsh30.c +++ b/drivers/gpu/drm/panel/panel-tdo-tl070wsh30.c @@ -59,8 +59,7 @@ static int tdo_tl070wsh30_panel_prepare(struct drm_panel *panel) err = mipi_dsi_dcs_exit_sleep_mode(tdo_tl070wsh30->link); if (err < 0) { dev_err(panel->dev, "failed to exit sleep mode: %d\n", err); - regulator_disable(tdo_tl070wsh30->supply); - return err; + goto err_disable_reg; } msleep(200); @@ -68,8 +67,7 @@ static int tdo_tl070wsh30_panel_prepare(struct drm_panel *panel) err = mipi_dsi_dcs_set_display_on(tdo_tl070wsh30->link); if (err < 0) { dev_err(panel->dev, "failed to set display on: %d\n", err); - regulator_disable(tdo_tl070wsh30->supply); - return err; + goto err_disable_reg; } msleep(20); @@ -77,6 +75,9 @@ static int tdo_tl070wsh30_panel_prepare(struct drm_panel *panel) tdo_tl070wsh30->prepared = true; return 0; +err_disable_reg: + regulator_disable(tdo_tl070wsh30->supply); + return err; } static int tdo_tl070wsh30_panel_unprepare(struct drm_panel *panel) -- 2.25.1

1 0

[PATCH] backlight: l4f00242t03: Add a single error handling block at the end of the function.
by Cai Huoqing 07 Sep '21

07 Sep '21

A single error handling block at the end of the function could be brought in to make code a little more concise. Signed-off-by: Cai Huoqing <caihuoqing(a)baidu.com> --- drivers/video/backlight/l4f00242t03.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/video/backlight/l4f00242t03.c b/drivers/video/backlight/l4f00242t03.c index 46f97d1c3d21..c6f540f1b507 100644 --- a/drivers/video/backlight/l4f00242t03.c +++ b/drivers/video/backlight/l4f00242t03.c @@ -65,14 +65,12 @@ static void l4f00242t03_lcd_init(struct spi_device *spi) ret = regulator_set_voltage(priv->core_reg, 2800000, 2800000); if (ret) { dev_err(&spi->dev, "failed to set the core regulator voltage.\n"); - regulator_disable(priv->io_reg); - return; + goto err_disable_reg; } ret = regulator_enable(priv->core_reg); if (ret) { dev_err(&spi->dev, "failed to enable the core regulator.\n"); - regulator_disable(priv->io_reg); - return; + goto err_disable_reg; } l4f00242t03_reset(priv->reset); @@ -80,6 +78,10 @@ static void l4f00242t03_lcd_init(struct spi_device *spi) gpiod_set_value(priv->enable, 1); msleep(60); spi_write(spi, (const u8 *)cmd, ARRAY_SIZE(cmd) * sizeof(u16)); + return; + +err_disable_reg: + regulator_disable(priv->io_reg); } static void l4f00242t03_lcd_powerdown(struct spi_device *spi) -- 2.25.1

1 0

[PATCH v2] drm/tidss: Make use of the helper macro SET_RUNTIME_PM_OPS()
by Cai Huoqing 07 Sep '21

07 Sep '21

Use the helper macro SET_RUNTIME_PM_OPS() instead of the verbose operators ".runtime_suspend/.runtime_resume", because the SET_RUNTIME_PM_OPS() is a nice helper macro that could be brought in to make code a little more concise. Signed-off-by: Cai Huoqing <caihuoqing(a)baidu.com> --- v1->v2: *Remove "#ifdef CONFIG_PM" around around runtime_suspend|resume(). *Make use of pm_ptr() in the assignment in tidss_platform_driver. v1 comments link: https://www.spinics.net/lists/dri-devel/msg313178.html drivers/gpu/drm/tidss/tidss_drv.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tidss_drv.c index d620f35688da..4366b5c798e0 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -88,16 +88,11 @@ static int __maybe_unused tidss_resume(struct device *dev) return drm_mode_config_helper_resume(&tidss->ddev); } -#ifdef CONFIG_PM - static const struct dev_pm_ops tidss_pm_ops = { - .runtime_suspend = tidss_pm_runtime_suspend, - .runtime_resume = tidss_pm_runtime_resume, SET_SYSTEM_SLEEP_PM_OPS(tidss_suspend, tidss_resume) + SET_RUNTIME_PM_OPS(tidss_pm_runtime_suspend, tidss_pm_runtime_resume, NULL) }; -#endif /* CONFIG_PM */ - /* DRM device Information */ static void tidss_release(struct drm_device *ddev) @@ -250,9 +245,7 @@ static struct platform_driver tidss_platform_driver = { .shutdown = tidss_shutdown, .driver = { .name = "tidss", -#ifdef CONFIG_PM - .pm = &tidss_pm_ops, -#endif + .pm = pm_ptr(&tidss_pm_ops), .of_match_table = tidss_of_table, .suppress_bind_attrs = true, }, -- 2.25.1

1 0

[drm:i915-display-struct-refactor 22/25] drivers/gpu/drm/i915/gvt/handlers.c:510:34: error: no member named 'dpll' in 'struct drm_i915_private'
by kernel test robot 07 Sep '21

07 Sep '21

tree: git://people.freedesktop.org/~airlied/linux.git i915-display-struct-refactor head: e183b125871ffdd77b6de15a963e6fc8a47173c9 commit: 5b99cab055595d1b12d7425e560b5a9fcd15c9a3 [22/25] drm/i915/display: move dpll struct into display config: x86_64-randconfig-a016-20210906 (attached as .config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 6fe2beba7d2a41964af658c8c59dd172683ef739) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git remote add drm git://people.freedesktop.org/~airlied/linux.git git fetch --no-tags drm i915-display-struct-refactor git checkout 5b99cab055595d1b12d7425e560b5a9fcd15c9a3 # save the attached .config to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com> All errors (new ones prefixed by >>): >> drivers/gpu/drm/i915/gvt/handlers.c:510:34: error: no member named 'dpll' in 'struct drm_i915_private' refclk = vgpu->gvt->gt->i915->dpll.ref_clks.ssc; ~~~~~~~~~~~~~~~~~~~ ^ drivers/gpu/drm/i915/gvt/handlers.c:541:36: error: no member named 'dpll' in 'struct drm_i915_private' int refclk = vgpu->gvt->gt->i915->dpll.ref_clks.nssc; ~~~~~~~~~~~~~~~~~~~ ^ 2 errors generated. vim +510 drivers/gpu/drm/i915/gvt/handlers.c 04d348ae3f0aea Zhi Wang 2016-04-25 446 6a4500c7b83f9e Colin Xu 2021-02-26 447 /* 6a4500c7b83f9e Colin Xu 2021-02-26 448 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to 6a4500c7b83f9e Colin Xu 2021-02-26 449 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on 6a4500c7b83f9e Colin Xu 2021-02-26 450 * setup_virtual_dp_monitor(). 6a4500c7b83f9e Colin Xu 2021-02-26 451 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled 6a4500c7b83f9e Colin Xu 2021-02-26 452 * DPLL. Later guest driver may setup a different DPLLx when setting mode. 6a4500c7b83f9e Colin Xu 2021-02-26 453 * So the correct sequence to find DP stream clock is: 6a4500c7b83f9e Colin Xu 2021-02-26 454 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x. 6a4500c7b83f9e Colin Xu 2021-02-26 455 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate. 6a4500c7b83f9e Colin Xu 2021-02-26 456 * Then Refresh rate then can be calculated based on follow equations: 6a4500c7b83f9e Colin Xu 2021-02-26 457 * Pixel clock = h_total * v_total * refresh_rate 6a4500c7b83f9e Colin Xu 2021-02-26 458 * stream clock = Pixel clock 6a4500c7b83f9e Colin Xu 2021-02-26 459 * ls_clk = DP bitrate 6a4500c7b83f9e Colin Xu 2021-02-26 460 * Link M/N = strm_clk / ls_clk 6a4500c7b83f9e Colin Xu 2021-02-26 461 */ 6a4500c7b83f9e Colin Xu 2021-02-26 462 6a4500c7b83f9e Colin Xu 2021-02-26 463 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 6a4500c7b83f9e Colin Xu 2021-02-26 464 { 6a4500c7b83f9e Colin Xu 2021-02-26 465 u32 dp_br = 0; 6a4500c7b83f9e Colin Xu 2021-02-26 466 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); 6a4500c7b83f9e Colin Xu 2021-02-26 467 6a4500c7b83f9e Colin Xu 2021-02-26 468 switch (ddi_pll_sel) { 6a4500c7b83f9e Colin Xu 2021-02-26 469 case PORT_CLK_SEL_LCPLL_2700: 6a4500c7b83f9e Colin Xu 2021-02-26 470 dp_br = 270000 * 2; 6a4500c7b83f9e Colin Xu 2021-02-26 471 break; 6a4500c7b83f9e Colin Xu 2021-02-26 472 case PORT_CLK_SEL_LCPLL_1350: 6a4500c7b83f9e Colin Xu 2021-02-26 473 dp_br = 135000 * 2; 6a4500c7b83f9e Colin Xu 2021-02-26 474 break; 6a4500c7b83f9e Colin Xu 2021-02-26 475 case PORT_CLK_SEL_LCPLL_810: 6a4500c7b83f9e Colin Xu 2021-02-26 476 dp_br = 81000 * 2; 6a4500c7b83f9e Colin Xu 2021-02-26 477 break; 6a4500c7b83f9e Colin Xu 2021-02-26 478 case PORT_CLK_SEL_SPLL: 6a4500c7b83f9e Colin Xu 2021-02-26 479 { 6a4500c7b83f9e Colin Xu 2021-02-26 480 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { 6a4500c7b83f9e Colin Xu 2021-02-26 481 case SPLL_FREQ_810MHz: 6a4500c7b83f9e Colin Xu 2021-02-26 482 dp_br = 81000 * 2; 6a4500c7b83f9e Colin Xu 2021-02-26 483 break; 6a4500c7b83f9e Colin Xu 2021-02-26 484 case SPLL_FREQ_1350MHz: 6a4500c7b83f9e Colin Xu 2021-02-26 485 dp_br = 135000 * 2; 6a4500c7b83f9e Colin Xu 2021-02-26 486 break; 6a4500c7b83f9e Colin Xu 2021-02-26 487 case SPLL_FREQ_2700MHz: 6a4500c7b83f9e Colin Xu 2021-02-26 488 dp_br = 270000 * 2; 6a4500c7b83f9e Colin Xu 2021-02-26 489 break; 6a4500c7b83f9e Colin Xu 2021-02-26 490 default: 6a4500c7b83f9e Colin Xu 2021-02-26 491 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n", 6a4500c7b83f9e Colin Xu 2021-02-26 492 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); 6a4500c7b83f9e Colin Xu 2021-02-26 493 break; 6a4500c7b83f9e Colin Xu 2021-02-26 494 } 6a4500c7b83f9e Colin Xu 2021-02-26 495 break; 6a4500c7b83f9e Colin Xu 2021-02-26 496 } 6a4500c7b83f9e Colin Xu 2021-02-26 497 case PORT_CLK_SEL_WRPLL1: 6a4500c7b83f9e Colin Xu 2021-02-26 498 case PORT_CLK_SEL_WRPLL2: 6a4500c7b83f9e Colin Xu 2021-02-26 499 { 6a4500c7b83f9e Colin Xu 2021-02-26 500 u32 wrpll_ctl; 6a4500c7b83f9e Colin Xu 2021-02-26 501 int refclk, n, p, r; 6a4500c7b83f9e Colin Xu 2021-02-26 502 6a4500c7b83f9e Colin Xu 2021-02-26 503 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1) 6a4500c7b83f9e Colin Xu 2021-02-26 504 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); 6a4500c7b83f9e Colin Xu 2021-02-26 505 else 6a4500c7b83f9e Colin Xu 2021-02-26 506 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2)); 6a4500c7b83f9e Colin Xu 2021-02-26 507 6a4500c7b83f9e Colin Xu 2021-02-26 508 switch (wrpll_ctl & WRPLL_REF_MASK) { 6a4500c7b83f9e Colin Xu 2021-02-26 509 case WRPLL_REF_PCH_SSC: 6a4500c7b83f9e Colin Xu 2021-02-26 @510 refclk = vgpu->gvt->gt->i915->dpll.ref_clks.ssc; 6a4500c7b83f9e Colin Xu 2021-02-26 511 break; 6a4500c7b83f9e Colin Xu 2021-02-26 512 case WRPLL_REF_LCPLL: 6a4500c7b83f9e Colin Xu 2021-02-26 513 refclk = 2700000; 6a4500c7b83f9e Colin Xu 2021-02-26 514 break; 6a4500c7b83f9e Colin Xu 2021-02-26 515 default: 6a4500c7b83f9e Colin Xu 2021-02-26 516 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n", 6a4500c7b83f9e Colin Xu 2021-02-26 517 vgpu->id, port_name(port), wrpll_ctl); 6a4500c7b83f9e Colin Xu 2021-02-26 518 goto out; 6a4500c7b83f9e Colin Xu 2021-02-26 519 } 6a4500c7b83f9e Colin Xu 2021-02-26 520 6a4500c7b83f9e Colin Xu 2021-02-26 521 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK; 6a4500c7b83f9e Colin Xu 2021-02-26 522 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 6a4500c7b83f9e Colin Xu 2021-02-26 523 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 6a4500c7b83f9e Colin Xu 2021-02-26 524 6a4500c7b83f9e Colin Xu 2021-02-26 525 dp_br = (refclk * n / 10) / (p * r) * 2; 6a4500c7b83f9e Colin Xu 2021-02-26 526 break; 6a4500c7b83f9e Colin Xu 2021-02-26 527 } 6a4500c7b83f9e Colin Xu 2021-02-26 528 default: 6a4500c7b83f9e Colin Xu 2021-02-26 529 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", 6a4500c7b83f9e Colin Xu 2021-02-26 530 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); 6a4500c7b83f9e Colin Xu 2021-02-26 531 break; 6a4500c7b83f9e Colin Xu 2021-02-26 532 } 6a4500c7b83f9e Colin Xu 2021-02-26 533 6a4500c7b83f9e Colin Xu 2021-02-26 534 out: 6a4500c7b83f9e Colin Xu 2021-02-26 535 return dp_br; 6a4500c7b83f9e Colin Xu 2021-02-26 536 } 6a4500c7b83f9e Colin Xu 2021-02-26 537 :::::: The code at line 510 was first introduced by commit :::::: 6a4500c7b83f9e4470dd20cf89f691abd132d090 drm/i915/gvt: Get accurate vGPU virtual display refresh rate from vreg :::::: TO: Colin Xu <colin.xu(a)intel.com> :::::: CC: Zhenyu Wang <zhenyuw(a)linux.intel.com> --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

1 0

[PATCH v2 0/2] Fix a hung during memory pressure test
by xinhui pan 07 Sep '21

07 Sep '21

A long time ago, someone reports system got hung during memory test. In recent days, I am trying to look for or understand the potential deadlock in ttm/amdgpu code. This patchset aims to fix the deadlock during ttm populate. TTM has a parameter called pages_limit, when allocated GTT memory reaches this limit, swapout would be triggered. As ttm_bo_swapout does not return the correct retval, populate might get hung. UVD ib test uses GTT which might be insufficient. So a gpu recovery would hung if populate hung. I have made one drm test which alloc two GTT BOs, submit gfx copy commands and free these BOs without waiting fence. What's more, these gfx copy commands will cause gfx ring hang. So gpu recovery would be triggered. Now here is one possible deadlock case. gpu_recovery -> stop drm scheduler -> asic reset -> ib test -> tt populate (uvd ib test) -> ttm_bo_swapout (BO A) // this always fails as the fence of BO A would not be signaled by schedluer or HW. Hit deadlock. I paste the drm test patch below. #modprobe ttm pages_limit=65536 #amdgpu_test -s 1 -t 4 --- tests/amdgpu/basic_tests.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index dbf02fee..f85ed340 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -65,13 +65,16 @@ static void amdgpu_direct_gma_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type); -static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, +static void _amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, unsigned ip_type, int instance, int pm4_dw, uint32_t *pm4_src, int res_cnt, amdgpu_bo_handle *resources, struct amdgpu_cs_ib_info *ib_info, - struct amdgpu_cs_request *ibs_request); + struct amdgpu_cs_request *ibs_request, int sync, int repeat); +#define amdgpu_test_exec_cs_helper(...) \ + _amdgpu_test_exec_cs_helper(__VA_ARGS__, 1, 1) + CU_TestInfo basic_tests[] = { { "Query Info Test", amdgpu_query_info_test }, { "Userptr Test", amdgpu_userptr_test }, @@ -1341,12 +1344,12 @@ static void amdgpu_command_submission_compute(void) * pm4_src, resources, ib_info, and ibs_request * submit command stream described in ibs_request and wait for this IB accomplished */ -static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, +static void _amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, unsigned ip_type, int instance, int pm4_dw, uint32_t *pm4_src, int res_cnt, amdgpu_bo_handle *resources, struct amdgpu_cs_ib_info *ib_info, - struct amdgpu_cs_request *ibs_request) + struct amdgpu_cs_request *ibs_request, int sync, int repeat) { int r; uint32_t expired; @@ -1395,12 +1398,15 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, CU_ASSERT_NOT_EQUAL(ibs_request, NULL); /* submit CS */ - r = amdgpu_cs_submit(context_handle, 0, ibs_request, 1); + while (repeat--) + r = amdgpu_cs_submit(context_handle, 0, ibs_request, 1); CU_ASSERT_EQUAL(r, 0); r = amdgpu_bo_list_destroy(ibs_request->resources); CU_ASSERT_EQUAL(r, 0); + if (!sync) + return; fence_status.ip_type = ip_type; fence_status.ip_instance = 0; fence_status.ring = ibs_request->ring; @@ -1667,7 +1673,7 @@ static void amdgpu_command_submission_sdma_const_fill(void) static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) { - const int sdma_write_length = 1024; + const int sdma_write_length = (255) << 20; const int pm4_dw = 256; amdgpu_context_handle context_handle; amdgpu_bo_handle bo1, bo2; @@ -1715,8 +1721,6 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) &bo1_va_handle); CU_ASSERT_EQUAL(r, 0); - /* set bo1 */ - memset((void*)bo1_cpu, 0xaa, sdma_write_length); /* allocate UC bo2 for sDMA use */ r = amdgpu_bo_alloc_and_map(device_handle, @@ -1727,8 +1731,6 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) &bo2_va_handle); CU_ASSERT_EQUAL(r, 0); - /* clear bo2 */ - memset((void*)bo2_cpu, 0, sdma_write_length); resources[0] = bo1; resources[1] = bo2; @@ -1785,17 +1787,11 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) } } - amdgpu_test_exec_cs_helper(context_handle, + _amdgpu_test_exec_cs_helper(context_handle, ip_type, ring_id, i, pm4, 2, resources, - ib_info, ibs_request); - - /* verify if SDMA test result meets with expected */ - i = 0; - while(i < sdma_write_length) { - CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa); - } + ib_info, ibs_request, 0, 100); r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc, sdma_write_length); CU_ASSERT_EQUAL(r, 0); -- *** BLURB HERE *** xinhui pan (2): drm/ttm: Fix a deadlock if the target BO is not idle during swap drm/amdpgu: Use VRAM domain in UVD IB test drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 8 ++++++++ drivers/gpu/drm/ttm/ttm_bo.c | 6 +++--- 2 files changed, 11 insertions(+), 3 deletions(-) -- 2.25.1

4 8

[PATCH v2 6/6] drm/fourcc: Add the ADL-P specific pitch requirements of CCS modifiers
by Imre Deak 06 Sep '21

06 Sep '21

On Alderlake-P for all CCS modifiers the main surface pitch must be either 8 Y-tile width or the multiple of 16 Y-tile widths. The CCS surface pitch must be rounded up to power-of-two. Adjust the modifier descriptions accordingly. Cc: Nanley G Chery <nanley.g.chery(a)intel.com> Cc: Juha-Pekka Heikkila <juhapekka.heikkila(a)gmail.com> Cc: dri-devel(a)lists.freedesktop.org Signed-off-by: Imre Deak <imre.deak(a)intel.com> --- include/uapi/drm/drm_fourcc.h | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 45a914850be0d..b63b7fa8bbac6 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -522,8 +522,16 @@ extern "C" { * The main surface is Y-tiled and at plane index 0, the CCS is linear and * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in * main surface. In other words, 4 bits in CCS map to a main surface cache - * line pair. The main surface pitch is required to be a multiple of four - * Y-tile widths. + * line pair. + * + * The pitch of the main surface is required to be either 8 or a multiple of + * 16 Y-tile widths on Alderlake-P and a multiple of 4 Y-tile widths on other + * platforms. + * + * The pitch of the CCS surface must be calculated using the + * ccs_surface_pitch=main_surface_pitch_in_bytes / 512 * 64. + * formula. On Alderlake-P this pitch must be rounded up to be power-of-two + * sized. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) @@ -533,10 +541,12 @@ extern "C" { * The main surface is Y-tiled and at plane index 0, the CCS is linear and * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in * main surface. In other words, 4 bits in CCS map to a main surface cache - * line pair. The main surface pitch is required to be a multiple of four - * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the + * line pair. For semi-planar formats like NV12, CCS planes follow the * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, * planes 2 and 3 for the respective CCS. + * + * About the requirement on the main and CCS surface pitches see the + * description for I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) @@ -554,8 +564,10 @@ extern "C" { * Clear Color value when applicable. The Converted Clear Color values are * consumed by the DE. The last 64 bits are used to store Color Discard Enable * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line - * corresponds to an area of 4x1 tiles in the main surface. The main surface - * pitch is required to be a multiple of 4 tile widths. + * corresponds to an area of 4x1 tiles in the main surface. + * + * About the requirement on the main and CCS surface pitches see the + * description for I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) -- 2.27.0

1 0

[PATCH] drm/i915/selftests: fixup igt_shrink_thp
by Matthew Auld 06 Sep '21

06 Sep '21

Since the object might still be active here, the shrink_all will simply ignore it, which blows up in the test, since the pages will still be there. Currently THP is disabled which should result in the test being skipped, but if we ever re-enable THP we might start seeing the failure. Fix this by forcing I915_SHRINK_ACTIVE. v2: Some machine in the shard runs doesn't seem to have any available swap when running this test. Try to handle this. Signed-off-by: Matthew Auld <matthew.auld(a)intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Cc: Thomas Hellström <thomas.hellstrom(a)linux.intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> #v1 --- .../gpu/drm/i915/gem/selftests/huge_pages.c | 31 ++++++++++++++----- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c index a094f3ce1a90..46ea1997c114 100644 --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c @@ -1519,6 +1519,7 @@ static int igt_shrink_thp(void *arg) struct i915_vma *vma; unsigned int flags = PIN_USER; unsigned int n; + bool should_swap; int err = 0; /* @@ -1567,23 +1568,39 @@ static int igt_shrink_thp(void *arg) break; } i915_gem_context_unlock_engines(ctx); + /* + * Nuke everything *before* we unpin the pages so we can be reasonably + * sure that when later checking get_nr_swap_pages() that some random + * leftover object doesn't steal the remaining swap space. + */ + i915_gem_shrink(NULL, i915, -1UL, NULL, + I915_SHRINK_BOUND | + I915_SHRINK_UNBOUND | + I915_SHRINK_ACTIVE); i915_vma_unpin(vma); if (err) goto out_put; + /* - * Now that the pages are *unpinned* shrink-all should invoke - * shmem to truncate our pages. + * Now that the pages are *unpinned* shrinking should invoke + * shmem to truncate our pages, if we have available swap. */ - i915_gem_shrink_all(i915); - if (i915_gem_object_has_pages(obj)) { - pr_err("shrink-all didn't truncate the pages\n"); + should_swap = get_nr_swap_pages() > 0; + i915_gem_shrink(NULL, i915, -1UL, NULL, + I915_SHRINK_BOUND | + I915_SHRINK_UNBOUND | + I915_SHRINK_ACTIVE); + if (should_swap == i915_gem_object_has_pages(obj)) { + pr_err("unexpected pages mismatch, should_swap=%s\n", + yesno(should_swap)); err = -EINVAL; goto out_put; } - if (obj->mm.page_sizes.sg || obj->mm.page_sizes.phys) { - pr_err("residual page-size bits left\n"); + if (should_swap == (obj->mm.page_sizes.sg || obj->mm.page_sizes.phys)) { + pr_err("unexpected residual page-size bits, should_swap=%s\n", + yesno(should_swap)); err = -EINVAL; goto out_put; } -- 2.26.3

2 5

[diagnostic TDR mode patches] unify our solution opinions/suggestions in one thread
by Liu, Monk 06 Sep '21

06 Sep '21

[AMD Official Use Only] Hi Daniel/Christian/Andrey It looks the voice from you three are spread over those email floods to me, the feature we are working on (diagnostic TDR scheme) is pending there for more than 6 month (we started it from feb 2021). Honestly speaking the email ways that we are using now is not friendly and quite painful to me .... Can we try to put all our opinions, suggestions, or even objects here together, let's go through them one by one, it's too hard for us to reply each email on different questions . For [PATCH 1/2] drm/sched: fix the bug of time out calculation(v4) This is a fixing patch on the timeout timer in scheduler, can we complete this one first ? it should already resolved all the questions and suggestions. For [PATCH 2/2] drm/sched: serialize job_timeout and scheduler I think I already explained the questions raised by Daniel in other thread , regarding why I use __kthread_should_park() For other aspects, can we put all our opinion synthesized here ? Thanks ! ------------------------------------------ Monk Liu | Cloud-GPU Core team ------------------------------------------

8 18

[Bug 107381] New: radeon VCE init error (-110) -- AMD/Intel Mars Hybrid Graphics
by bugzilla-daemon＠bugzilla.kernel.org 06 Sep '21

06 Sep '21

https://bugzilla.kernel.org/show_bug.cgi?id=107381 Bug ID: 107381 Summary: radeon VCE init error (-110) -- AMD/Intel Mars Hybrid Graphics Product: Drivers Version: 2.5 Kernel Version: 4.3 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: schmod(a)gmail.com Regression: No Created attachment 192261 --> https://bugzilla.kernel.org/attachment.cgi?id=192261&action=edit dmesg output Since upgrading to Ubuntu 15.10, I have encountered graphics performance issues, and have occasionally experienced lockups during boot. I have encountered this issue on kernel 4.2.0 and 4.3.0, and it seems to have affected users on other distributions as well: https://bugs.launchpad.net/fedora/+source/linux/+bug/1512848 https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=803087 https://bugzilla.redhat.com/show_bug.cgi?id=1262649 Notably, this issue seems to primarily impact users with The ATI "Mars" chipset, on machines that have an Intel/AMD hybrid graphics hardware configuration. This shows up in dmesg (full log attached, because there's a fair amount of seemingly-useful context): [ 4.917369] radeon 0000:01:00.0: VCE init error (-110). Some other context from my PC: $ xrandr --listproviders Providers: number : 3 Provider 0: id: 0x6a cap: 0x9, Source Output, Sink Offload crtcs: 4 outputs: 5 associated providers: 2 name:Intel Provider 1: id: 0x41 cap: 0x6, Sink Output, Source Offload crtcs: 2 outputs: 0 associated providers: 2 name:radeon Provider 2: id: 0x41 cap: 0x6, Sink Output, Source Offload crtcs: 2 outputs: 0 associated providers: 2 name:radeon $ lspci -k (trimmed to omit likely-irrelevant devices) 00:00.0 Host bridge: Intel Corporation 3rd Gen Core processor DRAM Controller (rev 09) Subsystem: Samsung Electronics Co Ltd Device c0e6 Kernel driver in use: ivb_uncore 00:01.0 PCI bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port (rev 09) Kernel driver in use: pcieport 00:02.0 VGA compatible controller: Intel Corporation 3rd Gen Core processor Graphics Controller (rev 09) DeviceName: Onboard IGD Subsystem: Samsung Electronics Co Ltd Device c0e6 Kernel driver in use: i915 01:00.0 Display controller: Advanced Micro Devices, Inc. [AMD/ATI] Mars [Radeon HD 8670A/8670M/8750M] (rev ff) Kernel driver in use: radeon -- You are receiving this mail because: You are watching the assignee of the bug.

1 23

[PATCH] drm/msm: Remove initialization of static variables
by zhaoxiao 06 Sep '21

06 Sep '21

Address the following checkpatch errors: ERROR: do not initialise statics to false FILE: :drivers/gpu/drm/msm/msm_drv.c:21: -static bool reglog = false; FILE: :drivers/gpu/drm/msm/msm_drv.c:31: -bool dumpstate = false; Signed-off-by: zhaoxiao <long870912(a)gmail.com> --- drivers/gpu/drm/msm/msm_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 9b8fa2ad0d84..d9ca4bc9620b 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -59,7 +59,7 @@ static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { }; #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING -static bool reglog = false; +static bool reglog; MODULE_PARM_DESC(reglog, "Enable register read/write logging"); module_param(reglog, bool, 0600); #else @@ -76,7 +76,7 @@ static char *vram = "16m"; MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); module_param(vram, charp, 0); -bool dumpstate = false; +bool dumpstate; MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); module_param(dumpstate, bool, 0600); -- 2.20.1

1 0

← Newer
1
...
71
72
73
74
75
76
77
...
82
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel September 2021