dri-devel September 2021

dri-devel@lists.freedesktop.org

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817 discussions

[PATCH 2/2] drm/amdpgu: Use VRAM domain in UVD IB test
by Pan, Xinhui 03 Sep '21

03 Sep '21

Like vce/vcn does, visible VRAM is ok for ib test. And in ib test stage, VRAM is sufficient. Signed-off-by: xinhui pan <xinhui.pan(a)amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index d451c359606a..1c099b79d12c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -1178,7 +1178,7 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, int r, i; r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_DOMAIN_VRAM, &bo, NULL, (void **)&msg); if (r) return r; @@ -1210,7 +1210,7 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, int r, i; r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_DOMAIN_VRAM, &bo, NULL, (void **)&msg); if (r) return r; -- 2.25.1

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[PATCH 0/2] Fix a hung during memory pressure test
by Pan, Xinhui 03 Sep '21

03 Sep '21

A long time ago, someone reports system got hung during memory test. In recent days, I am trying to look for or understand the potential deadlock in ttm/amdgpu code. This patchset aims to fix the deadlock during ttm populate. TTM has a parameter called pages_limit, when allocated GTT memory reaches this limit, swapout would be triggered. As ttm_bo_swapout does not return the correct retval, populate might get hung. UVD ib test uses GTT which might be insufficient. So a gpu recovery would hung if populate hung. I have made one drm test which alloc two GTT BOs, submit gfx copy commands and free these BOs without waiting fence. What's more, these gfx copy commands will cause gfx ring hang. So gpu recovery would be triggered. Now here is one possible deadlock case. gpu_recovery -> stop drm scheduler -> asic reset -> ib test -> tt populate (uvd ib test) -> ttm_bo_swapout (BO A) // this always fails as the fence of BO A would not be signaled by schedluer or HW. Hit deadlock. I paste the drm test patch below. Try it with modprobe ttm pages_limit=65536 --- tests/amdgpu/basic_tests.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index dbf02fee..f85ed340 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -65,13 +65,16 @@ static void amdgpu_direct_gma_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type); -static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, +static void _amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, unsigned ip_type, int instance, int pm4_dw, uint32_t *pm4_src, int res_cnt, amdgpu_bo_handle *resources, struct amdgpu_cs_ib_info *ib_info, - struct amdgpu_cs_request *ibs_request); + struct amdgpu_cs_request *ibs_request, int sync, int repeat); +#define amdgpu_test_exec_cs_helper(...) \ + _amdgpu_test_exec_cs_helper(__VA_ARGS__, 1, 1) + CU_TestInfo basic_tests[] = { { "Query Info Test", amdgpu_query_info_test }, { "Userptr Test", amdgpu_userptr_test }, @@ -1341,12 +1344,12 @@ static void amdgpu_command_submission_compute(void) * pm4_src, resources, ib_info, and ibs_request * submit command stream described in ibs_request and wait for this IB accomplished */ -static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, +static void _amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, unsigned ip_type, int instance, int pm4_dw, uint32_t *pm4_src, int res_cnt, amdgpu_bo_handle *resources, struct amdgpu_cs_ib_info *ib_info, - struct amdgpu_cs_request *ibs_request) + struct amdgpu_cs_request *ibs_request, int sync, int repeat) { int r; uint32_t expired; @@ -1395,12 +1398,15 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, CU_ASSERT_NOT_EQUAL(ibs_request, NULL); /* submit CS */ - r = amdgpu_cs_submit(context_handle, 0, ibs_request, 1); + while (repeat--) + r = amdgpu_cs_submit(context_handle, 0, ibs_request, 1); CU_ASSERT_EQUAL(r, 0); r = amdgpu_bo_list_destroy(ibs_request->resources); CU_ASSERT_EQUAL(r, 0); + if (!sync) + return; fence_status.ip_type = ip_type; fence_status.ip_instance = 0; fence_status.ring = ibs_request->ring; @@ -1667,7 +1673,7 @@ static void amdgpu_command_submission_sdma_const_fill(void) static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) { - const int sdma_write_length = 1024; + const int sdma_write_length = (255) << 20; const int pm4_dw = 256; amdgpu_context_handle context_handle; amdgpu_bo_handle bo1, bo2; @@ -1715,8 +1721,6 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) &bo1_va_handle); CU_ASSERT_EQUAL(r, 0); - /* set bo1 */ - memset((void*)bo1_cpu, 0xaa, sdma_write_length); /* allocate UC bo2 for sDMA use */ r = amdgpu_bo_alloc_and_map(device_handle, @@ -1727,8 +1731,6 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) &bo2_va_handle); CU_ASSERT_EQUAL(r, 0); - /* clear bo2 */ - memset((void*)bo2_cpu, 0, sdma_write_length); resources[0] = bo1; resources[1] = bo2; @@ -1785,17 +1787,11 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) } } - amdgpu_test_exec_cs_helper(context_handle, + _amdgpu_test_exec_cs_helper(context_handle, ip_type, ring_id, i, pm4, 2, resources, - ib_info, ibs_request); - - /* verify if SDMA test result meets with expected */ - i = 0; - while(i < sdma_write_length) { - CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa); - } + ib_info, ibs_request, 0, 100); r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc, sdma_write_length); CU_ASSERT_EQUAL(r, 0); -- xinhui pan (2): drm/ttm: Fix a deadlock if the target BO is not idle during swap drm/amdpgu: Use VRAM domain in UVD IB test drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 ++-- drivers/gpu/drm/ttm/ttm_bo.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.25.1

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[PATCH 4.19] fbmem: add margin check to fb_check_caps()
by Dongliang Mu 03 Sep '21

03 Sep '21

[ Upstream commit a49145acfb975d921464b84fe00279f99827d816 ] A fb_ioctl() FBIOPUT_VSCREENINFO call with invalid xres setting or yres setting in struct fb_var_screeninfo will result in a KASAN: vmalloc-out-of-bounds failure in bitfill_aligned() as the margins are being cleared. The margins are cleared in chunks and if the xres setting or yres setting is a value of zero upto the chunk size, the failure will occur. Add a margin check to validate xres and yres settings. Note that, this patch needs special handling to backport it to linux kernel 4.19, 4.14, 4.9, 4.4. Signed-off-by: George Kennedy <george.kennedy(a)oracle.com> Reported-by: syzbot+e5fd3e65515b48c02a30(a)syzkaller.appspotmail.com Reviewed-by: Dan Carpenter <dan.carpenter(a)oracle.com> Cc: Dhaval Giani <dhaval.giani(a)oracle.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie(a)samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1594149963-13801-1-git-send-e… Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/video/fbdev/core/fbmem.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c index 84845275dbef..de04c097d67c 100644 --- a/drivers/video/fbdev/core/fbmem.c +++ b/drivers/video/fbdev/core/fbmem.c @@ -991,6 +991,10 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var) goto done; } + /* bitfill_aligned() assumes that it's at least 8x8 */ + if (var->xres < 8 || var->yres < 8) + return -EINVAL; + ret = info->fbops->fb_check_var(var, info); if (ret) -- 2.25.1

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[PATCH 0/2] MSM8953 MDP/DSI PHY enablement
by Sireesh Kodali 02 Sep '21

02 Sep '21

This patch series adds support for the MDP and DSI PHY as found on the MSM8953 platform (APQ8053, SDM450, SDA450, SDM625, SDM626). All the SoCs on this platform use the adreno 506 GPU. Vladimir Lypak (2): drm/msm/dsi: Add phy configuration for MSM8953 drm/msm/mdp5: Add configuration for MDP v1.16 .../bindings/display/msm/dsi-phy-14nm.yaml | 1 + drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 89 +++++++++++++++++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 +++++ 5 files changed, 114 insertions(+) -- 2.33.0

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[PATCH v2 0/2] Use "ref" clocks from firmware for DSI PLL VCO parent
by Marijn Suijten 02 Sep '21

02 Sep '21

All DSI PHY/PLL drivers were referencing their VCO parent clock by a global name, most of which don't exist or have been renamed. These clock drivers seem to function fine without that except the 14nm driver for the sdm6xx [1]. At the same time all DTs provide a "ref" clock as per the requirements of dsi-phy-common.yaml, but the clock is never used. This patchset puts that clock to use without relying on a global clock name, so that all dependencies are explicitly defined in DT (the firmware) in the end. [1]: https://lore.kernel.org/linux-arm-msm/386db1a6-a1cd-3c7d-a88e-dc83f8a1be96@… Changes since v1: - Dropped "arm: dts: qcom: apq8064: Use 27MHz PXO clock as DSI PLL reference" which has made its way into 5.15-fixes in advance of this patchset landing in 5.16. - Added Fixes: tags for commits that added missing "ref" clocks to DT while this firmware clock was never used (until this patchset). - Documented missing/wrong and later-added clocks (by aforementioned patches) in patch 1/2 more clearly. Dmitry: I have not added the .name="xo" fallback to the 28nm-hpm driver for the missing "ref" clock in msm8974 yet. This patch is supposed to make it in for 5.16 while the missing clock should be added in 5.15, is that enough time? If not I'll gladly respin a v3 with that fallback, but I hope everyone can update their DT firmware before that time. Likewise Bjorn acknowledged that there is enough time for the same to happen on apq8064. Marijn Suijten (2): drm/msm/dsi: Use "ref" fw clock instead of global name for VCO parent clk: qcom: gcc-sdm660: Remove transient global "xo" clock drivers/clk/qcom/gcc-sdm660.c | 14 -------------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 4 +++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 +++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 4 +++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 4 +++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 +++- 6 files changed, 15 insertions(+), 19 deletions(-) -- 2.33.0

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Re: [PATCH v1 03/14] mm: add iomem vma selection for memory migration
by Dan Williams 02 Sep '21

02 Sep '21

On Thu, Sep 2, 2021 at 1:18 AM Christoph Hellwig <hch(a)lst.de> wrote: > > On Wed, Sep 01, 2021 at 11:40:43AM -0400, Felix Kuehling wrote: > > >>> It looks like I'm totally misunderstanding what you are adding here > > >>> then. Why do we need any special treatment at all for memory that > > >>> has normal struct pages and is part of the direct kernel map? > > >> The pages are like normal memory for purposes of mapping them in CPU > > >> page tables and for coherent access from the CPU. > > > That's the user page tables. What about the kernel direct map? > > > If there is a normal kernel struct page backing there really should > > > be no need for the pgmap. > > > > I'm not sure. The physical address ranges are in the UEFI system address > > map as special-purpose memory. Does Linux create the struct pages and > > kernel direct map for that without a pgmap call? I didn't see that last > > time I went digging through that code. > > So doing some googling finds a patch from Dan that claims to hand EFI > special purpose memory to the device dax driver. But when I try to > follow the version that got merged it looks it is treated simply as an > MMIO region to be claimed by drivers, which would not get a struct page. > > Dan, did I misunderstand how E820_TYPE_SOFT_RESERVED works? The original implementation of "soft reserve" support depended on the combination of the EFI special purpose memory type and the ACPI HMAT to define the device ranges. The requirement for ACPI HMAT was relaxed later with commit: 5ccac54f3e12 ACPI: HMAT: attach a device for each soft-reserved range The expectation is that system software policy can then either use the device interface, assign a portion of the reservation back to the page allocator, ignore the reservation altogether. Is this discussion asking for a way to assign this memory to the GPU driver to manage? device-dax already knows how to hand off to the page-allocator, seems reasonable for it to be able to hand-off to another driver.

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[Bug 214289] New: amdgpu Msg issuing pre-check failed and SMU may be not in the right state!
by bugzilla-daemon＠bugzilla.kernel.org 02 Sep '21

02 Sep '21

https://bugzilla.kernel.org/show_bug.cgi?id=214289 Bug ID: 214289 Summary: amdgpu Msg issuing pre-check failed and SMU may be not in the right state! Product: Drivers Version: 2.5 Kernel Version: 5.13.13 Hardware: Intel OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: michal.przybylowicz(a)gmail.com Regression: No I am using kernel 5.13.13 with amdgpu drivers. My graphics card is: PowerColor RX 6800 XT (connected through riser cable - if that means something). I don't have issues when using card with windows 10 (playing games etc.) $ inxi -Gx Graphics: Device-1: Advanced Micro Devices [AMD/ATI] Navi 21 [Radeon RX 6800/6800 XT / 6900 XT] vendor: Tul driver: amdgpu v: kernel bus-ID: 03:00.0 Display: server: X.Org 1.20.11 driver: loaded: amdgpu resolution: 3440x1440~144Hz OpenGL: renderer: AMD Radeon RX 6800 XT (SIENNA_CICHLID DRM 3.41.0 5.13.13-051313-lowlatency LLVM 12.0.1) v: 4.6 Mesa 21.3.0-devel (git-dfef775 2021-09-02 hirsute-oibaf-ppa) direct render: Yes Almost everyday during normal browser usage (watching youtube videos or twitch) I see these messages in the journalctl: ep 02 16:39:13 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:13 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:20 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:20 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:20 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:20 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:21 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:21 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:22 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:22 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:24 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:24 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Failed to power gate VCN! Sep 02 16:39:24 dagon kernel: [drm:amdgpu_dpm_enable_uvd [amdgpu]] *ERROR* Dpm disable uvd failed, ret = -5. Sep 02 16:39:24 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:24 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:24 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Failed to enable gfxoff! Sep 02 16:39:26 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:26 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:26 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:27 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:27 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Failed to power gate VCN! Sep 02 16:39:27 dagon kernel: [drm:amdgpu_dpm_enable_uvd [amdgpu]] *ERROR* Dpm disable uvd failed, ret = -5. Sep 02 16:39:27 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:27 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:27 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Failed to enable gfxoff! Sep 02 16:39:29 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:29 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:30 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:30 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Failed to enable gfxoff! Sep 02 16:39:31 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:31 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:31 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:31 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:31 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:32 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:32 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Failed to power gate VCN! Sep 02 16:39:32 dagon kernel: [drm:amdgpu_dpm_enable_uvd [amdgpu]] *ERROR* Dpm disable uvd failed, ret = -5. Sep 02 16:39:32 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:32 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:32 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Failed to enable gfxoff! Sep 02 16:39:34 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:34 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:34 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:35 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:39:35 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:40:33 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:40:33 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:40:38 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:40:39 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:42:10 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:42:10 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:44:05 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:44:05 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Failed to power gate VCN! Sep 02 16:44:05 dagon kernel: [drm:amdgpu_dpm_enable_uvd [amdgpu]] *ERROR* Dpm disable uvd failed, ret = -5. Sep 02 16:44:05 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:44:05 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:44:05 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Failed to enable gfxoff! Sep 02 16:44:19 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:44:20 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! Sep 02 16:44:20 dagon kernel: amdgpu 0000:03:00.0: amdgpu: Failed to power gate VCN! Sep 02 16:44:20 dagon kernel: [drm:amdgpu_dpm_enable_uvd [amdgpu]] *ERROR* Dpm disable uvd failed, ret = -5. I don't know what do these mean, so I am posting them here. My amdgpu module settings: $ cat /etc/modprobe.d/amdgpu.conf options amdgpu msi=1 aspm=0 audio=0 ppfeaturemask=0xffffffff $ systool -vm amdgpu Module = "amdgpu" Attributes: coresize = "6381568" initsize = "0" initstate = "live" refcnt = "17" srcversion = "426501DD3A5EEAA91AC749F" taint = "" uevent = <store method only> Parameters: abmlevel = "0" aspm = "0" async_gfx_ring = "1" audio = "0" backlight = "-1" bad_page_threshold = "-1" bapm = "-1" benchmark = "0" cg_mask = "4294967295" cik_support = "0" compute_multipipe = "-1" cwsr_enable = "1" dc = "-1" dcdebugmask = "0" dcfeaturemask = "2" debug_evictions = "N" debug_largebar = "0" deep_color = "0" disable_cu = "(null)" discovery = "-1" disp_priority = "0" dpm = "-1" emu_mode = "0" exp_hw_support = "0" force_asic_type = "-1" forcelongtraining = "0" freesync_video = "0" fw_load_type = "-1" gpu_recovery = "-1" halt_if_hws_hang = "0" hw_i2c = "0" hws_gws_support = "N" hws_max_conc_proc = "8" ignore_crat = "0" ip_block_mask = "4294967295" job_hang_limit = "0" lbpw = "-1" lockup_timeout = "" max_num_of_queues_per_device= "4096" mcbp = "0" mes = "0" msi = "1" no_queue_eviction_on_vm_fault= "0" no_system_mem_limit = "N" noretry = "-1" num_kcq = "-1" pcie_gen2 = "-1" pcie_gen_cap = "0" pcie_lane_cap = "0" pg_mask = "4294967295" ppfeaturemask = "0xffffffff" queue_preemption_timeout_ms= "9000" ras_enable = "-1" ras_mask = "4294967295" reset_method = "-1" runpm = "-1" sched_hw_submission = "2" sched_jobs = "32" sched_policy = "0" sdma_phase_quantum = "32" send_sigterm = "0" si_support = "0" smu_memory_pool_size= "0" smu_pptable_id = "-1" test = "0" timeout_fatal_disable= "N" timeout_period = "0" tmz = "-1" virtual_display = "(null)" vis_vramlimit = "0" vm_block_size = "-1" vm_debug = "0" vm_fault_stop = "0" vm_fragment_size = "-1" vm_size = "-1" vm_update_mode = "-1" Sections: -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

1 3

[PATCH] drm/lease: allow empty leases
by Simon Ser 02 Sep '21

02 Sep '21

This can be used to create a separate DRM file description, thus creating a new GEM handle namespace. See [1]. Example usage in wlroots is available at [2]. [1]: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/110 [2]: https://github.com/swaywm/wlroots/pull/3158 Signed-off-by: Simon Ser <contact(a)emersion.fr> Cc: Daniel Vetter <daniel.vetter(a)ffwll.ch> Cc: Daniel Stone <daniels(a)collabora.com> Cc: Pekka Paalanen <pekka.paalanen(a)collabora.co.uk> Cc: Michel Dänzer <michel(a)daenzer.net> Cc: Emil Velikov <emil.l.velikov(a)gmail.com> Cc: Keith Packard <keithp(a)keithp.com> Cc: Boris Brezillon <boris.brezillon(a)collabora.com> Cc: Dave Airlie <airlied(a)redhat.com> --- drivers/gpu/drm/drm_lease.c | 39 +++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/drm_lease.c b/drivers/gpu/drm/drm_lease.c index dee4f24a1808..d72c2fac0ff1 100644 --- a/drivers/gpu/drm/drm_lease.c +++ b/drivers/gpu/drm/drm_lease.c @@ -489,12 +489,6 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev, if (!drm_core_check_feature(dev, DRIVER_MODESET)) return -EOPNOTSUPP; - /* need some objects */ - if (cl->object_count == 0) { - DRM_DEBUG_LEASE("no objects in lease\n"); - return -EINVAL; - } - if (cl->flags && (cl->flags & ~(O_CLOEXEC | O_NONBLOCK))) { DRM_DEBUG_LEASE("invalid flags\n"); return -EINVAL; @@ -510,23 +504,26 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev, object_count = cl->object_count; - object_ids = memdup_user(u64_to_user_ptr(cl->object_ids), - array_size(object_count, sizeof(__u32))); - if (IS_ERR(object_ids)) { - ret = PTR_ERR(object_ids); - goto out_lessor; - } - + /* Handle leased objects, if any */ idr_init(&leases); + if (object_count != 0) { + object_ids = memdup_user(u64_to_user_ptr(cl->object_ids), + array_size(object_count, sizeof(__u32))); + if (IS_ERR(object_ids)) { + ret = PTR_ERR(object_ids); + idr_destroy(&leases); + goto out_lessor; + } - /* fill and validate the object idr */ - ret = fill_object_idr(dev, lessor_priv, &leases, - object_count, object_ids); - kfree(object_ids); - if (ret) { - DRM_DEBUG_LEASE("lease object lookup failed: %i\n", ret); - idr_destroy(&leases); - goto out_lessor; + /* fill and validate the object idr */ + ret = fill_object_idr(dev, lessor_priv, &leases, + object_count, object_ids); + kfree(object_ids); + if (ret) { + DRM_DEBUG_LEASE("lease object lookup failed: %i\n", ret); + idr_destroy(&leases); + goto out_lessor; + } } /* Allocate a file descriptor for the lease */ -- 2.33.0

3 2

[PATCH 0/7] drm/gud: Add some more pixel formats
by Noralf Trønnes 02 Sep '21

02 Sep '21

Hi, This adds some more pixel formats and gives the user the ability to choose the xrgb8888 emulation format. Pixel formats: R8: For greyscale e-ink displays RGB332: For e-ink displays and some niche displays RGB888: Same color depth as XRGB8888 but the smaller buffer gives better fps Noralf. Noralf Trønnes (7): drm/fourcc: Add R8 to drm_format_info drm/format-helper: Add drm_fb_xrgb8888_to_rgb332() drm/format-helper: Add drm_fb_xrgb8888_to_rgb888() drm/gud: Add GUD_PIXEL_FORMAT_R8 drm/gud: Add GUD_PIXEL_FORMAT_RGB332 drm/gud: Add GUD_PIXEL_FORMAT_RGB888 drm/gud: Add module parameter to control emulation: xrgb8888 drivers/gpu/drm/drm_format_helper.c | 85 +++++++++++++++++++++++++++++ drivers/gpu/drm/drm_fourcc.c | 1 + drivers/gpu/drm/gud/gud_drv.c | 19 ++++++- drivers/gpu/drm/gud/gud_internal.h | 12 ++++ drivers/gpu/drm/gud/gud_pipe.c | 6 ++ include/drm/drm_format_helper.h | 4 ++ include/drm/gud.h | 6 +- 7 files changed, 128 insertions(+), 5 deletions(-) -- 2.32.0

3 18

VKMS: New plane formats
by Igor Matheus Andrade Torrente 02 Sep '21

02 Sep '21

Hi, I'm working to add new plane formats to vkms. But I don't know what should be the behavior in the situation that we received multiple planes with different formats from the users-space. For example, if the user chooses: - DRM_FORMAT_ARGB16161616 to the primary plane - DRM_FORMAT_ARGB8888 to the cursor - DRM_FORMAT_YUV42 to the overlay What should be the output format that will be used to calculate the crc? DRM_FORMAT_ARGB16161616? My idea was to convert all the planes to the primary, but I'm not sure if it is the right approach. Best regards, --- Igor M. A. Torrente

2 2

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dri-devel September 2021