dri-devel January 2022

dri-devel@lists.freedesktop.org

373 participants
842 discussions

[PATCH v3 1/4] drm/i915: don't call free_mmap_offset when purging
by Matthew Auld 07 Jan '22

07 Jan '22

The TTM backend is in theory the only user here(also purge should only be called once we have dropped the pages), where it is setup at object creation and is only removed once the object is destroyed. Also resetting the node here might be iffy since the ttm fault handler uses the stored fake offset to determine the page offset within the pages array. This also blows up in the dontneed-before-mmap test, since the expectation is that the vma_node will live on, until the object is destroyed: <2> [749.062902] kernel BUG at drivers/gpu/drm/i915/gem/i915_gem_ttm.c:943! <4> [749.062923] invalid opcode: 0000 [#1] PREEMPT SMP NOPTI <4> [749.062928] CPU: 0 PID: 1643 Comm: gem_madvise Tainted: G U W 5.16.0-rc8-CI-CI_DRM_11046+ #1 <4> [749.062933] Hardware name: Gigabyte Technology Co., Ltd. GB-Z390 Garuda/GB-Z390 Garuda-CF, BIOS IG1c 11/19/2019 <4> [749.062937] RIP: 0010:i915_ttm_mmap_offset.cold.35+0x5b/0x5d [i915] <4> [749.063044] Code: 00 48 c7 c2 a0 23 4e a0 48 c7 c7 26 df 4a a0 e8 95 1d d0 e0 bf 01 00 00 00 e8 8b ec cf e0 31 f6 bf 09 00 00 00 e8 5f 30 c0 e0 <0f> 0b 48 c7 c1 24 4b 56 a0 ba 5b 03 00 00 48 c7 c6 c0 23 4e a0 48 <4> [749.063052] RSP: 0018:ffffc90002ab7d38 EFLAGS: 00010246 <4> [749.063056] RAX: 0000000000000240 RBX: ffff88811f2e61c0 RCX: 0000000000000006 <4> [749.063060] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000009 <4> [749.063063] RBP: ffffc90002ab7e58 R08: 0000000000000001 R09: 0000000000000001 <4> [749.063067] R10: 000000000123d0f8 R11: ffffc90002ab7b20 R12: ffff888112a1a000 <4> [749.063071] R13: 0000000000000004 R14: ffff88811f2e61c0 R15: ffff888112a1a000 <4> [749.063074] FS: 00007f6e5fcad500(0000) GS:ffff8884ad600000(0000) knlGS:0000000000000000 <4> [749.063078] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4> [749.063081] CR2: 00007efd264e39f0 CR3: 0000000115fd6005 CR4: 00000000003706f0 <4> [749.063085] Call Trace: <4> [749.063087] <TASK> <4> [749.063089] __assign_mmap_offset+0x41/0x300 [i915] <4> [749.063171] __assign_mmap_offset_handle+0x159/0x270 [i915] <4> [749.063248] ? i915_gem_dumb_mmap_offset+0x70/0x70 [i915] <4> [749.063325] drm_ioctl_kernel+0xae/0x140 <4> [749.063330] drm_ioctl+0x201/0x3d0 <4> [749.063333] ? i915_gem_dumb_mmap_offset+0x70/0x70 [i915] <4> [749.063409] ? do_user_addr_fault+0x200/0x670 <4> [749.063415] __x64_sys_ioctl+0x6d/0xa0 <4> [749.063419] do_syscall_64+0x3a/0xb0 <4> [749.063423] entry_SYSCALL_64_after_hwframe+0x44/0xae <4> [749.063428] RIP: 0033:0x7f6e5f100317 Testcase: igt/gem_madvise/dontneed-before-mmap Fixes: cf3e3e86d779 ("drm/i915: Use ttm mmap handling for ttm bo's.") Signed-off-by: Matthew Auld <matthew.auld(a)intel.com> Cc: Thomas Hellström <thomas.hellstrom(a)linux.intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom(a)linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index 89b70f5cde7a..9f429ed6e78a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -161,7 +161,6 @@ int i915_gem_object_pin_pages_unlocked(struct drm_i915_gem_object *obj) /* Immediately discard the backing storage */ int i915_gem_object_truncate(struct drm_i915_gem_object *obj) { - drm_gem_free_mmap_offset(&obj->base); if (obj->ops->truncate) return obj->ops->truncate(obj); -- 2.31.1

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[Bug 215001] Regression in 5.15, Firmware-initialized graphics console selects FB_VGA16, screen corruption
by bugzilla-daemon＠bugzilla.kernel.org 07 Jan '22

07 Jan '22

https://bugzilla.kernel.org/show_bug.cgi?id=215001 --- Comment #7 from Kris Karas (bugs-a21(a)moonlit-rail.com) --- Hi Javier - I tested the (updated) patch from comment 6 on three different systems, two servers with a character-graphic BIOS (expected to use VGA16), and my development system with a graphical UEFI boot (expected to use EFIFB). I am happy to report that in all cases, the patch worked perfectly. Thanks for having whipped up this patch! Feel free to submit upstream to Linus, and also to Greg for inclusion in 5.15.y. Tested-By: Kris Karas <bugs-a21(a)moonlit-rail.com> In reply to Thorsten in comment 4, I did indeed test against 5.15.13 and 5.16-rc8 without success. This makes me curious... ... I filed this bug nearly 2 months ago with the "Regression = Y" metadata clearly set; but the various kernel regression trackers haven't picked up on that fact until just days ago. Are automated regression trackers only looking at messages on LKML? What's the best way to get a bugzilla report for a regression tracked so that it doesn't get forgotten or lost in the shuffle? For example, bug 199533 was filed back in 2018, with a proper bisect even, but hasn't garnered even so much as a single comment. (Probably ought to be closed as I no longer have the hardware to test a fix :-) Kris -- You may reply to this email to add a comment. You are receiving this mail because: You are on the CC list for the bug.

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[Bug 215001] Regression in 5.15, Firmware-initialized graphics console selects FB_VGA16, screen corruption
by bugzilla-daemon＠bugzilla.kernel.org 07 Jan '22

07 Jan '22

https://bugzilla.kernel.org/show_bug.cgi?id=215001 Javier Martinez Canillas (javier(a)dowhile0.org) changed: What |Removed |Added ---------------------------------------------------------------------------- Attachment #300235|0 |1 is obsolete| | --- Comment #6 from Javier Martinez Canillas (javier(a)dowhile0.org) --- Created attachment 300236 --> https://bugzilla.kernel.org/attachment.cgi?id=300236&action=edit [PATCH] video: vga16fb: Only probe for EGA and VGA 16 color graphic cards -- You may reply to this email to add a comment. You are receiving this mail because: You are on the CC list for the bug.

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[Bug 215001] Regression in 5.15, Firmware-initialized graphics console selects FB_VGA16, screen corruption
by bugzilla-daemon＠bugzilla.kernel.org 07 Jan '22

07 Jan '22

https://bugzilla.kernel.org/show_bug.cgi?id=215001 --- Comment #5 from Javier Martinez Canillas (javier(a)dowhile0.org) --- Created attachment 300235 --> https://bugzilla.kernel.org/attachment.cgi?id=300235&action=edit [PATCH] video: vga16fb: Only probe for EGA and VGA 16 color graphic cards Can you try the attached (untested) patch? The commit you mention in Comment 3 didn't change any logic but just moved the platform device registration that match the vesafb and efifb drivers. As far as I can tell, the problem is that the vga16fb driver doesn't check if the video modes are one that's supported by it and just blindly attempts to probe the driver. This probably wasn't a problem before because the sysfb.o was in arch/x86/kernel but no is in drivers/firmware. But the issue in vga16fb was present before, just moving exposed it. I believe that the correct thing is to check if screen_info says that's a {E,V}GA 16 color mode and fail to probe the vga16fb driver otherwise. -- You may reply to this email to add a comment. You are receiving this mail because: You are on the CC list for the bug.

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[PATCH] drm/mediatek: Fix unused-but-set variable warning
by Miles Chen 07 Jan '22

07 Jan '22

Fix unused-but-set variable warning: drivers/gpu/drm/mediatek/mtk_cec.c:85:6: warning: variable 'tmp' set but not used [-Wunused-but-set-variable] Signed-off-by: Miles Chen <miles.chen(a)mediatek.com> --- drivers/gpu/drm/mediatek/mtk_cec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c index e9cef5c0c8f7..cdfa648910b2 100644 --- a/drivers/gpu/drm/mediatek/mtk_cec.c +++ b/drivers/gpu/drm/mediatek/mtk_cec.c @@ -85,7 +85,7 @@ static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset, u32 tmp = readl(cec->regs + offset) & ~mask; tmp |= val & mask; - writel(val, cec->regs + offset); + writel(tmp, cec->regs + offset); } void mtk_cec_set_hpd_event(struct device *dev, -- 2.18.0

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[PATCH 0/4] add pine64 touch panel support to rockpro64
by Peter Geis 07 Jan '22

07 Jan '22

This patch series adds support for the Pine64 touch panel to the rockpro64 single board computer. This panel attaches to the dsi port and includes an i2c touch screen. The first two patches involve making the reset pin to the Feiyang fy07024di26a30d panel optional. On the rockpro64 and quartz64-a this pin is tied to dvdd and automatically comes high when power is applied. The third patch adds the device tree nodes to rockpro64 to permit the panel to be used. The fourth patch is an example patch to enable this support, tagged do not merge as this is something for the end user to enable only when they have the panel attached. Peter Geis (4): dt-bindings: display: panel: feiyang,fy07024di26a30d: make reset gpio optional drm/panel: feiyang-fy07024di26a30d: make reset gpio optional arm64: dts: rockchip: add pine64 touch panel display to rockpro64 arm64: dts: rockchip: enable the pine64 touch screen on rockpro64 .../panel/feiyang,fy07024di26a30d.yaml | 1 - .../boot/dts/rockchip/rk3399-rockpro64.dtsi | 80 ++++++++++++++++++- .../drm/panel/panel-feiyang-fy07024di26a30d.c | 11 ++- 3 files changed, 83 insertions(+), 9 deletions(-) -- 2.32.0

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[PATCH v4] drm/msm/dp: add support of tps4 (training pattern 4) for HBR3
by Kuogee Hsieh 07 Jan '22

07 Jan '22

From: Kuogee Hsieh <khsieh(a)codeaurora.org> Some DP sinkers prefer to use tps4 instead of tps3 during training #2. This patch will use tps4 to perform link training #2 if sinker's DPCD supports it. Changes in V2: -- replace dp_catalog_ctrl_set_pattern() with dp_catalog_ctrl_set_pattern_state_bit() Changes in V3: -- change state_ctrl_bits type to u32 and pattern type to u8 Changes in V4: -- align } else if { and } else { Signed-off-by: Kuogee Hsieh <quic_khsieh(a)quicinc.com> Reviewed-by: Stephen Boyd <swboyd(a)chromium.org> --- drivers/gpu/drm/msm/dp/dp_catalog.c | 12 ++++++------ drivers/gpu/drm/msm/dp/dp_catalog.h | 2 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 17 ++++++++++++----- 3 files changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 6ae9b29..64f0b26 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -456,19 +456,19 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); } -int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, - u32 pattern) +int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, + u32 state_bit) { int bit, ret; u32 data; struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - bit = BIT(pattern - 1); - DRM_DEBUG_DP("hw: bit=%d train=%d\n", bit, pattern); + bit = BIT(state_bit - 1); + DRM_DEBUG_DP("hw: bit=%d train=%d\n", bit, state_bit); dp_catalog_ctrl_state_ctrl(dp_catalog, bit); - bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; + bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; /* Poll for mainlink ready status */ ret = readx_poll_timeout(readl, catalog->io->dp_controller.link.base + @@ -476,7 +476,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); if (ret < 0) { - DRM_ERROR("set pattern for link_train=%d failed\n", pattern); + DRM_ERROR("set state_bit for link_train=%d failed\n", state_bit); return ret; } return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 6965afa..7dea101 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -94,7 +94,7 @@ void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable); void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb); void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, bool fixed_nvid); -int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, u32 pattern); +int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32 pattern); void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog); bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 39558a2..ad64ddd 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1083,7 +1083,7 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, *training_step = DP_TRAINING_1; - ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1); + ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); if (ret) return ret; dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | @@ -1181,7 +1181,8 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, int *training_step) { int tries = 0, ret = 0; - char pattern; + u8 pattern; + u32 state_ctrl_bit; int const maximum_retries = 5; u8 link_status[DP_LINK_STATUS_SIZE]; @@ -1189,12 +1190,18 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, *training_step = DP_TRAINING_2; - if (drm_dp_tps3_supported(ctrl->panel->dpcd)) + if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { + pattern = DP_TRAINING_PATTERN_4; + state_ctrl_bit = 4; + } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { pattern = DP_TRAINING_PATTERN_3; - else + state_ctrl_bit = 3; + } else { pattern = DP_TRAINING_PATTERN_2; + state_ctrl_bit = 2; + } - ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern); + ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); if (ret) return ret; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

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[PATCH v4] drm/msm/dp: populate connector of struct dp_panel
by Kuogee Hsieh 07 Jan '22

07 Jan '22

DP CTS test case 4.2.2.6 has valid edid with bad checksum on purpose and expect DP source return correct checksum. During drm edid read, correct edid checksum is calculated and stored at connector::real_edid_checksum. The problem is struct dp_panel::connector never be assigned, instead the connector is stored in struct msm_dp::connector. When we run compliance testing test case 4.2.2.6 dp_panel_handle_sink_request() won't have a valid edid set in struct dp_panel::edid so we'll try to use the connectors real_edid_checksum and hit a NULL pointer dereference error because the connector pointer is never assigned. Changes in V2: -- populate panel connector at msm_dp_modeset_init() instead of at dp_panel_read_sink_caps() Changes in V3: -- remove unhelpful kernel crash trace commit text -- remove renaming dp_display parameter to dp Changes in V4: -- add more details to commit text Fixes: 7948fe12d47 ("drm/msm/dp: return correct edid checksum after corrupted edid checksum read") Signee-off-by: Kuogee Hsieh <quic_khsieh(a)quicinc.com> --- drivers/gpu/drm/msm/dp/dp_display.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 3449d3f..40a059d 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1499,6 +1499,7 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, struct drm_encoder *encoder) { struct msm_drm_private *priv; + struct dp_display_private *dp_priv; int ret; if (WARN_ON(!encoder) || WARN_ON(!dp_display) || WARN_ON(!dev)) @@ -1507,6 +1508,8 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, priv = dev->dev_private; dp_display->drm_dev = dev; + dp_priv = container_of(dp_display, struct dp_display_private, dp_display); + ret = dp_display_request_irq(dp_display); if (ret) { DRM_ERROR("request_irq failed, ret=%d\n", ret); @@ -1524,6 +1527,8 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, return ret; } + dp_priv->panel->connector = dp_display->connector; + priv->connectors[priv->num_connectors++] = dp_display->connector; return 0; } -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

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[PATCH v3] drm/msm/dp: add support of tps4 (training pattern 4) for HBR3
by Kuogee Hsieh 07 Jan '22

07 Jan '22

From: Kuogee Hsieh <khsieh(a)codeaurora.org> Some DP sinkers prefer to use tps4 instead of tps3 during training #2. This patch will use tps4 to perform link training #2 if sinker's DPCD supports it. Changes in V2: -- replace dp_catalog_ctrl_set_pattern() with dp_catalog_ctrl_set_pattern_state_bit() Changes in V3: -- change state_ctrl_bits type to u32 and pattern type to u8 Signed-off-by: Kuogee Hsieh <quic_khsieh(a)quicinc.com> --- drivers/gpu/drm/msm/dp/dp_catalog.c | 12 ++++++------ drivers/gpu/drm/msm/dp/dp_catalog.h | 2 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 19 ++++++++++++++----- 3 files changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 6ae9b29..64f0b26 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -456,19 +456,19 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); } -int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, - u32 pattern) +int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, + u32 state_bit) { int bit, ret; u32 data; struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - bit = BIT(pattern - 1); - DRM_DEBUG_DP("hw: bit=%d train=%d\n", bit, pattern); + bit = BIT(state_bit - 1); + DRM_DEBUG_DP("hw: bit=%d train=%d\n", bit, state_bit); dp_catalog_ctrl_state_ctrl(dp_catalog, bit); - bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; + bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; /* Poll for mainlink ready status */ ret = readx_poll_timeout(readl, catalog->io->dp_controller.link.base + @@ -476,7 +476,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); if (ret < 0) { - DRM_ERROR("set pattern for link_train=%d failed\n", pattern); + DRM_ERROR("set state_bit for link_train=%d failed\n", state_bit); return ret; } return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 6965afa..7dea101 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -94,7 +94,7 @@ void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable); void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb); void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, bool fixed_nvid); -int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, u32 pattern); +int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32 pattern); void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog); bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 39558a2..ba70387 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1083,7 +1083,7 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, *training_step = DP_TRAINING_1; - ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1); + ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); if (ret) return ret; dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | @@ -1181,7 +1181,8 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, int *training_step) { int tries = 0, ret = 0; - char pattern; + u8 pattern; + u32 state_ctrl_bit; int const maximum_retries = 5; u8 link_status[DP_LINK_STATUS_SIZE]; @@ -1189,12 +1190,20 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, *training_step = DP_TRAINING_2; - if (drm_dp_tps3_supported(ctrl->panel->dpcd)) + if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { + pattern = DP_TRAINING_PATTERN_4; + state_ctrl_bit = 4; + } + else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { pattern = DP_TRAINING_PATTERN_3; - else + state_ctrl_bit = 3; + } + else { pattern = DP_TRAINING_PATTERN_2; + state_ctrl_bit = 2; + } - ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern); + ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); if (ret) return ret; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

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[PATCH v2 0/3] Update to GuC version 69.0.3
by John.C.Harrison＠Intel.com 07 Jan '22

07 Jan '22

From: John Harrison <John.C.Harrison(a)Intel.com> Update to the latest GuC version. This includes a suite of interface changes and new features with corresponding i915 side changes. v2: Rebased to latest tree. Signed-off-by: John Harrison <John.C.Harrison(a)Intel.com> John Harrison (3): drm/i915/guc: Temporarily bump the GuC load timeout drm/i915/guc: Update to GuC version 69.0.3 drm/i915/guc: Improve GuC loading status check/error reports Documentation/gpu/i915.rst | 1 + .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 80 +++++----- .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 23 +++ drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 82 ++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc.c | 126 +++++++++++++--- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 4 + drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 45 +++++- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 141 ++++++++++-------- drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 30 ++-- drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 37 ++++- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 31 ++-- drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 3 + drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 4 - .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +++ drivers/gpu/drm/i915/gt/uc/intel_huc.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_uc.c | 31 ++-- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 30 ++-- 17 files changed, 493 insertions(+), 194 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h -- 2.25.1

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dri-devel January 2022