dri-devel March 2022

dri-devel@lists.freedesktop.org

370 participants
780 discussions

[PATCH 0/5] dyndbg add exclusive class support
by Jim Cromie 28 Mar '22

28 Mar '22

Hi Greg, Jason, Please consider these for char/misc or linux-next/soon/mumble. This patchset adds exclusive class support to dyndbg, allowing it to directly represent drm's debug_category. It is the dyndbg half of: https://lore.kernel.org/lkml/20220217034829.64395-1-jim.cromie@gmail.com/ The DRM half of that patchset uses this support to reimplement drm.debug on dyndbg, and uses its callsite patching to avoid the runtime checking done by drm_debug_enabled(). Background: In the past, various extensions to dyndbg/pr_debug have been proposed, none seemed to gain any consensus. This list is certainly incomplete. https://lore.kernel.org/lkml/20200609104604.1594-1-stanimir.varbanov@linaro… pr_levels was discussed around this patchset, in revs 3,4,5 This search helps: s:venus: s:dynamic f:stanimir.varbanov@linaro.org IMO, pr_levels suffers from implied meaning between the levels: 2 > 1. In contrast, DRM has logically disjoint categories, and is implemented in an enum (despite its flag/mask values, a micro-optimization). https://lore.kernel.org/lkml/20210813151734.1236324-1-jim.cromie@gmail.com/ That patchset used pr_debug in DRM, and prepended "drm:kms:" etc to the format strings so each category was selectable; "format drm:kms:" in the query. This worked, but it made the format config-dependent, and was hard to explain without undue "artifact". So this patchset adds .class_id field (4-bits) to dynamic-debug callsites, and 'class N' query/command support to select upon it. Existing callsites and queries get .class_id=15, so 0-14 are available for use by the client (DRM wants 0-10). The DRM patchset then: . renumbers drm_debug_category to fit into the 4-bit .class_id the new enumerations *are* the bit-positions in drm/parameters/debug. . adapts the category-macro layer to use _CLS macros, mapping categories. . adds macro layer under the category-macro layer which wraps drm_*dbg inside a dyndbg Factory macro . uses DEFINE_DYNAMIC_DEBUG_CLASSBITS to tie to __drm_debug callbacks ref the var, so drm_debug_enabled(cat) just works. Jim Cromie (5): dyndbg: fix static_branch manipulation fixes a latent bug, before a 2nd "enable" flag exposes it. dyndbg: add class_id field and query support will allow (with that drm patchset): #> # turn on DRM_ATOMIC in amdgpu #> echo module amdgpu class 4 +p > /proc/dynamic_debug/control #> # turn on DRM_CORE in drm #> echo module drm class 0 +p > /proc/dynamic_debug/control dyndbg: add DEFINE_DYNAMIC_DEBUG_CLASSBITS macro adds macro & callbacks to support drm.debug bitmap #> echo 4 > /sys/module/drm/parameters/debug dyndbg: drop EXPORTed dynamic_debug_exec_queries unused yet, obsoleted by 2,3 dyndbg: show both old and new in change-info minor debug improvement .../admin-guide/dynamic-debug-howto.rst | 7 + include/linux/dynamic_debug.h | 111 ++++++++++--- lib/dynamic_debug.c | 150 ++++++++++++++---- 3 files changed, 213 insertions(+), 55 deletions(-) -- 2.35.1

3 10

[PATCH v5 0/9] drm/i915/ttm: Evict and restore of compressed object
by Ramalingam C 28 Mar '22

28 Mar '22

On Xe-HP and later devices, we use dedicated compression control state (CCS) stored in local memory for each surface, to support the 3D and media compression formats. The memory required for the CCS of the entire local memory is 1/256 of the local memory size. So before the kernel boot, the required memory is reserved for the CCS data and a secure register will be programmed with the CCS base address So when we allocate a object in local memory we dont need to explicitly allocate the space for ccs data. But when we evict the obj into the smem to hold the compression related data along with the obj we need smem space of obj_size + (obj_size/256). Hence when we create smem for an obj with lmem placement possibility we create with the extra space. When we are swapping out the local memory obj on flat-ccs capable platform, we need to capture the ccs data too along with main meory and we need to restore it when we are swapping in the content. When lmem object is swapped into a smem obj, smem obj will have the extra pages required to hold the ccs data corresponding to the lmem main memory. So main memory of lmem will be copied into the initial pages of the smem and then ccs data corresponding to the main memory will be copied to the subsequent pages of smem. Swapin happens exactly in reverse order. First main memory of lmem is restored from the smem's initial pages and the ccs data will be restored from the subsequent pages of smem. Extracting and restoring the CCS data is done through a special cmd called XY_CTRL_SURF_COPY_BLT v5: Correct locating of ccs data [Thomas] Reuse of emit_copy_ccs. R-bs picked. Test-with: 20220314051432.15785-1-ramalingam.c(a)intel.com Ramalingam C (9): drm/i915/gt: Use XY_FAST_COLOR_BLT to clear obj on graphics ver 12+ drm/i915/gt: Optimize the migration and clear loop drm/i915/gt: Clear compress metadata for Flat-ccs objects drm/i915/selftest_migrate: Consider the possible roundup of size drm/i915/selftest_migrate: Check CCS meta data clear drm/i915/gt: offset handling for multiple copy engines drm/ttm: Add a parameter to add extra pages into ttm_tt drm/i915/gem: Add extra pages in ttm_tt for ccs data drm/i915/migrate: Evict and restore the flatccs capable lmem obj drivers/gpu/drm/drm_gem_vram_helper.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 29 +- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 20 + drivers/gpu/drm/i915/gt/intel_migrate.c | 409 +++++++++++++++++-- drivers/gpu/drm/i915/gt/selftest_migrate.c | 253 ++++++++++-- drivers/gpu/drm/qxl/qxl_ttm.c | 2 +- drivers/gpu/drm/ttm/ttm_agp_backend.c | 2 +- drivers/gpu/drm/ttm/ttm_tt.c | 12 +- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 +- include/drm/ttm/ttm_tt.h | 4 +- 10 files changed, 664 insertions(+), 71 deletions(-) -- 2.20.1

3 18

[PATCH v3 00/12] drm/edid: constify EDID parsing, with fixes
by Jani Nikula 28 Mar '22

28 Mar '22

v3 of https://patchwork.freedesktop.org/series/101787/ and https://patchwork.freedesktop.org/series/101862/ I screwed up with the struct renamings in v2, so there's some falling back to v1 and general confusion here. Sorry. BR, Jani. Jani Nikula (12): drm/edid: don't modify EDID while parsing drm/edid: fix reduced blanking support check drm/edid: pass a timing pointer to is_display_descriptor() drm/edid: pass a timing pointer to is_detailed_timing_descriptor() drm/edid: use struct detailed_timing member access in is_rb() drm/edid: use struct detailed_timing member access in gtf2 functions drm/edid: constify struct detailed_timing in lower level parsing drm/edid: constify struct detailed_timing in parsing callbacks drm/edid: constify struct edid passed to detailed blocks drm/edid: constify struct edid passed around in callbacks and closure drm/edid: add more general struct edid constness in the interfaces drm/edid: split drm_add_edid_modes() to two drivers/gpu/drm/drm_edid.c | 325 ++++++++++++++++++++----------------- include/drm/drm_edid.h | 10 +- 2 files changed, 185 insertions(+), 150 deletions(-) -- 2.30.2

3 26

[PATCH] drm/i915: avoid concurrent writes to aux_inv
by fei.yang＠intel.com 28 Mar '22

28 Mar '22

From: Fei Yang <fei.yang(a)intel.com> GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the rq->engine is not necessarily the engine eventually carrying out the request, and potentially the engine could even be a virtual one (with engine->instance being -1). With the MMIO remap feature, we can actually set bit 17 of MI_LRI instruction and let the hardware to figure out the local aux_inv register at runtime to avoid invalidating auxiliary table for all engines. Bspec: 45728 v2: Invalidate AUX table for indirect context as well. Cc: Stuart Summers <stuart.summers(a)intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Signed-off-by: Chris Wilson <chris.p.wilson(a)intel.com> Signed-off-by: Fei Yang <fei.yang(a)intel.com> --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 48 ++++---------------- drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 4 +- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 12 +++++ 4 files changed, 26 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 36148887c699..8178be083b42 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -6,7 +6,6 @@ #include "gen8_engine_cs.h" #include "i915_drv.h" #include "intel_gpu_commands.h" -#include "intel_gt_regs.h" #include "intel_lrc.h" #include "intel_ring.h" @@ -165,33 +164,9 @@ static u32 preparser_disable(bool state) return MI_ARB_CHECK | 1 << 8 | state; } -static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine) +u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs) { - static const i915_reg_t vd[] = { - GEN12_VD0_AUX_NV, - GEN12_VD1_AUX_NV, - GEN12_VD2_AUX_NV, - GEN12_VD3_AUX_NV, - }; - - static const i915_reg_t ve[] = { - GEN12_VE0_AUX_NV, - GEN12_VE1_AUX_NV, - }; - - if (engine->class == VIDEO_DECODE_CLASS) - return vd[engine->instance]; - - if (engine->class == VIDEO_ENHANCEMENT_CLASS) - return ve[engine->instance]; - - GEM_BUG_ON("unknown aux_inv reg\n"); - return INVALID_MMIO_REG; -} - -static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs) -{ - *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN; *cs++ = i915_mmio_reg_offset(inv_reg); *cs++ = AUX_INV; *cs++ = MI_NOOP; @@ -293,10 +268,12 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) if (mode & EMIT_INVALIDATE) { cmd += 2; - if (!HAS_FLAT_CCS(rq->engine->i915)) { + if (!HAS_FLAT_CCS(rq->engine->i915) && + (rq->engine->class == VIDEO_DECODE_CLASS || + rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) { aux_inv = rq->engine->mask & ~BIT(BCS0); if (aux_inv) - cmd += 2 * hweight32(aux_inv) + 2; + cmd += 4; } } @@ -329,15 +306,10 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) *cs++ = 0; /* value */ if (aux_inv) { /* hsdes: 1809175790 */ - struct intel_engine_cs *engine; - unsigned int tmp; - - *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv)); - for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) { - *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine)); - *cs++ = AUX_INV; - } - *cs++ = MI_NOOP; + if (rq->engine->class == VIDEO_DECODE_CLASS) + cs = gen12_emit_aux_table_inv(GEN12_VD0_AUX_NV, cs); + else + cs = gen12_emit_aux_table_inv(GEN12_VE0_AUX_NV, cs); } if (mode & EMIT_INVALIDATE) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h index cc6e21d3662a..94f589e73d10 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h @@ -10,7 +10,7 @@ #include <linux/types.h> #include "i915_gem.h" /* GEM_BUG_ON */ - +#include "intel_gt_regs.h" #include "intel_gpu_commands.h" struct i915_request; @@ -38,6 +38,8 @@ u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); +u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs); + static inline u32 * __gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset) { diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index d112ffd56418..4243be030bc1 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -144,6 +144,7 @@ #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) /* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */ #define MI_LRI_LRM_CS_MMIO REG_BIT(19) +#define MI_LRI_MMIO_REMAP_EN REG_BIT(17) #define MI_LRI_FORCE_POSTED (1<<12) #define MI_LOAD_REGISTER_IMM_MAX_REGS (126) #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 07bef7128fdb..7581ef9e2cce 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1208,6 +1208,10 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); + /* hsdes: 1809175790 */ + if (!HAS_FLAT_CCS(ce->engine->i915)) + cs = gen12_emit_aux_table_inv(GEN12_GFX_CCS_AUX_NV, cs); + return cs; } @@ -1225,6 +1229,14 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs) PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); + /* hsdes: 1809175790 */ + if (!HAS_FLAT_CCS(ce->engine->i915)) { + if (ce->engine->class == VIDEO_DECODE_CLASS) + cs = gen12_emit_aux_table_inv(GEN12_VD0_AUX_NV, cs); + else if (ce->engine->class == VIDEO_ENHANCEMENT_CLASS) + cs = gen12_emit_aux_table_inv(GEN12_VE0_AUX_NV, cs); + } + return cs; } -- 2.25.1

3 2

[PATCH v3 1/8] Revert "drm/bridge: dw-mipi-dsi: Find the possible DSI devices"
by Jagan Teki 28 Mar '22

28 Mar '22

This reverts commit c206c7faeb3263a7cc7b4de443a3877cd7a5e74b. In order to avoid any probe ordering issues, the I2C based downstream bridge drivers now register and attach the DSI devices at the probe instead of doing it on drm_bridge_function.attach(). Examples of those commits are: commit <6ef7ee48765f> ("drm/bridge: sn65dsi83: Register and attach our DSI device at probe") commit <d89078c37b10> ("drm/bridge: lt8912b: Register and attach our DSI device at probe") commit <864c49a31d6b> ("drm/bridge: adv7511: Register and attach our DSI device at probe") dw-mipi-dsi has panel or bridge finding code based on previous downstream bridges, so revert the same and make the panel or bridge funding in host attach as before. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v3, v2: - none drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 58 +++++-------------- 1 file changed, 15 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 11d20b8638cd..1cc912b6e1f8 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -246,7 +246,6 @@ struct dw_mipi_dsi { struct clk *pclk; - bool device_found; unsigned int lane_mbps; /* per lane */ u32 channel; u32 lanes; @@ -310,37 +309,13 @@ static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) return readl(dsi->base + reg); } -static int dw_mipi_dsi_panel_or_bridge(struct dw_mipi_dsi *dsi, - struct device_node *node) -{ - struct drm_bridge *bridge; - struct drm_panel *panel; - int ret; - - ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge); - if (ret) - return ret; - - if (panel) { - bridge = drm_panel_bridge_add_typed(panel, - DRM_MODE_CONNECTOR_DSI); - if (IS_ERR(bridge)) - return PTR_ERR(bridge); - } - - dsi->panel_bridge = bridge; - - if (!dsi->panel_bridge) - return -EPROBE_DEFER; - - return 0; -} - static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *device) { struct dw_mipi_dsi *dsi = host_to_dsi(host); const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; + struct drm_bridge *bridge; + struct drm_panel *panel; int ret; if (device->lanes > dsi->plat_data->max_data_lanes) { @@ -354,14 +329,22 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, dsi->format = device->format; dsi->mode_flags = device->mode_flags; - if (!dsi->device_found) { - ret = dw_mipi_dsi_panel_or_bridge(dsi, host->dev->of_node); - if (ret) - return ret; + ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, + &panel, &bridge); + if (ret) + return ret; - dsi->device_found = true; + if (panel) { + bridge = drm_panel_bridge_add_typed(panel, + DRM_MODE_CONNECTOR_DSI); + if (IS_ERR(bridge)) + return PTR_ERR(bridge); } + dsi->panel_bridge = bridge; + + drm_bridge_add(&dsi->bridge); + if (pdata->host_ops && pdata->host_ops->attach) { ret = pdata->host_ops->attach(pdata->priv_data, device); if (ret < 0) @@ -1021,16 +1004,6 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge, /* Set the encoder type as caller does not know it */ bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; - if (!dsi->device_found) { - int ret; - - ret = dw_mipi_dsi_panel_or_bridge(dsi, dsi->dev->of_node); - if (ret) - return ret; - - dsi->device_found = true; - } - /* Attach the panel-bridge to the dsi bridge */ return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge, flags); @@ -1217,7 +1190,6 @@ __dw_mipi_dsi_probe(struct platform_device *pdev, #ifdef CONFIG_OF dsi->bridge.of_node = pdev->dev.of_node; #endif - drm_bridge_add(&dsi->bridge); return dsi; } -- 2.25.1

2 9

[PATCH] drm/vmwgfx: Propagate error on failed ioctl
by Philipp Sieweck 28 Mar '22

28 Mar '22

The cases of vmw_user_bo_synccpu_grab failing with -ERESTARTSYS or -EBUSY are handled in vmw_user_bo_synccpu_ioctl by not printing an error message. However, the error value gets discarded, indicating success. This leads to rendering glitches and a reported drm error on the next ioctl call to release the handle. This patch propagates the error value from vmw_user_synccpu_grab. Signed-off-by: Philipp Sieweck <psi(a)informatik.uni-kiel.de> --- drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c index 31aecc46624b..81fe4dc5e6ab 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c @@ -621,6 +621,8 @@ int vmw_user_bo_synccpu_ioctl(struct drm_device *dev, void *data, (unsigned int) arg->handle); return ret; } + if (unlikely(ret != 0)) + return ret; break; case drm_vmw_synccpu_release: ret = vmw_user_bo_synccpu_release(file_priv, -- 2.35.1

3 3

[PATCH v2 00/11] drm/edid: constify EDID parsing, with some fixes
by Jani Nikula 28 Mar '22

28 Mar '22

v2 of https://patchwork.freedesktop.org/series/101787/ addressing some review comments from Ville. Jani Nikula (11): drm/edid: don't modify EDID while parsing drm/edid: fix reduced blanking support check drm/edid: slightly restructure timing and non-timing descriptor structs drm/edid: pass a timing pointer to is_display_descriptor() drm/edid: use struct detailed_timing member access in is_rb() drm/edid: use struct detailed_data_monitor_range member access in gtf2 functions drm/edid: constify struct detailed_timing in lower level parsing drm/edid: constify struct detailed_timing in parsing callbacks drm/edid: constify struct edid passed to detailed blocks drm/edid: constify struct edid passed around in callbacks and closure drm/edid: add more general struct edid constness in the interfaces .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +- drivers/gpu/drm/drm_edid.c | 287 ++++++++++-------- include/drm/drm_edid.h | 19 +- 3 files changed, 174 insertions(+), 138 deletions(-) -- 2.30.2

3 18

[PATCH v2] drm/bridge: nwl-dsi: switch to devm_drm_of_get_bridge
by José Expósito 28 Mar '22

28 Mar '22

The function "drm_of_find_panel_or_bridge" has been deprecated in favor of "devm_drm_of_get_bridge". Switch to the new function and reduce boilerplate. Signed-off-by: José Expósito <jose.exposito89(a)gmail.com> --- v2: (Thanks to Liu Ying) - Rebase on top of drm-misc-next - Remove drm_of_panel_bridge_remove --- drivers/gpu/drm/bridge/nwl-dsi.c | 23 ++++------------------- 1 file changed, 4 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c index e34fb09b90b9..de62e3fc6a59 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -912,19 +912,11 @@ static int nwl_dsi_bridge_attach(struct drm_bridge *bridge, { struct nwl_dsi *dsi = bridge_to_dsi(bridge); struct drm_bridge *panel_bridge; - struct drm_panel *panel; - int ret; - - ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel, - &panel_bridge); - if (ret) - return ret; - if (panel) { - panel_bridge = drm_panel_bridge_add(panel); - if (IS_ERR(panel_bridge)) - return PTR_ERR(panel_bridge); - } + panel_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, + 1, 0); + if (IS_ERR(panel_bridge)) + return PTR_ERR(panel_bridge); if (!panel_bridge) return -EPROBE_DEFER; @@ -932,12 +924,6 @@ static int nwl_dsi_bridge_attach(struct drm_bridge *bridge, return drm_bridge_attach(bridge->encoder, panel_bridge, bridge, flags); } -static void nwl_dsi_bridge_detach(struct drm_bridge *bridge) -{ struct nwl_dsi *dsi = bridge_to_dsi(bridge); - - drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0); -} - static u32 *nwl_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, @@ -983,7 +969,6 @@ static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = { .mode_set = nwl_dsi_bridge_mode_set, .mode_valid = nwl_dsi_bridge_mode_valid, .attach = nwl_dsi_bridge_attach, - .detach = nwl_dsi_bridge_detach, }; static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) -- 2.25.1

3 3

[PATCH] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
by Matt Atwood 28 Mar '22

28 Mar '22

Newer platforms have DSS that aren't necessarily available for both geometry and compute, two queries will need to exist. This introduces the first, when passing a valid engine class and engine instance in the flags returns a topology describing geometry. v2: fix white space errors v3: change flags from hosting 2 8 bit numbers to holding a i915_engine_class_instance struct Cc: Ashutosh Dixit <ashutosh.dixit(a)intel.com> Cc: Matt Roper <matthew.d.roper(a)intel.com> Cc: Joonas Lahtinen <joonas.lahtinen(a)linux.intel.com> UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143 Signed-off-by: Matt Atwood <matthew.s.atwood(a)intel.com> --- drivers/gpu/drm/i915/i915_query.c | 68 ++++++++++++++++++++++--------- include/uapi/drm/i915_drm.h | 24 +++++++---- 2 files changed, 65 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 2dfbc22857a3..fcb374201edb 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -9,6 +9,7 @@ #include "i915_drv.h" #include "i915_perf.h" #include "i915_query.h" +#include "gt/intel_engine_user.h" #include <uapi/drm/i915_drm.h> static int copy_query_item(void *query_hdr, size_t query_sz, @@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t query_sz, return 0; } -static int query_topology_info(struct drm_i915_private *dev_priv, - struct drm_i915_query_item *query_item) +static int fill_topology_info(const struct sseu_dev_info *sseu, + struct drm_i915_query_item *query_item, + const u8 *subslice_mask) { - const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu; struct drm_i915_query_topology_info topo; u32 slice_length, subslice_length, eu_length, total_length; int ret; - if (query_item->flags != 0) - return -EINVAL; + BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); if (sseu->max_slices == 0) return -ENODEV; - BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); - slice_length = sizeof(sseu->slice_mask); subslice_length = sseu->max_slices * sseu->ss_stride; eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride; total_length = sizeof(topo) + slice_length + subslice_length + eu_length; - ret = copy_query_item(&topo, sizeof(topo), total_length, - query_item); + ret = copy_query_item(&topo, sizeof(topo), total_length, query_item); + if (ret != 0) return ret; - if (topo.flags != 0) - return -EINVAL; - memset(&topo, 0, sizeof(topo)); topo.max_slices = sseu->max_slices; topo.max_subslices = sseu->max_subslices; @@ -69,27 +64,61 @@ static int query_topology_info(struct drm_i915_private *dev_priv, topo.eu_stride = sseu->eu_stride; if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), - &topo, sizeof(topo))) + &topo, sizeof(topo))) return -EFAULT; if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)), - &sseu->slice_mask, slice_length)) + &sseu->slice_mask, slice_length)) return -EFAULT; if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + - sizeof(topo) + slice_length), - sseu->subslice_mask, subslice_length)) + sizeof(topo) + slice_length), + subslice_mask, subslice_length)) return -EFAULT; if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + - sizeof(topo) + - slice_length + subslice_length), - sseu->eu_mask, eu_length)) + sizeof(topo) + + slice_length + subslice_length), + sseu->eu_mask, eu_length)) return -EFAULT; return total_length; } +static int query_topology_info(struct drm_i915_private *dev_priv, + struct drm_i915_query_item *query_item) +{ + const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu; + + if (query_item->flags != 0) + return -EINVAL; + + return fill_topology_info(sseu, query_item, sseu->subslice_mask); +} + +static int query_geometry_subslices(struct drm_i915_private *i915, + struct drm_i915_query_item *query_item) +{ + const struct sseu_dev_info *sseu; + struct intel_engine_cs *engine; + struct i915_engine_class_instance classinstance; + + if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) + return -ENODEV; + + classinstance = *((struct i915_engine_class_instance *)&query_item->flags); + + engine = intel_engine_lookup_user(i915, (u8) classinstance.engine_class, + (u8) classinstance.engine_instance); + + if (!engine) + return -EINVAL; + + sseu = &engine->gt->info.sseu; + + return fill_topology_info(sseu, query_item, sseu->geometry_subslice_mask); +} + static int query_engine_info(struct drm_i915_private *i915, struct drm_i915_query_item *query_item) @@ -485,6 +514,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, query_engine_info, query_perf_config, query_memregion_info, + query_geometry_subslices, }; int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 05c3642aaece..b539c83a4034 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2687,10 +2687,11 @@ struct drm_i915_perf_oa_config { struct drm_i915_query_item { /** @query_id: The id for this query */ __u64 query_id; -#define DRM_I915_QUERY_TOPOLOGY_INFO 1 -#define DRM_I915_QUERY_ENGINE_INFO 2 -#define DRM_I915_QUERY_PERF_CONFIG 3 -#define DRM_I915_QUERY_MEMORY_REGIONS 4 +#define DRM_I915_QUERY_TOPOLOGY_INFO 1 +#define DRM_I915_QUERY_ENGINE_INFO 2 +#define DRM_I915_QUERY_PERF_CONFIG 3 +#define DRM_I915_QUERY_MEMORY_REGIONS 4 +#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 5 /* Must be kept compact -- no holes and well documented */ /** @@ -2714,6 +2715,9 @@ struct drm_i915_query_item { * - DRM_I915_QUERY_PERF_CONFIG_LIST * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID + * + * When query_id == DRM_I915_QUERY_GEOMETRY_SUBSLICES must have a valid + * i915_engine_class_instance struct. */ __u32 flags; #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 @@ -2772,16 +2776,20 @@ struct drm_i915_query { }; /* - * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO : + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO, + * DRM_I915_QUERY_GEOMETRY_SUBSLICE: * * data: contains the 3 pieces of information : * - * - the slice mask with one bit per slice telling whether a slice is - * available. The availability of slice X can be queried with the following - * formula : + * - For DRM_I915_QUERY_TOPOLOGY_INFO the slice mask with one bit per slice + * telling whether a slice is available. The availability of slice X can be + * queried with the following formula : * * (data[X / 8] >> (X % 8)) & 1 * + * - For DRM_I915_QUERY_GEOMETRY_SUBSLICES Slices are equal to 1 and this field + * is not used. + * * - the subslice mask for each slice with one bit per subslice telling * whether a subslice is available. Gen12 has dual-subslices, which are * similar to two gen11 subslices. For gen12, this array represents dual- -- 2.21.3

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[PATCH 0/3] drm: omapdrm: Fix excessive GEM buffers DMM/CMA usage
by Ivaylo Dimitrov 28 Mar '22

28 Mar '22

This patch series fixes excessive DMM or CMA usage of GEM buffers leading to various runtime allocation failures. The series enables daily usage of devices without exausting limited resources like CMA or DMM space if GPU rendering is needed. The first patch doesn't bring any functional changes, it just moves some TILER/DMM related code to a separate function, to simplify the review of the next two patches. The second patch allows off-CPU rendering to non-scanout buffers. Without that patch, it is basically impossible to use the driver allocated GEM buffers on OMAP3 for anything else but a basic CPU rendered examples as if we want GPU rendering, we must allocate buffers as scanout buffers, which are CMA allocated. CMA soon gets fragmented and we start seeing allocation failures. Such failres in Xorg cannot be handeled gracefully, so the system is basically unusable. Third patch fixes similar issue on OMAP4/5, where DMM/TILER spaces get fragmented with time, leading to allocation failures. Series were tested on Motolola Droid4 and Nokia N900, with OMAP DDX and PVR EXA from https://github.com/maemo-leste/xf86-video-omap Ivaylo Dimitrov (3): drm: omapdrm: simplify omap_gem_pin drm: omapdrm: Support exporting of non-contiguous GEM BOs drm: omapdrm: Do no allocate non-scanout GEMs through DMM/TILER drivers/gpu/drm/omapdrm/omap_gem.c | 198 +++++++++++++++++------------- drivers/gpu/drm/omapdrm/omap_gem.h | 3 +- drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c | 5 +- 3 files changed, 116 insertions(+), 90 deletions(-) -- 1.9.1

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dri-devel March 2022