dri-devel March 2022

dri-devel@lists.freedesktop.org

370 participants
780 discussions

[PATCH v3 00/21] DEPT(Dependency Tracker)
by Byungchul Park 04 Mar '22

04 Mar '22

I didn't want to bother you so I was planning to send the next spin after making more progress. However, PATCH v2 reports too many false positives because Dept tracked the bit_wait_table[] wrong way - I apologize for that. So I decided to send PATCH v3 first before going further for those who want to run Dept for now. There might still be some false positives but not overwhelming. --- Hi Linus and folks, I've been developing a tool for detecting deadlock possibilities by tracking wait/event rather than lock(?) acquisition order to try to cover all synchonization machanisms. It's done on v5.17-rc1 tag. https://github.com/lgebyungchulpark/linux-dept/commits/dept1.14_on_v5.17-rc1 Benifit: 0. Works with all lock primitives. 1. Works with wait_for_completion()/complete(). 2. Works with 'wait' on PG_locked. 3. Works with 'wait' on PG_writeback. 4. Works with swait/wakeup. 5. Works with waitqueue. 6. Multiple reports are allowed. 7. Deduplication control on multiple reports. 8. Withstand false positives thanks to 6. 9. Easy to tag any wait/event. Future work: 0. To make it more stable. 1. To separates Dept from Lockdep. 2. To improves performance in terms of time and space. 3. To use Dept as a dependency engine for Lockdep. 4. To add any missing tags of wait/event in the kernel. 5. To deduplicate stack trace. How to interpret reports: 1. E(event) in each context cannot be triggered because of the W(wait) that cannot be woken. 2. The stack trace helping find the problematic code is located in each conext's detail. Thanks, Byungchul --- Changes from v2: 1. Disable Dept on bit_wait_table[] in sched/wait_bit.c reporting a lot of false positives, which is my fault. Wait/event for bit_wait_table[] should've been tagged in a higher layer for better work, which is a future work. (feedback from Jan Kara) 2. Disable Dept on crypto_larval's completion to prevent a false positive. Changes from v1: 1. Fix coding style and typo. (feedback from Steven) 2. Distinguish each work context from another in workqueue. 3. Skip checking lock acquisition with nest_lock, which is about correct lock usage that should be checked by Lockdep. Changes from RFC: 1. Prevent adding a wait tag at prepare_to_wait() but __schedule(). (feedback from Linus and Matthew) 2. Use try version at lockdep_acquire_cpus_lock() annotation. 3. Distinguish each syscall context from another. Byungchul Park (21): llist: Move llist_{head,node} definition to types.h dept: Implement Dept(Dependency Tracker) dept: Embed Dept data in Lockdep dept: Add a API for skipping dependency check temporarily dept: Apply Dept to spinlock dept: Apply Dept to mutex families dept: Apply Dept to rwlock dept: Apply Dept to wait_for_completion()/complete() dept: Apply Dept to seqlock dept: Apply Dept to rwsem dept: Add proc knobs to show stats and dependency graph dept: Introduce split map concept and new APIs for them dept: Apply Dept to wait/event of PG_{locked,writeback} dept: Apply SDT to swait dept: Apply SDT to wait(waitqueue) locking/lockdep, cpu/hotplus: Use a weaker annotation in AP thread dept: Distinguish each syscall context from another dept: Distinguish each work from another dept: Disable Dept within the wait_bit layer by default dept: Add nocheck version of init_completion() dept: Disable Dept on struct crypto_larval's completion for now crypto/api.c | 7 +- include/linux/completion.h | 50 +- include/linux/dept.h | 535 +++++++ include/linux/dept_page.h | 78 ++ include/linux/dept_sdt.h | 62 + include/linux/hardirq.h | 3 + include/linux/irqflags.h | 33 +- include/linux/llist.h | 8 - include/linux/lockdep.h | 158 ++- include/linux/lockdep_types.h | 3 + include/linux/mutex.h | 33 + include/linux/page-flags.h | 45 +- include/linux/pagemap.h | 7 +- include/linux/percpu-rwsem.h | 10 +- include/linux/rtmutex.h | 7 + include/linux/rwlock.h | 52 + include/linux/rwlock_api_smp.h | 8 +- include/linux/rwlock_types.h | 7 + include/linux/rwsem.h | 33 + include/linux/sched.h | 7 + include/linux/seqlock.h | 59 +- include/linux/spinlock.h | 26 + include/linux/spinlock_types_raw.h | 13 + include/linux/swait.h | 4 + include/linux/types.h | 8 + include/linux/wait.h | 6 +- init/init_task.c | 2 + init/main.c | 4 + kernel/Makefile | 1 + kernel/cpu.c | 2 +- kernel/dependency/Makefile | 4 + kernel/dependency/dept.c | 2712 ++++++++++++++++++++++++++++++++++++ kernel/dependency/dept_hash.h | 10 + kernel/dependency/dept_internal.h | 26 + kernel/dependency/dept_object.h | 13 + kernel/dependency/dept_proc.c | 92 ++ kernel/entry/common.c | 3 + kernel/exit.c | 1 + kernel/fork.c | 2 + kernel/locking/lockdep.c | 12 +- kernel/module.c | 2 + kernel/sched/completion.c | 12 +- kernel/sched/core.c | 3 + kernel/sched/swait.c | 10 + kernel/sched/wait.c | 16 + kernel/sched/wait_bit.c | 5 +- kernel/softirq.c | 6 +- kernel/trace/trace_preemptirq.c | 19 +- kernel/workqueue.c | 3 + lib/Kconfig.debug | 21 + mm/filemap.c | 68 + mm/page_ext.c | 5 + 52 files changed, 4257 insertions(+), 59 deletions(-) create mode 100644 include/linux/dept.h create mode 100644 include/linux/dept_page.h create mode 100644 include/linux/dept_sdt.h create mode 100644 kernel/dependency/Makefile create mode 100644 kernel/dependency/dept.c create mode 100644 kernel/dependency/dept_hash.h create mode 100644 kernel/dependency/dept_internal.h create mode 100644 kernel/dependency/dept_object.h create mode 100644 kernel/dependency/dept_proc.c -- 1.9.1

2 29

[PATCH V2 00/12] drm: bridge: icn6211: Fix hard-coded panel settings and add I2C support
by Marek Vasut 04 Mar '22

04 Mar '22

This series fixes multiple problems with the ICN6211 driver and adds support for configuration of the chip via I2C bus. First, in the current state, the ICN6211 driver hard-codes DPI timing and clock settings specific to some unknown panel. The settings provided by panel driver are ignored. Using any other panel than the one for which this driver is currently hard-coded can lead to permanent damage of the panel (per display supplier warning, and it sure did in my case. The damage looks like multiple rows of dead pixels at the bottom of the panel, and this is not going away even after long power off time). Much of this series thus fixes incorrect register layout, DPI timing programming, clock generation by adding actual PLL configuration code. This series also adds lane count decoding instead of using hard-coded value, and fills in a couple of registers with likely correct default values. Second, this series adds support for I2C configuration of the ICN6211. The device can be configured either via DSI command mode or via I2C, the register layout is the same in both cases. Since the datasheet for this device is very hard to come by, a lot of information has been salvaged from [1] and [2]. [1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/gpu/drm/… [2] https://github.com/tdjastrzebski/ICN6211-Configurator Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Maxime Ripard <maxime(a)cerno.tech> Cc: Robert Foss <robert.foss(a)linaro.org> Cc: Sam Ravnborg <sam(a)ravnborg.org> Cc: Thomas Zimmermann <tzimmermann(a)suse.de> To: dri-devel(a)lists.freedesktop.org Marek Vasut (12): drm: bridge: icn6211: Fix register layout drm: bridge: icn6211: Fix HFP_HSW_HBP_HI and HFP_MIN handling drm: bridge: icn6211: Add HS/VS/DE polarity handling drm: bridge: icn6211: Add DSI lane count DT property parsing drm: bridge: icn6211: Add generic DSI-to-DPI PLL configuration drm: bridge: icn6211: Use DSI burst mode without EoT and with LP command mode drm: bridge: icn6211: Disable DPI color swap drm: bridge: icn6211: Set SYS_CTRL_1 to value used in examples drm: bridge: icn6211: Implement atomic_get_input_bus_fmts drm: bridge: icn6211: Add I2C configuration support drm: bridge: icn6211: Rename ICN6211_DSI to chipone_writeb drm: bridge: icn6211: Read and validate chip IDs before configuration drivers/gpu/drm/bridge/chipone-icn6211.c | 510 ++++++++++++++++++++--- 1 file changed, 458 insertions(+), 52 deletions(-) -- 2.34.1

2 28

[PATCH v2] drm/msm/disp/dpu1: add inline rotation support for sc7280 target
by Vinod Polimera 04 Mar '22

04 Mar '22

- Some DPU versions support inline rot90. It is supported only for limited amount of UBWC formats. - There are two versions of inline rotators, v1 (present on sm8250 and sm7250) and v2 (sc7280). These versions differ in the list of supported formats and in the scaler possibilities. Changes in RFC: - Rebase changes to the latest code base. - Append rotation config variables with v2 and remove unused variables.(Dmitry) - Move pixel_ext setup separately from scaler3 config.(Dmitry) - Add 270 degree rotation to supported rotation list.(Dmitry) Changes in V2: - Remove unused macros and fix indentation. - Add check if 90 rotation is supported and add supported rotations to rot_cfg. Signed-off-by: Kalyan Thota <quic_kalyant(a)quicinc.com> Signed-off-by: Vinod Polimera <quic_vpolimer(a)quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 44 +++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 17 ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 108 +++++++++++++++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 + 4 files changed, 134 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index aa75991..7cd07be 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -25,6 +25,9 @@ #define VIG_SM8250_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) +#define VIG_SC7280_MASK \ + (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) + #define DMA_SDM845_MASK \ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ @@ -177,6 +180,11 @@ static const uint32_t plane_formats_yuv[] = { DRM_FORMAT_YVU420, }; +static const uint32_t rotation_v2_formats[] = { + DRM_FORMAT_NV12, + /* TODO add formats after validation */ +}; + /************************************************************* * DPU sub blocks config *************************************************************/ @@ -464,8 +472,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = { *************************************************************/ /* SSPP common configuration */ - -#define _VIG_SBLK(num, sdma_pri, qseed_ver) \ +#define _VIG_SBLK(num, sdma_pri, qseed_ver, rot_cfg) \ { \ .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ @@ -482,6 +489,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = { .num_formats = ARRAY_SIZE(plane_formats_yuv), \ .virt_format_list = plane_formats, \ .virt_num_formats = ARRAY_SIZE(plane_formats), \ + .rotation_cfg = rot_cfg, \ } #define _DMA_SBLK(num, sdma_pri) \ @@ -497,14 +505,21 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = { .virt_num_formats = ARRAY_SIZE(plane_formats), \ } +static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { + .rot_maxheight = 1088, + .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), + .rot_format_list = rotation_v2_formats, + .rot_supported = DRM_MODE_ROTATE_MASK | DRM_MODE_REFLECT_MASK, +}; + static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = - _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3, NULL); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = - _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3, NULL); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = - _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3, NULL); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = - _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3, NULL); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); @@ -543,7 +558,10 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { }; static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = - _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4, NULL); + +static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = + _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); static const struct dpu_sspp_cfg sc7180_sspp[] = { SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, @@ -557,13 +575,13 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { }; static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = - _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE, NULL); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = - _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE, NULL); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = - _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE, NULL); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = - _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE, NULL); static const struct dpu_sspp_cfg sm8250_sspp[] = { SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK, @@ -585,8 +603,8 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { }; static const struct dpu_sspp_cfg sc7280_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, - sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK, + sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 31af04a..269eb45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -109,6 +109,7 @@ enum { * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec * @DPU_SSPP_CDP Supports client driven prefetch + * @DPU_SSPP_INLINE_ROTATION Support inline rotation * @DPU_SSPP_MAX maximum value */ enum { @@ -129,6 +130,7 @@ enum { DPU_SSPP_TS_PREFILL, DPU_SSPP_TS_PREFILL_REC1, DPU_SSPP_CDP, + DPU_SSPP_INLINE_ROTATION, DPU_SSPP_MAX }; @@ -312,6 +314,20 @@ struct dpu_qos_lut_tbl { }; /** + * struct dpu_rotation_cfg - define inline rotation config + * @rot_maxheight: max pre rotated height allowed for rotation + * @rot_num_formats: count of the formats + * @rot_format_list: list of supported rotator formats + * @rot_supported: allowed rotations + */ +struct dpu_rotation_cfg { + u32 rot_maxheight; + u32 rot_num_formats; + const u32 *rot_format_list; + u32 rot_supported; +}; + +/** * struct dpu_caps - define DPU capabilities * @max_mixer_width max layer mixer line width support. * @max_mixer_blendstages max layer mixer blend stages or @@ -387,6 +403,7 @@ struct dpu_sspp_sub_blks { u32 num_formats; const u32 *virt_format_list; u32 virt_num_formats; + const struct dpu_rotation_cfg *rotation_cfg; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index ca75089..031a0ff 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -528,11 +528,19 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, struct dpu_plane_state *pstate, uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, struct dpu_hw_scaler3_cfg *scale_cfg, - struct dpu_hw_pixel_ext *pixel_ext, const struct dpu_format *fmt, uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) { uint32_t i; + bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90); + + /* + * For inline rotation cases, scaler config is post-rotation, + * so swap the dimensions here. However, pixel extension will + * need pre-rotation settings. + */ + if (inline_rotation) + swap(src_w, src_h); scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); @@ -571,11 +579,6 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; } - - pixel_ext->num_ext_pxls_top[i] = - scale_cfg->src_height[i]; - pixel_ext->num_ext_pxls_left[i] = - scale_cfg->src_width[i]; } if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) && (src_w == dst_w)) @@ -591,6 +594,24 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, scale_cfg->enable = 1; } +static void _dpu_plane_setup_pixel_ext(struct dpu_plane_state *pstate, + struct dpu_hw_scaler3_cfg *scale_cfg, + struct dpu_hw_pixel_ext *pixel_ext) +{ + int i = 0; + bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90); + + if (!scale_cfg && !scale_cfg->enable) + return; + + for (i = 0; i < DPU_MAX_PLANES; i++) { + pixel_ext->num_ext_pxls_top[i] = inline_rotation ? + scale_cfg->src_width[i] : scale_cfg->src_height[i]; + pixel_ext->num_ext_pxls_left[i] = inline_rotation ? + scale_cfg->src_height[i] : scale_cfg->src_width[i]; + } +} + static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { { /* S15.16 format */ @@ -665,9 +686,12 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, drm_rect_height(&pipe_cfg->src_rect), drm_rect_width(&pipe_cfg->dst_rect), drm_rect_height(&pipe_cfg->dst_rect), - &scaler3_cfg, &pixel_ext, fmt, + &scaler3_cfg, fmt, info->hsub, info->vsub); + /* configure pixel extension based on scalar config */ + _dpu_plane_setup_pixel_ext(pstate, &scaler3_cfg, &pixel_ext); + if (pdpu->pipe_hw->ops.setup_pe) pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, &pixel_ext); @@ -967,15 +991,17 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, const struct dpu_format *fmt; struct drm_rect src, dst, fb_rect = { 0 }; uint32_t min_src_size, max_linewidth; + unsigned int rotation = 0; + const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap; if (new_plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); - min_scale = FRAC_16_16(1, pdpu->pipe_hw->cap->sblk->maxupscale); + min_scale = FRAC_16_16(1, pipe_hw_caps->sblk->maxupscale); ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, min_scale, - pdpu->pipe_hw->cap->sblk->maxdwnscale << 16, + pipe_hw_caps->sblk->maxdwnscale << 16, true, true); if (ret) { DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); @@ -1001,8 +1027,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; if (DPU_FORMAT_IS_YUV(fmt) && - (!(pdpu->pipe_hw->cap->features & DPU_SSPP_SCALER) || - !(pdpu->pipe_hw->cap->features & DPU_SSPP_CSC_ANY))) { + (!(pipe_hw_caps->features & DPU_SSPP_SCALER) || + !(pipe_hw_caps->features & DPU_SSPP_CSC_ANY))) { DPU_DEBUG_PLANE(pdpu, "plane doesn't have scaler/csc for yuv\n"); return -EINVAL; @@ -1035,6 +1061,42 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -E2BIG; } + if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && + (pipe_hw_caps->sblk->rotation_cfg)) { + rotation = drm_rotation_simplify(new_plane_state->rotation, + pipe_hw_caps->sblk->rotation_cfg->rot_supported); + + if (rotation & DRM_MODE_ROTATE_90) { + bool found = false; + u32 i, num_formats; + const u32 *supported_formats; + + if ((drm_rect_width(&src) > + pipe_hw_caps->sblk->rotation_cfg->rot_maxheight)) { + DPU_DEBUG_PLANE(pdpu, + "invalid height for inline rot:%d max:%d\n", + src.y2, pipe_hw_caps->sblk->rotation_cfg->rot_maxheight); + return -EINVAL; + } + + supported_formats = pipe_hw_caps->sblk->rotation_cfg->rot_format_list; + num_formats = pipe_hw_caps->sblk->rotation_cfg->rot_num_formats; + + for (i = 0; i < num_formats; i++) { + /* check for valid formats supported by inline rotation */ + if (fmt->base.pixel_format == supported_formats[i] && + DPU_FORMAT_IS_UBWC(fmt)) + found = true; + } + + if (!found || !num_formats) { + DPU_DEBUG_PLANE(pdpu, + "supported_format not found num:%d\n", num_formats); + return -EINVAL; + } + } + } + pstate->rotation = rotation; pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); return 0; @@ -1150,21 +1212,18 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) pstate->multirect_mode); if (pdpu->pipe_hw->ops.setup_format) { - unsigned int rotation; src_flags = 0x0; - rotation = drm_rotation_simplify(state->rotation, - DRM_MODE_ROTATE_0 | - DRM_MODE_REFLECT_X | - DRM_MODE_REFLECT_Y); - - if (rotation & DRM_MODE_REFLECT_X) + if (pstate->rotation & DRM_MODE_REFLECT_X) src_flags |= DPU_SSPP_FLIP_LR; - if (rotation & DRM_MODE_REFLECT_Y) + if (pstate->rotation & DRM_MODE_REFLECT_Y) src_flags |= DPU_SSPP_FLIP_UD; + if (pstate->rotation & DRM_MODE_ROTATE_90) + src_flags |= DPU_SSPP_ROT_90; + /* update format */ pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, pstate->multirect_index); @@ -1462,6 +1521,8 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, int zpos_max = DPU_ZPOS_MAX; uint32_t num_formats; int ret = -EINVAL; + unsigned int supported_rotations = DRM_MODE_ROTATE_0 | + DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; /* create and zero local structure */ pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL); @@ -1529,12 +1590,11 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE)); + if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) + supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270; + drm_plane_create_rotation_property(plane, - DRM_MODE_ROTATE_0, - DRM_MODE_ROTATE_0 | - DRM_MODE_ROTATE_180 | - DRM_MODE_REFLECT_X | - DRM_MODE_REFLECT_Y); + DRM_MODE_ROTATE_0, supported_rotations); drm_plane_enable_fb_damage_clips(plane); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 9d51dad..e72da02 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -25,6 +25,7 @@ * @pending: whether the current update is still pending * @plane_fetch_bw: calculated BW per plane * @plane_clk: calculated clk per plane + * @rotation: simplified drm rotation hint */ struct dpu_plane_state { struct drm_plane_state base; @@ -37,6 +38,7 @@ struct dpu_plane_state { u64 plane_fetch_bw; u64 plane_clk; + unsigned int rotation; }; /** -- 2.7.4

3 2

[PATCH v2 0/4] drm/msm: rework MDSS drivers
by Dmitry Baryshkov 03 Mar '22

03 Mar '22

These patches coninue work started by AngeloGioacchino Del Regno in the previous cycle by further decoupling and dissecting MDSS and MDP drivers probe/binding paths. This removes code duplication between MDP5 and DPU1 MDSS drivers, by merging them and moving to the top level. This patchset depends on the patches 1 and 2 from [1] Changes since v1: - Rebased on top of [2] and [1] [1] https://patchwork.freedesktop.org/series/99066/ [2] https://patchwork.freedesktop.org/series/98521/ Dmitry Baryshkov (4): drm/msm: unify MDSS drivers drm/msm: remove extra indirection for msm_mdss drm/msm: split the main platform driver drm/msm: stop using device's match data pointer drivers/gpu/drm/msm/Makefile | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 260 ------------- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 68 +++- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 11 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 252 ------------- drivers/gpu/drm/msm/msm_drv.c | 260 +++---------- drivers/gpu/drm/msm/msm_drv.h | 16 + drivers/gpu/drm/msm/msm_kms.h | 18 - drivers/gpu/drm/msm/msm_mdss.c | 438 ++++++++++++++++++++++ 10 files changed, 578 insertions(+), 758 deletions(-) delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c delete mode 100644 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c create mode 100644 drivers/gpu/drm/msm/msm_mdss.c base-commit: 6ed95285382d6f90a3c3a11d5806a5eb7db715c3 prerequisite-patch-id: b5572c353efa8ebefb32fc70e54bc537f78ff2bd prerequisite-patch-id: 40a854aee69b6ddf5b1c33cac3647efae3e3ebf1 prerequisite-patch-id: 8b687a19047983e26262a1bb2feda8a9fd5bc97f prerequisite-patch-id: e2d7f768b4b287c80797635f3ed5b6353b12adb5 prerequisite-patch-id: cac9fb235e3510b5bcb713f602658e6233cd308b -- 2.34.1

2 10

[PATCH] dt-bindings: gpu: Convert aspeed-gfx bindings to yaml
by Joel Stanley 03 Mar '22

03 Mar '22

Convert the bindings to yaml and add the ast2600 compatible string. Signed-off-by: Joel Stanley <joel(a)jms.id.au> --- .../devicetree/bindings/gpu/aspeed,gfx.yaml | 69 +++++++++++++++++++ .../devicetree/bindings/gpu/aspeed-gfx.txt | 41 ----------- 2 files changed, 69 insertions(+), 41 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpu/aspeed,gfx.yaml delete mode 100644 Documentation/devicetree/bindings/gpu/aspeed-gfx.txt diff --git a/Documentation/devicetree/bindings/gpu/aspeed,gfx.yaml b/Documentation/devicetree/bindings/gpu/aspeed,gfx.yaml new file mode 100644 index 000000000000..8ddc4fa6e8e4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/aspeed,gfx.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/aspeed,gfx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED GFX display device + +maintainers: + - Joel Stanley <joel(a)jms.id.au> + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-gfx + - aspeed,ast2500-gfx + - aspeed,ast2600-gfx + - const: syscon + + reg: + minItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + memory-region: true + + syscon: true + + reg-io-width: true + +required: + - reg + - compatible + - interrupts + - clocks + - resets + - memory-region + - syscon + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/aspeed-clock.h> + gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_CRT1>; + interrupts = <0x19>; + syscon = <&syscon>; + memory-region = <&gfx_memory>; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; diff --git a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt deleted file mode 100644 index 958bdf962339..000000000000 --- a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt +++ /dev/null @@ -1,41 +0,0 @@ -Device tree configuration for the GFX display device on the ASPEED SoCs - -Required properties: - - compatible - * Must be one of the following: - + aspeed,ast2500-gfx - + aspeed,ast2400-gfx - * In addition, the ASPEED pinctrl bindings require the 'syscon' property to - be present - - - reg: Physical base address and length of the GFX registers - - - interrupts: interrupt number for the GFX device - - - clocks: clock number used to generate the pixel clock - - - resets: reset line that must be released to use the GFX device - - - memory-region: - Phandle to a memory region to allocate from, as defined in - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - - -Example: - -gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; - clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; - resets = <&syscon ASPEED_RESET_CRT1>; - interrupts = <0x19>; - memory-region = <&gfx_memory>; -}; - -gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; -}; -- 2.34.1

3 4

[PATCH 0/4] drm/msm: Clear perf counters across context switch
by Rob Clark 03 Mar '22

03 Mar '22

From: Rob Clark <robdclark(a)chromium.org> Some clever folks figured out a way to use performance counters as a side-channel[1]. But, other than the special case of using the perf counters for system profiling, we can reset the counters across context switches to protect against this. This series introduces a SYSPROF param which a sufficiently privilaged userspace (like Mesa's pps-producer, which already must run as root) to opt-out, and makes the default behavior to reset counters on context switches. [1] https://dl.acm.org/doi/pdf/10.1145/3503222.3507757 Rob Clark (4): drm/msm: Update generated headers drm/msm: Add SET_PARAM ioctl drm/msm: Add SYSPROF param drm/msm/a6xx: Zap counters across context switch drivers/gpu/drm/msm/adreno/a2xx.xml.h | 26 +- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a3xx.xml.h | 30 +- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a4xx.xml.h | 112 ++- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a5xx.xml.h | 63 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a6xx.xml.h | 674 +++++++++++------- drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 26 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 30 + .../gpu/drm/msm/adreno/adreno_common.xml.h | 31 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 14 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 + drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 46 +- drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h | 37 +- drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h | 37 +- drivers/gpu/drm/msm/disp/mdp_common.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h | 37 +- .../gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h | 480 ------------- drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h | 43 +- drivers/gpu/drm/msm/dsi/mmss_cc.xml.h | 37 +- drivers/gpu/drm/msm/dsi/sfpb.xml.h | 37 +- drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 37 +- drivers/gpu/drm/msm/hdmi/qfprom.xml.h | 37 +- drivers/gpu/drm/msm/msm_drv.c | 28 + drivers/gpu/drm/msm/msm_gpu.h | 29 + drivers/gpu/drm/msm/msm_submitqueue.c | 34 + include/uapi/drm/msm_drm.h | 28 +- 34 files changed, 1051 insertions(+), 1130 deletions(-) delete mode 100644 drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h -- 2.35.1

3 11

[PATCH] drm/nouveau/instmem: fix uninitialized_var.cocci warning
by Guo Zhengkui 03 Mar '22

03 Mar '22

Fix following coccicheck warning: drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c:316:11-12: WARNING this kind of initialization is deprecated. `void *map = map` has the same form of uninitialized_var() macro. I remove the redundant assignement. It has been tested with gcc (Debian 8.3.0-6) 8.3.0. The patch which removed uninitialized_var() is: https://lore.kernel.org/all/20121028102007.GA7547@gmail.com/ And there is very few "/* GCC */" comments in the Linux kernel code now. Signed-off-by: Guo Zhengkui <guozhengkui(a)vivo.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c index 96aca0edfa3c..c51bac76174c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c @@ -313,7 +313,7 @@ nv50_instobj_dtor(struct nvkm_memory *memory) struct nv50_instobj *iobj = nv50_instobj(memory); struct nvkm_instmem *imem = &iobj->imem->base; struct nvkm_vma *bar; - void *map = map; + void *map; mutex_lock(&imem->mutex); if (likely(iobj->lru.next)) -- 2.20.1

2 1

[PATCH v3 0/6] drm/msm/dpu: simplify IRQ helpers
by Dmitry Baryshkov 03 Mar '22

03 Mar '22

This is the second part of https://patchwork.freedesktop.org/series/91631/ reworked and cleaned up. Changes since v1: - Fix warning ins dpu_trace.h related to dpu_core_irq_unregister_callback event Changes since v1: - Use ARRAY_SIZE() rather INTR_IDX_MAX when clearing irq arrays. Changes since the original pull request: - Split applied patches - Add unlikely and WARN_ON in dpu_core_irq_register_callback() - Remove extra checks in dpu_core_irq_unregister_callback() - Remove unused arguments of dpu_core_irq_unregister_callback() - Clean the cb and arg in dpu_core_irq_unregister_callback() - Split the last patch. Leave enum dpu_intr_idx intact. Pass irq index, callback and data directly to dpu_encoder helpers. Dmitry Baryshkov (6): drm/msm/dpu: remove extra wrappers around dpu_core_irq drm/msm/dpu: remove always-true argument of dpu_core_irq_read() drm/msm/dpu: allow just single IRQ callback drm/msm/dpu: get rid of dpu_encoder_helper_(un)register_irq drm/msm/dpu: remove struct dpu_encoder_irq drm/msm/dpu: pass irq to dpu_encoder_helper_wait_for_irq() drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 32 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 112 +++---------- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 43 +---- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 92 +++++----- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 51 +++--- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 157 +++++++----------- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 27 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 12 -- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 67 ++++---- 10 files changed, 202 insertions(+), 403 deletions(-) -- 2.34.1

3 11

2022 X.Org Board of Directors Elections timeline extended, Request for nominations
by Lyude Paul 03 Mar '22

03 Mar '22

We are seeking nominations for candidates for election to the X.org Foundation Board of Directors. However, as we presently do not have enough nominations to start the election - the decision has been made to extend the timeline by 2 weeks. Note this is a fairly regular part of the elections process. The new deadline for nominations to the X.org Board of Directors is 23:59 UTC on 20th March 2022. The Board consists of directors elected from the membership. Each year, an election is held to bring the total number of directors to eight. The four members receiving the highest vote totals will serve as directors for two year terms. The directors who received two year terms starting in 2021 were Lyude Paul, Samuel Iglesias Gonsálvez, Manasi D Navare and Daniel Vetter. They will continue to serve until their term ends in 2023. Current directors whose term expires in 2022 are Emma Anholt, Keith Packard, Harry Wentland and Mark Filion. A director is expected to participate in the fortnightly IRC meeting to discuss current business and to attend the annual meeting of the X.Org Foundation, which will be held at a location determined in advance by the Board of Directors. A member may nominate themselves or any other member they feel is qualified. Nominations should be sent to the Election Committee at elections at x.org. Nominees shall be required to be current members of the X.Org Foundation, and submit a personal statement of up to 200 words that will be provided to prospective voters. The collected statements, along with the statement of contribution to the X.Org Foundation in the member's account page on http://members.x.org, will be made available to all voters to help them make their voting decisions. Nominations, membership applications or renewals and completed personal statements must be received no later than 23:59 UTC on 20th March 2022. The slate of candidates will be published 28th March 2022 and candidate Q&A will begin then. The deadline for Xorg membership applications and renewals is 31st March 2022. Cheers, Lyude Paul, on behalf of the X.Org BoD

1 0

[PATCH 0/4] drm/msm/dpu: clearly document INTF_DP vs INTF_EDP difference
by Dmitry Baryshkov 03 Mar '22

03 Mar '22

Recent dicussion on the mailing list [1], [2] outlined a need to document which intf type is used for DP and which one is used for eDP interfaces. This series implements my proposal [3]: - Keep INTF_EDP reserved for 8x74/8x84 - Use INTF_DP for all contemporary DP and eDP ports - Documet this in dpu_hw_mdss.h - Remove INTF_EDP usage in dpu1 driver. Main reasons behind this proposal: - It's not always possible to separate eDP and DP. For example INTF_5 on sc7280 is connected to combo eDP/DP PHY. - Using INTF_EDP would require us to split too many pieces, ending up with a singnificant amount of code duplication... - ... for nothing. From the DPU point of view there is no difference between DP and eDP interfaces as found on current SoC generations. [1]: https://lore.kernel.org/linux-arm-msm/0dac8ffa-89a6-d972-bdc1-3f7755c5169d@… [2]: https://lore.kernel.org/linux-arm-msm/be397e2e-05ab-5c18-8e2d-16c443f0a6d1@… [3]: https://lore.kernel.org/linux-arm-msm/e2fab93e-82a6-4837-4ee5-ee1b16caa84d@… Dmitry Baryshkov (4): drm/msm/dpu: document INTF_EDP/INTF_DP difference drm/msm/dpu: drop INTF_TYPE_MAX symbol drm/msm/dpu: drop obsolete INTF_EDP comment drm/msm/dpu: drop INTF_EDP from interface type conditions .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 +------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 9 ++++++++- 3 files changed, 10 insertions(+), 15 deletions(-) -- 2.34.1

3 9

← Newer
1
...
65
66
67
68
69
70
71
...
78
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel March 2022