dri-devel March 2022

dri-devel@lists.freedesktop.org

370 participants
780 discussions

linux-next: build warning after merge of the drm tree
by Stephen Rothwell 02 Mar '22

02 Mar '22

Hi all, After merging the drm tree, today's linux-next build (htmldocs) produced this warning: include/drm/drm_connector.h:637: warning: Function parameter or member 'edid_hdmi_rgb444_dc_modes' not described in 'drm_display_info' include/drm/drm_connector.h:637: warning: Function parameter or member 'edid_hdmi_ycbcr444_dc_modes' not described in 'drm_display_info' Introduced by commit 4adc33f36d80 ("drm/edid: Split deep color modes between RGB and YUV444") -- Cheers, Stephen Rothwell

1 1

[PATCH v3 0/8] Prep work for next GuC release
by John.C.Harrison＠Intel.com 02 Mar '22

02 Mar '22

From: John Harrison <John.C.Harrison(a)Intel.com> The next GuC firmware release includes some significant backwards breaking API changes. One such is that there is no longer an LRC descriptor pool. A bunch of prep work for that change can be done in advance - the descriptor pool was being used for things it shouldn't really have been used for anyway. v2: Extend commit message on 'better name' patch. Improve 'split apart' patch to include some necessary re-arrangement that was in a later patch and which introduced an unnecessary conditional in said patch too. (review feedback from Daniele) v3: Rebase to newer tree. Signed-off-by: John Harrison <John.C.Harrison(a)Intel.com> John Harrison (8): drm/i915/guc: Do not conflate lrc_desc with GuC id for registration drm/i915/guc: Add an explicit 'submission_initialized' flag drm/i915/guc: Better name for context id limit drm/i915/guc: Split guc_lrc_desc_pin apart drm/i915/guc: Move lrc desc setup to where it is needed drm/i915/guc: Rename desc_idx to ctx_id drm/i915/guc: Drop obsolete H2G definitions drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs drivers/gpu/drm/i915/gt/intel_context.c | 2 +- .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 - drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 + drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 181 ++++++++++-------- drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +- 6 files changed, 109 insertions(+), 84 deletions(-) -- 2.25.1

1 8

[PATCH v5 0/7] Add Aspeed AST2600 soc display support
by Tommy Haung 02 Mar '22

02 Mar '22

v5: Add lost reset define. v4: Add necessary reset control for ast2600. Add chip caps for futher use. These code are test on AST2500 and AST2600 by below steps. 1. Add below config to turn VT and LOGO on. CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LDISC_AUTOLOAD=y CONFIG_DEVMEM=y CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_LOGO=y CONFIG_LOGO_LINUX_CLUT224=y 2. The Linux logo will be shown on the screen, when the BMC boot in Linux. v3: Refine the patch for clear separate purpose. Skip to send devicetree patch v2: Remove some unnecessary patch. Refine for reviwer request. v1: First add patch. Joel Stanley (2): ARM: dts: aspeed: Add GFX node to AST2600 ARM: dts: aspeed: ast2600-evb: Enable GFX device Tommy Haung (1): dt-bindings:ast2600-clock Add CRT reset define tommy-huang (4): drm/aspeed: Update INTR_STS handling drm/aspeed: Add AST2600 chip support drm/aspeed: Add reset and clock for AST2600 arm:boot:dts:aspeed-g6 Add more gfx reset control arch/arm/boot/dts/aspeed-ast2600-evb.dts | 18 +++++++ arch/arm/boot/dts/aspeed-g6.dtsi | 13 +++++ drivers/gpu/drm/aspeed/aspeed_gfx.h | 17 +++++- drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 16 ++++++ drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 65 +++++++++++++++++++++-- include/dt-bindings/clock/ast2600-clock.h | 1 + 6 files changed, 124 insertions(+), 6 deletions(-) -- 2.17.1

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[PATCH] drm/v3d: centralize error handling when init scheduler fails
by Melissa Wen 01 Mar '22

01 Mar '22

Remove redundant error message (since now it is very similar to what we do in drm_sched_init) and centralize all error handling in a unique place, as we follow the same steps in any case of failure. Signed-off-by: Melissa Wen <mwen(a)igalia.com> --- drivers/gpu/drm/v3d/v3d_sched.c | 40 +++++++++++---------------------- 1 file changed, 13 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/v3d/v3d_sched.c b/drivers/gpu/drm/v3d/v3d_sched.c index 39459ae96f30..06238e6d7f5c 100644 --- a/drivers/gpu/drm/v3d/v3d_sched.c +++ b/drivers/gpu/drm/v3d/v3d_sched.c @@ -392,34 +392,24 @@ v3d_sched_init(struct v3d_dev *v3d) hw_jobs_limit, job_hang_limit, msecs_to_jiffies(hang_limit_ms), NULL, NULL, "v3d_bin", v3d->drm.dev); - if (ret) { - dev_err(v3d->drm.dev, "Failed to create bin scheduler: %d.", ret); + if (ret) return ret; - } ret = drm_sched_init(&v3d->queue[V3D_RENDER].sched, &v3d_render_sched_ops, hw_jobs_limit, job_hang_limit, msecs_to_jiffies(hang_limit_ms), NULL, NULL, "v3d_render", v3d->drm.dev); - if (ret) { - dev_err(v3d->drm.dev, "Failed to create render scheduler: %d.", - ret); - v3d_sched_fini(v3d); - return ret; - } + if (ret) + goto fail; ret = drm_sched_init(&v3d->queue[V3D_TFU].sched, &v3d_tfu_sched_ops, hw_jobs_limit, job_hang_limit, msecs_to_jiffies(hang_limit_ms), NULL, NULL, "v3d_tfu", v3d->drm.dev); - if (ret) { - dev_err(v3d->drm.dev, "Failed to create TFU scheduler: %d.", - ret); - v3d_sched_fini(v3d); - return ret; - } + if (ret) + goto fail; if (v3d_has_csd(v3d)) { ret = drm_sched_init(&v3d->queue[V3D_CSD].sched, @@ -427,27 +417,23 @@ v3d_sched_init(struct v3d_dev *v3d) hw_jobs_limit, job_hang_limit, msecs_to_jiffies(hang_limit_ms), NULL, NULL, "v3d_csd", v3d->drm.dev); - if (ret) { - dev_err(v3d->drm.dev, "Failed to create CSD scheduler: %d.", - ret); - v3d_sched_fini(v3d); - return ret; - } + if (ret) + goto fail; ret = drm_sched_init(&v3d->queue[V3D_CACHE_CLEAN].sched, &v3d_cache_clean_sched_ops, hw_jobs_limit, job_hang_limit, msecs_to_jiffies(hang_limit_ms), NULL, NULL, "v3d_cache_clean", v3d->drm.dev); - if (ret) { - dev_err(v3d->drm.dev, "Failed to create CACHE_CLEAN scheduler: %d.", - ret); - v3d_sched_fini(v3d); - return ret; - } + if (ret) + goto fail; } return 0; + +fail: + v3d_sched_fini(v3d); + return ret; } void -- 2.34.1

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[PATCH] dt-bindings: display/msm: Drop bogus interrupt flags cell on MDSS nodes
by Rob Herring 01 Mar '22

01 Mar '22

The MDSS interrupt provider is a single cell, so specifying interrupt flags on the consumers is incorrect. Signed-off-by: Rob Herring <robh(a)kernel.org> --- .../devicetree/bindings/display/msm/dpu-msm8998.yaml | 4 ++-- .../devicetree/bindings/display/msm/dpu-qcm2290.yaml | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml index 167bc48748d7..2df64afb76e6 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -155,7 +155,7 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> - display-subsystem@c900000 { + mdss: display-subsystem@c900000 { compatible = "qcom,msm8998-mdss"; reg = <0x0c900000 0x1000>; reg-names = "mdss"; @@ -192,7 +192,7 @@ examples: clock-names = "iface", "bus", "mnoc", "core", "vsync"; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmpd MSM8998_VDDMX>; diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml index 8766b13f0c46..28617bc1d2ff 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml @@ -197,7 +197,7 @@ examples: power-domains = <&rpmpd QCM2290_VDDCX>; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_NONE>; + interrupts = <0>; ports { #address-cells = <1>; -- 2.32.0

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[PATCH v2 00/13] i915: Prepare for Xe_HP compute engines
by Matt Roper 01 Mar '22

01 Mar '22

The Xe_HP architecture introduces compute engines as a new engine class. These compute command streamers (CCS) are similar to the render engine, except that they're intended for GPGPU usage and lack support for the 3D pipeline. For now we're just sending some initial "under the hood" preparation for CCS engines without actually exposing them to userspace or adding them to any platform's engine list yet. There may be a bit more GuC-related updates necessary before it's safe to expose them, so the actual uabi bits will come later once that's all worked out. Daniele Ceraolo Spurio (3): drm/i915/xehp: compute engine pipe_control drm/i915/xehp/guc: enable compute engine inside GuC drm/i915/xehp: handle fused off CCS engines Matt Roper (8): drm/i915/xehp: Define compute class and engine drm/i915/xehp: CCS shares the render reset domain drm/i915/xehp: Add Compute CS IRQ handlers drm/i915/xehp: CCS should use RCS setup functions drm/i915: Move context descriptor fields to intel_lrc.h drm/i915/xehp: Define context scheduling attributes in lrc descriptor drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE drm/i915/xehp: Add compute workarounds Matthew Brost (1): drm/i915/xehp: Don't support parallel submission on compute / render Srinivasan Shanmugam (1): drm/i915/xehpsdv: Move render/compute engine reset domains related workarounds drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++ .../drm/i915/gem/selftests/i915_gem_context.c | 8 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 35 ++++++-- drivers/gpu/drm/i915/gt/intel_engine.h | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 83 +++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_engine_types.h | 11 ++- drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +- .../drm/i915/gt/intel_execlists_submission.c | 24 +++++- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 ++++ drivers/gpu/drm/i915/gt/intel_gt_irq.c | 15 +++- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 45 +++------- drivers/gpu/drm/i915/gt/intel_lrc.c | 10 ++- drivers/gpu/drm/i915/gt/intel_lrc.h | 51 ++++++++++++ drivers/gpu/drm/i915/gt/intel_sseu.c | 17 +++- drivers/gpu/drm/i915/gt/intel_sseu.h | 4 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 73 +++++++++++++--- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 5 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 32 +++++-- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +++- .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 4 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 4 + 22 files changed, 393 insertions(+), 80 deletions(-) -- 2.34.1

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[pull] drm/msm: drm-msm-next-2022-03-01 for 5.18
by Rob Clark 01 Mar '22

01 Mar '22

Hi Dave & Daniel, This is the main pull for v5.18. We're experimenting a bit with the process this time, with Dmitry collecting display patches and merging them into msm-next with me handling the gpu/etc side of things. Summary of interesting new bits and pieces * dpu + dp support for sc8180x * dp support for sm8350 * dpu + dsi support for qcm2290 * 10nm dsi phy tuning support * bridge support for dp encoder * gpu support for additional 7c3 SKUs * assorted cleanups and fixes The following changes since commit 26291c54e111ff6ba87a164d85d4a4e134b7315c: Linux 5.17-rc2 (2022-01-30 15:37:07 +0200) are available in the Git repository at: https://gitlab.freedesktop.org/drm/msm.git drm-msm-next-2022-03-01 for you to fetch changes up to afab9d91d872819f98a792c32c302d9e3261f1a1: drm/msm/adreno: Expose speedbin to userspace (2022-02-25 13:29:57 -0800) ---------------------------------------------------------------- Akhil P Oommen (4): drm/msm: Use generic name for gpu resources drm/msm/adreno: Generate name from chipid for 7c3 drm/msm/a6xx: Add support for 7c3 SKUs drm/msm/adreno: Expose speedbin to userspace AngeloGioacchino Del Regno (5): drm/msm/dpu1: Add DMA2, DMA3 clock control to enum drm/msm/dpu1: Add MSM8998 to hw catalog dt-bindings: display: msm: Add binding for msm8998 dpu drm/msm/dpu: Add a function to retrieve the current CTL status drm/msm/dpu: Fix timeout issues on command mode panels Bjorn Andersson (5): drm/msm/dp: Move debugfs files into subdirectory drm/msm/dp: Add sc8180x DP controllers drm/msm/dp: Add DisplayPort controller for SM8350 drm/msm/dpu: Add INTF_5 interrupts drm/msm/dpu: Only create debugfs for PRIMARY minor Changcheng Deng (1): drm/msm: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE Christophe JAILLET (1): drm/msm/dp: Simplify dp_debug_init() and dp_debug_get() Daniel Thompson (2): drm/msm/dsi: Remove spurious IRQF_ONESHOT flag drm/msm/hdmi: Remove spurious IRQF_ONESHOT flag Dmitry Baryshkov (27): drm/msm: drop register logging support drm/msm: drop dbgname argument from msm_ioremap*() drm/msm: move msm_readl/_writel to msm_drv.h drm/msm: reduce usage of round_pixclk callback drm/msm: move utility functions from msm_drv.c drm/msm/dsi: move DSI host powerup to modeset time drm/msm/dsi/phy: fix 7nm v4.0 settings for C-PHY mode drm/msm/dpu: drop unused lm_max_width from RM drm/msm/dpu: add DSPP blocks teardown drm/msm/dpu: get INTF blocks directly rather than through RM drm/msm/dpu: stop embedding dpu_hw_blk into dpu_hw_intf drm/msm/dpu: fix error handling in dpu_rm_init drm/msm/dpu: drop unused access macros drm/msm/dpu: fix dp audio condition drm/msm: move struct msm_display_info to dpu driver drm/msm/dpu: remove msm_dp cached in dpu_encoder_virt drm/msm/dpu: drop bus_scaling_client field drm/msm/dpu: encoder: drop unused mode_fixup callback drm/msm/dpu: switch dpu_encoder to use atomic_mode_set drm/msm/dpu: pull connector from dpu_encoder_phys to dpu_encoder_virt drm/msm/dpu: simplify clocks handling drm/msm/dp: fix panel bridge attachment drm/msm/dp: support attaching bridges to the DP encoder drm/msm/dp: support finding next bridge even for DP interfaces Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', 'msm-next-lumag-dp', 'msm-next-lumag-dsi', 'msm-next-lumag-hdmi' and 'msm-next-lumag-mdp5' into msm-next-lumag drm/msm/dpu: wire up MSM8998's DSPP blocks Merge branches 'msm-next-lumag-dpu' and 'msm-next-lumag-dsi' into msm-next-lumag Kuogee Hsieh (8): drm/msm/dp: do not initialize phy until plugin interrupt received drm/msm/dp: populate connector of struct dp_panel drm/msm/dp: add support of tps4 (training pattern 4) for HBR3 drm/msm/dp: stop link training after link training 2 failed drm/msm/dp: always add fail-safe mode into connector mode list drm/msm/dp: add connector type to enhance debug messages drm/msm/dp: enhance debug info related to dp phy drm/msm: populate intf_audio_select() base on hardware capability Loic Poulain (5): drm/msm/dsi: Allow to specify dsi config as pdata drm/msm/dsi: Add support for qcm2290 dsi controller dt-bindings: msm/dsi: Add qcm2290 dsi controller binding drm/msm: add support for QCM2290 MDSS dt-bindings: msm: disp: add yaml schemas for QCM2290 DPU bindings Marijn Suijten (1): drm/msm/dsi: Use "ref" fw clock instead of global name for VCO parent Rajeev Nandan (3): dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties drm/msm/dsi: Add dsi phy tuning configuration support drm/msm/dsi: Add 10nm dsi phy tuning configuration support Rob Clark (5): drm/msm/rd: Add chip-id drm/msm/dpu: Add SC8180x to hw catalog drm/msm/gpu: Add ctx to get_param() drm/msm/gpu: Track global faults per address-space drm/msm: Avoid dirtyfb stalls on video mode displays (v2) Vinod Koul (3): drm/msm/dpu: Remove set but unused variables drm/msm/dpu: Update the comment style drm/msm/dpu: Update function parameter documentation Yang Li (1): drm/msm/dpu: clean up some inconsistent indenting Yury Norov (1): drm: replace bitmap_weight with bitmap_empty where appropriate .../bindings/display/msm/dp-controller.yaml | 1 + .../bindings/display/msm/dpu-msm8998.yaml | 219 ++++++++ .../bindings/display/msm/dpu-qcm2290.yaml | 214 ++++++++ .../bindings/display/msm/dsi-controller-main.yaml | 5 +- .../bindings/display/msm/dsi-phy-10nm.yaml | 36 ++ drivers/gpu/drm/msm/Kconfig | 9 - drivers/gpu/drm/msm/Makefile | 3 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 20 +- drivers/gpu/drm/msm/adreno/adreno_device.c | 1 - drivers/gpu/drm/msm/adreno/adreno_gpu.c | 41 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 23 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 22 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 100 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 28 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 19 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 39 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 36 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 610 ++++++++++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 21 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 7 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 11 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 68 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 28 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 107 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 19 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 19 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 8 + drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 9 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 5 + drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 4 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 21 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 2 +- drivers/gpu/drm/msm/dp/dp_catalog.c | 12 +- drivers/gpu/drm/msm/dp/dp_catalog.h | 2 +- .../{disp/dpu1/dpu_io_util.c => dp/dp_clk_util.c} | 69 +-- .../{disp/dpu1/dpu_io_util.h => dp/dp_clk_util.h} | 8 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 102 ++-- drivers/gpu/drm/msm/dp/dp_ctrl.h | 8 +- drivers/gpu/drm/msm/dp/dp_debug.c | 28 +- drivers/gpu/drm/msm/dp/dp_display.c | 196 ++++--- drivers/gpu/drm/msm/dp/dp_display.h | 2 +- drivers/gpu/drm/msm/dp/dp_drm.c | 21 +- drivers/gpu/drm/msm/dp/dp_panel.c | 5 + drivers/gpu/drm/msm/dp/dp_parser.c | 38 +- drivers/gpu/drm/msm/dp/dp_parser.h | 4 +- drivers/gpu/drm/msm/dsi/dsi.c | 4 +- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 23 + drivers/gpu/drm/msm/dsi/dsi_cfg.h | 3 + drivers/gpu/drm/msm/dsi/dsi_host.c | 8 +- drivers/gpu/drm/msm/dsi/dsi_manager.c | 65 ++- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 14 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 4 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 122 ++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 4 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 4 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 26 +- drivers/gpu/drm/msm/hdmi/hdmi.c | 7 +- drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 11 +- drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 2 +- drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 7 +- drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c | 2 +- drivers/gpu/drm/msm/msm_atomic.c | 15 - drivers/gpu/drm/msm/msm_debugfs.c | 6 +- drivers/gpu/drm/msm/msm_drv.c | 160 +----- drivers/gpu/drm/msm/msm_drv.h | 46 +- drivers/gpu/drm/msm/msm_fb.c | 41 +- drivers/gpu/drm/msm/msm_gem.h | 3 + drivers/gpu/drm/msm/msm_gpu.c | 14 +- drivers/gpu/drm/msm/msm_gpu.h | 8 +- drivers/gpu/drm/msm/msm_io_utils.c | 126 +++++ drivers/gpu/drm/msm/msm_rd.c | 8 +- 82 files changed, 2045 insertions(+), 990 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml rename drivers/gpu/drm/msm/{disp/dpu1/dpu_io_util.c => dp/dp_clk_util.c} (61%) rename drivers/gpu/drm/msm/{disp/dpu1/dpu_io_util.h => dp/dp_clk_util.h} (85%) create mode 100644 drivers/gpu/drm/msm/msm_io_utils.c

1 0

Re: [PATCH v7, 04/15] media: mtk-vcodec: Read max resolution from dec_capability
by Przemysław Drozdowski 01 Mar '22

01 Mar '22

1 0

[PATCH v3] drm/i915/guc: Do not complain about stale reset notifications
by John.C.Harrison＠Intel.com 01 Mar '22

01 Mar '22

From: John Harrison <John.C.Harrison(a)Intel.com> It is possible for reset notifications to arrive for a context that is in the process of being banned. So don't flag these as an error, just report it as informational (because it is still useful to know that resets are happening even if they are being ignored). v2: Better wording for the message (review feedback from Tvrtko). v3: Fix rebase issue (review feedback from Daniele). Signed-off-by: John Harrison <John.C.Harrison(a)Intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index b3a429a92c0d..d39d74d39794 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -4022,10 +4022,9 @@ static void guc_handle_context_reset(struct intel_guc *guc, capture_error_state(guc, ce); guc_context_replay(ce); } else { - drm_err(&guc_to_gt(guc)->i915->drm, - "Invalid GuC engine reset notificaion for 0x%04X on %s: banned = %d, blocked = %d", - ce->guc_id.id, ce->engine->name, intel_context_is_banned(ce), - context_blocked(ce)); + drm_info(&guc_to_gt(guc)->i915->drm, + "Ignoring context reset notification of banned context 0x%04X on %s", + ce->guc_id.id, ce->engine->name); } } -- 2.25.1

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[PATCH v6] drm/i915/gt: Clear compress metadata for Xe_HP platforms
by Ramalingam C 01 Mar '22

01 Mar '22

From: Ayaz A Siddiqui <ayaz.siddiqui(a)intel.com> Xe-HP and latest devices support Flat CCS which reserved a portion of the device memory to store compression metadata, during the clearing of device memory buffer object we also need to clear the associated CCS buffer. Flat CCS memory can not be directly accessed by S/W. Address of CCS buffer associated main BO is automatically calculated by device itself. KMD/UMD can only access this buffer indirectly using XY_CTRL_SURF_COPY_BLT cmd via the address of device memory buffer. v2: Fixed issues with platform naming [Lucas] v3: Rebased [Ram] Used the round_up funcs [Bob] v4: Fixed ccs blk calculation [Ram] Added Kdoc on flat-ccs. v5: GENMASK is used [Matt] mocs fix [Matt] Comments Fix [Matt] Flush address programming [Ram] v6: FLUSH_DW is fixed Few coding style fix Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui(a)intel.com> Signed-off-by: Ramalingam C <ramalingam.c(a)intel.com> --- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 ++ drivers/gpu/drm/i915/gt/intel_migrate.c | 143 ++++++++++++++++++- 2 files changed, 154 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index f8253012d166..237c1baccc64 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -203,6 +203,21 @@ #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) +#define XY_CTRL_SURF_INSTR_SIZE 5 +#define MI_FLUSH_DW_SIZE 3 +#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3) +#define SRC_ACCESS_TYPE_SHIFT 21 +#define DST_ACCESS_TYPE_SHIFT 20 +#define CCS_SIZE_MASK GENMASK(17, 8) +#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 25) +#define NUM_CCS_BYTES_PER_BLOCK 256 +#define NUM_BYTES_PER_CCS_BYTE 256 +#define NUM_CCS_BLKS_PER_XFER 1024 +#define INDIRECT_ACCESS 0 +#define DIRECT_ACCESS 1 +#define MI_FLUSH_LLC BIT(9) +#define MI_FLUSH_CCS BIT(16) + #define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2)) #define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22) #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22) diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c index 20444d6ceb3c..330fcdc3e0cf 100644 --- a/drivers/gpu/drm/i915/gt/intel_migrate.c +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c @@ -16,6 +16,8 @@ struct insert_pte_data { }; #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */ +#define GET_CCS_BYTES(i915, size) (HAS_FLAT_CCS(i915) ? \ + DIV_ROUND_UP(size, NUM_BYTES_PER_CCS_BYTE) : 0) static bool engine_supports_migration(struct intel_engine_cs *engine) { @@ -467,6 +469,110 @@ static bool wa_1209644611_applies(int ver, u32 size) return height % 4 == 3 && height <= 8; } +/** + * DOC: Flat-CCS - Memory compression for Local memory + * + * On Xe-HP and later devices, we use dedicated compression control state (CCS) + * stored in local memory for each surface, to support the 3D and media + * compression formats. + * + * The memory required for the CCS of the entire local memory is 1/256 of the + * local memory size. So before the kernel boot, the required memory is reserved + * for the CCS data and a secure register will be programmed with the CCS base + * address. + * + * Flat CCS data needs to be cleared when a lmem object is allocated. + * And CCS data can be copied in and out of CCS region through + * XY_CTRL_SURF_COPY_BLT. CPU can't access the CCS data directly. + * + * When we exhaust the lmem, if the object's placements support smem, then we can + * directly decompress the compressed lmem object into smem and start using it + * from smem itself. + * + * But when we need to swapout the compressed lmem object into a smem region + * though objects' placement doesn't support smem, then we copy the lmem content + * as it is into smem region along with ccs data (using XY_CTRL_SURF_COPY_BLT). + * When the object is referred, lmem content will be swaped in along with + * restoration of the CCS data (using XY_CTRL_SURF_COPY_BLT) at corresponding + * location. + */ + +static inline u32 *i915_flush_dw(u32 *cmd, u32 flags) +{ + *cmd++ = MI_FLUSH_DW | flags; + *cmd++ = 0; + *cmd++ = 0; + + return cmd; +} + +static u32 calc_ctrl_surf_instr_size(struct drm_i915_private *i915, int size) +{ + u32 num_cmds, num_blks, total_size; + + if (!GET_CCS_BYTES(i915, size)) + return 0; + + /* + * XY_CTRL_SURF_COPY_BLT transfers CCS in 256 byte + * blocks. one XY_CTRL_SURF_COPY_BLT command can + * transfer upto 1024 blocks. + */ + num_blks = DIV_ROUND_UP(GET_CCS_BYTES(i915, size), + NUM_CCS_BYTES_PER_BLOCK); + num_cmds = DIV_ROUND_UP(num_blks, NUM_CCS_BLKS_PER_XFER); + total_size = XY_CTRL_SURF_INSTR_SIZE * num_cmds; + + /* + * Adding a flush before and after XY_CTRL_SURF_COPY_BLT + */ + total_size += 2 * MI_FLUSH_DW_SIZE; + + return total_size; +} + +static u32 *_i915_ctrl_surf_copy_blt(u32 *cmd, u64 src_addr, u64 dst_addr, + u8 src_mem_access, u8 dst_mem_access, + int src_mocs, int dst_mocs, + u32 ccs_blocks) +{ + /* + * The XY_CTRL_SURF_COPY_BLT instruction is used to copy the CCS + * data in and out of the CCS region. + * + * We can copy at most 1024 blocks of 256 bytes using one + * XY_CTRL_SURF_COPY_BLT instruction. + * + * In case we need to copy more than 1024 blocks, we need to add + * another instruction to the same batch buffer. + * + * 1024 blocks of 256 bytes of CCS represent a total 256KB of CCS. + * + * 256 KB of CCS represents 256 * 256 KB = 64 MB of LMEM. + */ + do { + int blks_per_copy; + + blks_per_copy = ccs_blocks >= NUM_CCS_BLKS_PER_XFER ? + NUM_CCS_BLKS_PER_XFER : ccs_blocks; + *cmd++ = XY_CTRL_SURF_COPY_BLT | + src_mem_access << SRC_ACCESS_TYPE_SHIFT | + dst_mem_access << DST_ACCESS_TYPE_SHIFT | + FIELD_PREP(CCS_SIZE_MASK, blks_per_copy - 1); + *cmd++ = lower_32_bits(src_addr); + *cmd++ = (upper_32_bits(src_addr) & 0xFFFF) | + FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, src_mocs); + *cmd++ = lower_32_bits(dst_addr); + *cmd++ = (upper_32_bits(dst_addr) & 0xFFFF) | + FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, dst_mocs); + src_addr += SZ_64M; + dst_addr += SZ_64M; + ccs_blocks -= blks_per_copy; + } while (ccs_blocks > 0); + + return cmd; +} + static int emit_copy(struct i915_request *rq, u32 dst_offset, u32 src_offset, int size) { @@ -614,16 +720,24 @@ intel_context_migrate_copy(struct intel_context *ce, return err; } -static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value) +static int emit_clear(struct i915_request *rq, u64 offset, int size, + u32 value, bool is_lmem) { - const int ver = GRAPHICS_VER(rq->engine->i915); + struct drm_i915_private *i915 = rq->engine->i915; + const int ver = GRAPHICS_VER(i915); + u32 num_ccs_blks, ccs_ring_size; + int mocs = rq->engine->gt->mocs.uc_index << 1; u32 *cs; GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX); offset += (u64)rq->engine->instance << 32; - cs = intel_ring_begin(rq, ver >= 8 ? 8 : 6); + /* Clear CCS only when value is 0 */ + ccs_ring_size = (is_lmem && !value) ? + calc_ctrl_surf_instr_size(i915, size) : 0; + + cs = intel_ring_begin(rq, round_up(ver >= 8 ? 8 + ccs_ring_size : 6, 2)); if (IS_ERR(cs)) return PTR_ERR(cs); @@ -646,6 +760,27 @@ static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value) *cs++ = value; } + if (is_lmem && HAS_FLAT_CCS(i915) && !value) { + num_ccs_blks = DIV_ROUND_UP(GET_CCS_BYTES(i915, size), + NUM_CCS_BYTES_PER_BLOCK); + + /* + * Flat CCS surface can only be accessed via + * XY_CTRL_SURF_COPY_BLT CMD and using indirect + * mapping of associated LMEM. + * We can clear ccs surface by writing all 0s, + * so we will flush the previously cleared buffer + * and use it as a source. + */ + cs = i915_flush_dw(cs, MI_FLUSH_LLC | MI_FLUSH_CCS); + cs = _i915_ctrl_surf_copy_blt(cs, offset, offset, + DIRECT_ACCESS, INDIRECT_ACCESS, + mocs, mocs, num_ccs_blks); + cs = i915_flush_dw(cs, MI_FLUSH_LLC | MI_FLUSH_CCS); + + if (ccs_ring_size & 1) + *cs++ = MI_NOOP; + } intel_ring_advance(rq, cs); return 0; } @@ -711,7 +846,7 @@ intel_context_migrate_clear(struct intel_context *ce, if (err) goto out_rq; - err = emit_clear(rq, offset, len, value); + err = emit_clear(rq, offset, len, value, is_lmem); /* Arbitration is re-enabled between requests. */ out_rq: -- 2.20.1

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dri-devel March 2022