dri-devel May 2022

dri-devel@lists.freedesktop.org

344 participants
736 discussions

[PATCH v12 0/3] eDP/DP Phy vdda realted function
by Kuogee Hsieh 25 May '22

25 May '22

1) add regulator_set_load() to eDP phy 2) add regulator_set_load() to DP phy 3) remove vdda related function out of eDP/DP controller Kuogee Hsieh (3): phy: qcom-edp: add regulator_set_load to edp phy phy: qcom-qmp: add regulator_set_load to dp phy drm/msm/dp: delete vdda regulator related functions from eDP/DP controller drivers/gpu/drm/msm/dp/dp_parser.c | 14 ------ drivers/gpu/drm/msm/dp/dp_parser.h | 8 ---- drivers/gpu/drm/msm/dp/dp_power.c | 95 +------------------------------------ drivers/phy/qualcomm/phy-qcom-edp.c | 12 +++++ drivers/phy/qualcomm/phy-qcom-qmp.c | 41 ++++++++++++---- 5 files changed, 46 insertions(+), 124 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

2 4

[PATCH] drm: Create support for Write-Only property blob
by Mark Yacoub 25 May '22

25 May '22

[Why] User space might need to inject data into the kernel without allowing it to be read again by any user space. An example of where this is particularly useful is secret keys fetched by user space and injected into the kernel to enable content protection. [How] Create a DRM_MODE_CREATE_BLOB_WRITE_ONLY flag used by user space to create a blob and mark the blob as write only. On reading back the blob, data will be not be copied if it's a write only blob Signed-off-by: Mark Yacoub <markyacoub(a)chromium.org> --- drivers/gpu/drm/drm_property.c | 3 ++- include/drm/drm_property.h | 2 ++ include/uapi/drm/drm_mode.h | 6 ++++++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c index dfec479830e4..afedf7109d00 100644 --- a/drivers/gpu/drm/drm_property.c +++ b/drivers/gpu/drm/drm_property.c @@ -765,7 +765,7 @@ int drm_mode_getblob_ioctl(struct drm_device *dev, if (!blob) return -ENOENT; - if (out_resp->length == blob->length) { + if (out_resp->length == blob->length && !blob->is_write_only) { if (copy_to_user(u64_to_user_ptr(out_resp->data), blob->data, blob->length)) { @@ -800,6 +800,7 @@ int drm_mode_createblob_ioctl(struct drm_device *dev, ret = -EFAULT; goto out_blob; } + blob->is_write_only = out_resp->flags & DRM_MODE_CREATE_BLOB_WRITE_ONLY; /* Dropping the lock between create_blob and our access here is safe * as only the same file_priv can remove the blob; at this point, it is diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h index 65bc9710a470..700782f021b9 100644 --- a/include/drm/drm_property.h +++ b/include/drm/drm_property.h @@ -205,6 +205,7 @@ struct drm_property { * &drm_mode_config.property_blob_list. * @head_file: entry on the per-file blob list in &drm_file.blobs list. * @length: size of the blob in bytes, invariant over the lifetime of the object + * @is_write_only: user space can't read the blob data. * @data: actual data, embedded at the end of this structure * * Blobs are used to store bigger values than what fits directly into the 64 @@ -219,6 +220,7 @@ struct drm_property_blob { struct list_head head_global; struct list_head head_file; size_t length; + bool is_write_only; void *data; }; diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 0a0d56a6158e..de192d3813e9 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -1107,6 +1107,9 @@ struct drm_format_modifier { __u64 modifier; }; +#define DRM_MODE_CREATE_BLOB_WRITE_ONLY \ + (1 << 0) /* data of the blob can't be read by user space */ + /** * struct drm_mode_create_blob - Create New blob property * @@ -1120,6 +1123,9 @@ struct drm_mode_create_blob { __u32 length; /** @blob_id: Return: new property ID. */ __u32 blob_id; + /** Flags for special handling. */ + __u32 flags; + __u32 pad; }; /** -- 2.36.0.512.ge40c2bad7a-goog

2 4

[PATCH 0/2] x86/pat: fix querying available caching modes
by Juergen Gross 25 May '22

25 May '22

Fix some issues with querying caching modes being available for memory mappings. This is a replacement for the patch of Jan sent recently: https://lists.xen.org/archives/html/xen-devel/2022-04/msg02392.html Juergen Gross (2): x86/pat: fix x86_has_pat_wp() x86/pat: add functions to query specific cache mode availability arch/x86/include/asm/memtype.h | 2 ++ arch/x86/include/asm/pci.h | 2 +- arch/x86/mm/init.c | 24 ++++++++++++++++++++++-- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 8 ++++---- 4 files changed, 29 insertions(+), 7 deletions(-) -- 2.35.3

4 26

[PATCH] drm/amdgpu: make program_imu_rlc_ram static
by Jiapeng Chong 25 May '22

25 May '22

This symbol is not used outside of imu_v11_0.c, so marks it static. Fixes the following w1 warning: drivers/gpu/drm/amd/amdgpu/imu_v11_0.c:302:6: warning: no previous prototype for ‘program_imu_rlc_ram’ [-Wmissing-prototypes]. Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> --- drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c index 5d2dfeff8fe5..d63d3f2b8a16 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c @@ -299,7 +299,7 @@ static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11_0_2[] = IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0) }; -void program_imu_rlc_ram(struct amdgpu_device *adev, +static void program_imu_rlc_ram(struct amdgpu_device *adev, const struct imu_rlc_ram_golden *regs, const u32 array_size) { -- 2.20.1.7.g153144c

2 1

[PATCH] drm/vkms: Update vkms_composer_worker documentation
by André Almeida 25 May '22

25 May '22

Since commit ba420afab565 ("drm/vkms: Bugfix racing hrtimer vblank handle") the work is scheduled at vkms_vblank_simulate() and since commit 5ef8100a3919 ("drm/vkms: flush crc workers earlier in commit flow") the work is flushed at vkms_atomic_commit_tail(). Update function commment to reflect that. Signed-off-by: André Almeida <andrealmeid(a)igalia.com> --- drivers/gpu/drm/vkms/vkms_composer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vkms/vkms_composer.c b/drivers/gpu/drm/vkms/vkms_composer.c index c6a1036bf2ea..914c0ac7dc8b 100644 --- a/drivers/gpu/drm/vkms/vkms_composer.c +++ b/drivers/gpu/drm/vkms/vkms_composer.c @@ -213,7 +213,7 @@ static int compose_active_planes(void **vaddr_out, * * Work handler for composing and computing CRCs. work_struct scheduled in * an ordered workqueue that's periodically scheduled to run by - * _vblank_handle() and flushed at vkms_atomic_crtc_destroy_state(). + * vkms_vblank_simulate() and flushed at vkms_atomic_commit_tail(). */ void vkms_composer_worker(struct work_struct *work) { -- 2.36.0

2 1

[PATCH] drm: use ENOMEM for drmm_kzalloc allocation failures
by Niels Dossche 25 May '22

25 May '22

Other callers of drmm_kzalloc already return -ENOMEM on allocation failure. Change EINVAL to ENOMEM for consistency. Signed-off-by: Niels Dossche <dossche.niels(a)gmail.com> --- Note: I found this issue using my experimental static analyser on Linux 5.17.9. I compile tested the patch on x86_64. drivers/gpu/drm/drm_encoder.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_encoder.c b/drivers/gpu/drm/drm_encoder.c index 72e982323a5e..a940024c8087 100644 --- a/drivers/gpu/drm/drm_encoder.c +++ b/drivers/gpu/drm/drm_encoder.c @@ -226,7 +226,7 @@ void *__drmm_encoder_alloc(struct drm_device *dev, size_t size, size_t offset, container = drmm_kzalloc(dev, size, GFP_KERNEL); if (!container) - return ERR_PTR(-EINVAL); + return ERR_PTR(-ENOMEM); encoder = container + offset; -- 2.36.0

2 1

[PATCH] dma-buf: cleanup dma_fence_chain_walk
by Christian König 25 May '22

25 May '22

Use unrcu_pointer() instead of the manual cast. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/dma-buf/dma-fence-chain.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c index 06f8ef97c6e8..a0d920576ba6 100644 --- a/drivers/dma-buf/dma-fence-chain.c +++ b/drivers/dma-buf/dma-fence-chain.c @@ -62,8 +62,8 @@ struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence) replacement = NULL; } - tmp = cmpxchg((struct dma_fence __force **)&chain->prev, - prev, replacement); + tmp = unrcu_pointer(cmpxchg(&chain->prev, RCU_INITIALIZER(prev), + RCU_INITIALIZER(replacement))); if (tmp == prev) dma_fence_put(tmp); else -- 2.25.1

2 1

[PATCH] drm/sun4i: Fix blend registers corruption for DE2.0/DE3.0
by Roman Stratiienko 25 May '22

25 May '22

Corruption happens when plane zpos is updated Example scenario: Initial frame blender state: PLANE_ZPOS = {0, 1, 2, 3} BLD_ROUTE = {0, 1, 2, 0} BLD_EN = {1, 1, 1, 0} New frame commit (Only ZPOS has been changed): PLANE_ZPOS = {0->2, 1->0, 2->1, 3} Expected results after plane state update: Z0 Z1 Z2 Z3 BLD_ROUTE = {1, 2, 0, 0} BLD_EN = {1, 1, 1, 0} What is currently happening: 1. sun8i_vi_layer_enable(enabled=true, zpos=2, old_zpos=0): BLD_ROUTE = {1->0, 1, 2->0, 0} BLD_EN = {1->0, 1, 1->1, 0} 2. sun8i_ui_layer_enable(enabled=true, zpos=0, old_zpos=1): BLD_ROUTE = {0->1, 1->0, 0, 0} BLD_EN = {0->1, 1->0, 1, 0} 3. sun8i_ui_layer_enable(enabled=true, zpos=1, old_zpos=2): BLD_ROUTE = {1, 0->2, 0->0, 0} BLD_EN = {1, 0->2, 1->0, 0} After updating of all the planes we are ending up with BLD_EN[2]=0, which makes this channel disabled. To fix this issue, clear BLEND registers before updating the planes and do not clear the old state while processing every plane. Signed-off-by: Roman Stratiienko <roman.o.stratiienko(a)globallogic.com> --- drivers/gpu/drm/sun4i/sun8i_mixer.c | 16 +++++++++++++++ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 28 ++++---------------------- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 28 ++++---------------------- 3 files changed, 24 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index f5e8aeaa3cdf..004377a000fc 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -248,6 +248,21 @@ int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format) return -EINVAL; } +static void sun8i_atomic_begin(struct sunxi_engine *engine, + struct drm_crtc_state *old_state) +{ + struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); + u32 bld_base = sun8i_blender_base(mixer); + + regmap_write(engine->regs, + SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), + 0); + + regmap_write(engine->regs, + SUN8I_MIXER_BLEND_ROUTE(bld_base), + 0); +} + static void sun8i_mixer_commit(struct sunxi_engine *engine) { DRM_DEBUG_DRIVER("Committing changes\n"); @@ -299,6 +314,7 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm, } static const struct sunxi_engine_ops sun8i_engine_ops = { + .atomic_begin = sun8i_atomic_begin, .commit = sun8i_mixer_commit, .layers_init = sun8i_layers_init, }; diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index 7845c2a53a7f..b294a882626a 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -24,8 +24,7 @@ #include "sun8i_ui_scaler.h" static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, - int overlay, bool enable, unsigned int zpos, - unsigned int old_zpos) + int overlay, bool enable, unsigned int zpos) { u32 val, bld_base, ch_base; @@ -44,18 +43,6 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val); - if (!enable || zpos != old_zpos) { - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), - SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos), - 0); - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_ROUTE(bld_base), - SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos), - 0); - } - if (enable) { val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); @@ -291,31 +278,24 @@ static int sun8i_ui_layer_atomic_check(struct drm_plane *plane, static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane, struct drm_atomic_state *state) { - struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, - plane); struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; - sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0, - old_zpos); + sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0); } static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state) { - struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, - plane); struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); unsigned int zpos = new_state->normalized_zpos; - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; if (!new_state->visible) { sun8i_ui_layer_enable(mixer, layer->channel, - layer->overlay, false, 0, old_zpos); + layer->overlay, false, 0); return; } @@ -328,7 +308,7 @@ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, sun8i_ui_layer_update_buffer(mixer, layer->channel, layer->overlay, plane); sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, - true, zpos, old_zpos); + true, zpos); } static const struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = { diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index bb7c43036dfa..4653244b2fd8 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -18,8 +18,7 @@ #include "sun8i_vi_scaler.h" static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel, - int overlay, bool enable, unsigned int zpos, - unsigned int old_zpos) + int overlay, bool enable, unsigned int zpos) { u32 val, bld_base, ch_base; @@ -38,18 +37,6 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel, SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val); - if (!enable || zpos != old_zpos) { - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), - SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos), - 0); - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_ROUTE(bld_base), - SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos), - 0); - } - if (enable) { val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); @@ -395,31 +382,24 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane, static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane, struct drm_atomic_state *state) { - struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, - plane); struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; - sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0, - old_zpos); + sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0); } static void sun8i_vi_layer_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state) { - struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, - plane); struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); unsigned int zpos = new_state->normalized_zpos; - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; if (!new_state->visible) { sun8i_vi_layer_enable(mixer, layer->channel, - layer->overlay, false, 0, old_zpos); + layer->overlay, false, 0); return; } @@ -432,7 +412,7 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane, sun8i_vi_layer_update_buffer(mixer, layer->channel, layer->overlay, plane); sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, - true, zpos, old_zpos); + true, zpos); } static const struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = { -- 2.30.2

2 10

Tackling the indefinite/user DMA fence problem
by Christian König 25 May '22

25 May '22

Hello everyone, it's a well known problem that the DMA-buf subsystem mixed synchronization and memory management requirements into the same dma_fence and dma_resv objects. Because of this dma_fence objects need to guarantee that they complete within a finite amount of time or otherwise the system can easily deadlock. One of the few good things about this problem is that it is really good understood by now. Daniel and others came up with some documentation: https://dri.freedesktop.org/docs/drm/driver-api/dma-buf.html?highlight=dma_… And Jason did an excellent presentation about that problem on last years LPC: https://lpc.events/event/11/contributions/1115/ Based on that we had been able to reject new implementations of infinite/user DMA fences and mitigate the effect of the few existing ones. The still remaining down side is that we don't have a way of using user fences as dependency in both the explicit (sync_file, drm_syncobj) as well as the implicit (dma_resv) synchronization objects, resulting in numerous problems and limitations for things like HMM, user queues etc.... This patch set here now tries to tackle this problem by untangling the synchronization from the memory management. What it does *not* try to do is to fix the existing kernel fences, because I think we now can all agree on that this isn't really possible. To archive this goal what I do in this patch set is to add some parallel infrastructure to cleanly separate normal kernel dma_fence objects from indefinite/user fences: 1. It introduce a DMA_FENCE_FLAG_USER define (after renaming some existing driver defines). To note that a certain dma_fence is an user fence and *must* be ignore by memory management and never used as dependency for normal none user dma_fence objects. 2. The dma_fence_array and dma_fence_chain containers are modified so that they are marked as user fences whenever any of their contained fences are an user fence. 3. The dma_resv object gets a new DMA_RESV_USAGE_USER flag which must be used with indefinite/user fences and separates those into it's own synchronization domain. 4. The existing dma_buf_poll_add_cb() function is modified so that indefinite/user fences are included in the polling. 5. The sync_file synchronization object is modified so that we essentially have two fence streams instead of just one. 6. The drm_syncobj is modified in a similar way. User fences are just ignored unless the driver explicitly states support to wait for them. 7. The DRM subsystem gains a new DRIVER_USER_FENCE flag which drivers can use to indicate the need for user fences. If user fences are used the atomic mode setting starts to support user fences as IN/OUT fences. 8. Lockdep is used at various critical locations to ensure that nobody ever tries to mix user fences with non user fences. The general approach is to just ignore user fences unless a driver stated explicitely support for them. On top of all of this I've hacked amdgpu so that we add the resulting CS fence only as kernel dependency to the dma_resv object and an additional wrapped up with a dma_fence_array and a stub user fence. The result is that the newly added atomic modeset functions now correctly wait for the user fence to complete before doing the flip. And dependent CS don't pipeline any more, but rather block on the CPU before submitting work. After tons of debugging and testing everything now seems to not go up in flames immediately and even lockdep is happy with the annotations. I'm perfectly aware that this is probably by far the most controversial patch set I've ever created and I really wish we wouldn't need it. But we certainly have the requirement for this and I don't see much other chance to get that working in an UAPI compatible way. Thoughts/comments? Regards, Christian.

7 28

[PATCH v21 0/5] Add Mediatek Soc DRM (vdosys0) support for mt8195
by Jason-JH.Lin 25 May '22

25 May '22

Change in v21: - rebase on next-20220525 Change in v20: - split binding patch to another series 'MediaTek MT8195 display binding': https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669 - fix io_start type from u32 to resource_size_t - fix some commit message for DITHER enum Change in v19: - fix checking condition for the return vaule of platform resource - drm/mediatek fix build waning for [-Wunused-const-variable] Change in v18: - change get driver data by io_start and wrap mmsys driver data into mmsys match data structure to support identifying multi mmsys driver data with the same compatible name - change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0 Change in v17: - change compatible name from 2 vdosys to 1 mmsys - add get driver data by clk name function to get corresponding driver data for mt8195 vdosys0 - add all routing table setting for mt8195 vdosys0 - remove useless mutex define Change in v16: - rebase on linu-next tag: 'next-20220303' - rebase on series: 'Fix MediaTek display dt-bindings issues' Change in v15: - remove mt8195-mmsys.h comment for mux settings - define the mask macro to replace using value as mask to fix zero mask problem - add EOF setting comment for MUTEX sof register Change in v14: - rebase on mediatek-drm-next-5.17 - rebase on "Add mmsys and mutex support for MDP" series - rebase on "media: mediatek: support mdp3 on mt8183 platform" series Change in v13: - remove dts patch - rebase on kernel-5.16-rc1 - rebase on mediatek-drm-next Change in v12: - add clock-names property to merge yaml - using BIT(nr) macro to define the settings of mmsys routing table - fix clk_get and clk_prepare_enable error handling issue Change in v11: - rebase on kernel-5.15-rc1 - change mbox label to gce0 for dts node of vdosys0 - change ovl compatibale to mt8192 to set smi_id_en=true in driver data - move common module from display folder to common folder, such as AAL, COCLOR, CCORR and MUTEX Change in v10: - rebase on "drm/mediatek: add support for mediatek SOC MT8192" series - rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series - fix some typo and "mediatek" start with capital in every dt-bindings - move mutex yaml from dfisplay folder to soc folder - separate merge additional propoerties to an individual dt-bindings patch Change in v9: - separate power and gce properties of mmsys into another dt-binding patch - rebase on "Separate aal module" series - keep mtk_ddp_clk_enable/disable in the same place - change mtk_dsc_start config register to mtk_drm_ddp_write_mask - remove the 0 setting of merge fifo config function - add CCORR driver data for mt8195 Change in v8: - add DP_INTF0 mux into mmsys routing table - add DP_INTF0 mutex mod and enum into add/remove comp function - remove bypass DSC enum in mtk_ddp_comp_init Change in v7: - add dt=binding of mmsys and disp path into this series - separate th modidfication of alphabetic order, remove unused define and rename the define of register offset to individual patch - add comment for MERGE ultra and preultra setting Change in v6: - adjust alphabetic order for mediatek-drm - move the patch that add mt8195 support for mediatek-drm as the lastest patch - add MERGE define for const varriable Change in v5: - add power-domain property into vdosys0 and vdosys1 dts node. - add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h Change in v4: - extract dt-binding patches to another patch series - squash DSC module into mtk_drm_ddp_comp.c - add coment and simplify MERGE config function Change in v3: - change mmsys and display dt-bindings document from txt to yaml - add MERGE additional description in display dt-bindings document - fix mboxes-cells number of vdosys0 node in dts - drop mutex eof convert define - remove pm_runtime apis in DSC and MERGE - change DSC and MERGE enum to alphabetic order Change in v2: - add DSC yaml file - add mt8195 drm driver porting parts in to one patch - remove useless define, variable, structure member and function - simplify DSC and MERGE file and switch threre order jason-jh.lin (5): drm/mediatek: add DSC support for mediatek-drm drm/mediatek: add MERGE support for mediatek-drm drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0 soc: mediatek: remove DDP_DOMPONENT_DITHER from enum drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 + drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 65 +++++- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 160 +++++++++++-- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 + include/linux/soc/mediatek/mtk-mmsys.h | 3 +- 9 files changed, 482 insertions(+), 16 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c -- 2.18.0

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dri-devel May 2022