dri-devel May 2022

dri-devel@lists.freedesktop.org

344 participants
736 discussions

[PATCH 0/7] Revert some refactoring patches
by Tvrtko Ursulin 19 May '22

19 May '22

From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> As agreed on the mailing list and between the maintainers more consensus is needed on the topic. Tvrtko Ursulin (7): Revert "drm/i915: Drop has_psr from device info" Revert "drm/i915: Drop has_dp_mst from device info" Revert "drm/i915: Drop has_ddi from device info" Revert "drm/i915: Drop has_logical_ring_elsq from device info" Revert "drm/i915: Drop has_reset_engine from device info" Revert "drm/i915: Drop has_rc6 from device info" Revert "drm/i915: Drop has_gt_uc from device info" drivers/gpu/drm/i915/gt/intel_reset.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 16 ++++++------- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_pci.c | 29 +++++++++++++++++++++++- drivers/gpu/drm/i915/intel_device_info.h | 7 ++++++ 5 files changed, 44 insertions(+), 12 deletions(-) -- 2.32.0

2 8

[PATCH] video: fbdev: Fix refcount leak in clcdfb_of_vram_setup
by Miaoqian Lin 19 May '22

19 May '22

of_parse_phandle() returns a node pointer with refcount incremented, we should use of_node_put() on it when not need anymore. Add missing of_node_put() to avoid refcount leak. Fixes: d10715be03bd ("video: ARM CLCD: Add DT support") Signed-off-by: Miaoqian Lin <linmq006(a)gmail.com> --- drivers/video/fbdev/amba-clcd.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/video/fbdev/amba-clcd.c b/drivers/video/fbdev/amba-clcd.c index 9ec969e136bf..8080116aea84 100644 --- a/drivers/video/fbdev/amba-clcd.c +++ b/drivers/video/fbdev/amba-clcd.c @@ -758,12 +758,15 @@ static int clcdfb_of_vram_setup(struct clcd_fb *fb) return -ENODEV; fb->fb.screen_base = of_iomap(memory, 0); - if (!fb->fb.screen_base) + if (!fb->fb.screen_base) { + of_node_put(memory); return -ENOMEM; + } fb->fb.fix.smem_start = of_translate_address(memory, of_get_address(memory, 0, &size, NULL)); fb->fb.fix.smem_len = size; + of_node_put(memory); return 0; } -- 2.25.1

2 1

[PATCH] video: hyperv_fb: Allow resolutions with size > 64 MB for Gen1
by Saurabh Sengar 19 May '22

19 May '22

This patch fixes a bug where GEN1 VMs doesn't allow resolutions greater than 64 MB size (eg 7680x4320). Unnecessary PCI check limits Gen1 VRAM to legacy PCI BAR size only (ie 64MB). Thus any, resolution requesting greater then 64MB (eg 7680x4320) would fail. MMIO region assigning this memory shouldn't be limited by PCI bar size. Signed-off-by: Saurabh Sengar <ssengar(a)linux.microsoft.com> --- drivers/video/fbdev/hyperv_fb.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) diff --git a/drivers/video/fbdev/hyperv_fb.c b/drivers/video/fbdev/hyperv_fb.c index c8e0ea2..58c304a 100644 --- a/drivers/video/fbdev/hyperv_fb.c +++ b/drivers/video/fbdev/hyperv_fb.c @@ -1009,7 +1009,6 @@ static int hvfb_getmem(struct hv_device *hdev, struct fb_info *info) struct pci_dev *pdev = NULL; void __iomem *fb_virt; int gen2vm = efi_enabled(EFI_BOOT); - resource_size_t pot_start, pot_end; phys_addr_t paddr; int ret; @@ -1060,23 +1059,7 @@ static int hvfb_getmem(struct hv_device *hdev, struct fb_info *info) dio_fb_size = screen_width * screen_height * screen_depth / 8; - if (gen2vm) { - pot_start = 0; - pot_end = -1; - } else { - if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || - pci_resource_len(pdev, 0) < screen_fb_size) { - pr_err("Resource not available or (0x%lx < 0x%lx)\n", - (unsigned long) pci_resource_len(pdev, 0), - (unsigned long) screen_fb_size); - goto err1; - } - - pot_end = pci_resource_end(pdev, 0); - pot_start = pot_end - screen_fb_size + 1; - } - - ret = vmbus_allocate_mmio(&par->mem, hdev, pot_start, pot_end, + ret = vmbus_allocate_mmio(&par->mem, hdev, 0, -1, screen_fb_size, 0x100000, true); if (ret != 0) { pr_err("Unable to allocate framebuffer memory\n"); -- 1.8.3.1

5 6

[CI 1/3] drm/i915: Introduce has_media_ratio_mode
by Tvrtko Ursulin 19 May '22

19 May '22

From: Ashutosh Dixit <ashutosh.dixit(a)intel.com> Media ratio mode (the ability for media IP to work at a different frequency from the GT) is available for a subset of dGfx platforms supporting GuC/SLPC. Introduce 'has_media_ratio_mode' flag in intel_device_info to identify these platforms and set it for XEHPSDV and DG2/ATS-M. Signed-off-by: Ashutosh Dixit <ashutosh.dixit(a)intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi(a)intel.com> Reviewed-by: Andi Shyti <andi.shyti(a)linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 2 ++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 3 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 10f273800645..3897dcb5d68d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1230,6 +1230,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define CCS_MASK(gt) \ ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) +#define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode) + /* * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution * All later gens can run the final buffer from the ppgtt diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index d8d893bafa51..6e309595b1e7 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1006,6 +1006,7 @@ static const struct intel_device_info xehpsdv_info = { .display = { }, .has_64k_pages = 1, .needs_compact_pt = 1, + .has_media_ratio_mode = 1, .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | @@ -1027,6 +1028,7 @@ static const struct intel_device_info xehpsdv_info = { .has_guc_deprivilege = 1, \ .has_heci_pxp = 1, \ .needs_compact_pt = 1, \ + .has_media_ratio_mode = 1, \ .platform_engine_mask = \ BIT(RCS0) | BIT(BCS0) | \ BIT(VECS0) | BIT(VECS1) | \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 60fc35ae81df..ebfaa6bcd508 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -152,6 +152,7 @@ enum intel_ppgtt_type { func(has_l3_dpf); \ func(has_llc); \ func(has_logical_ring_contexts); \ + func(has_media_ratio_mode); \ func(has_mslices); \ func(has_pooled_eu); \ func(has_pxp); \ -- 2.32.0

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[PULL] drm-misc-next-fixes
by Maxime Ripard 19 May '22

19 May '22

Hi Daniel, Dave, Here's this week drm-misc-next-fixes PR Maxime drm-misc-next-fixes-2022-05-19: A device tree binding change for Rockchip VOP2 The following changes since commit 6071c4c2a319da360b0bf2bc397d4fefad10b2c8: drm/qxl: add drm_gem_plane_helper_prepare_fb (2022-05-05 12:30:10 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2022-05-19 for you to fetch changes up to 5ee8c8f930ba7d20717c4fc2d9f1ce0e757d1155: drm/rockchip: Change register space names in vop2 (2022-05-17 00:16:33 +0200) ---------------------------------------------------------------- A device tree binding change for Rockchip VOP2 ---------------------------------------------------------------- Sascha Hauer (2): dt-bindings: display: rockchip: make reg-names mandatory for VOP2 drm/rockchip: Change register space names in vop2 .../devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 8 +++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4 ++-- 2 files changed, 9 insertions(+), 3 deletions(-)

1 0

[PATCH -next] drm/i915: Fix some integer constant macro to unsigned type
by Yipeng Zou 19 May '22

19 May '22

Build Kernel with gcc 7.5.0 or older, will get some error message: drivers/gpu/drm/i915/display/intel_ddi.c:1915:2: error: case label does not reduce to an integer constant case PORT_CLK_SEL_WRPLL1: ^~~~ ...... Look here : https://lore.kernel.org/r/YkwQ6%2BtIH8GQpuct@zn.tnic for the details why it happends. Reported-by: Hulk Robot <hulkci(a)huawei.com> Signed-off-by: Yipeng Zou <zouyipeng(a)huawei.com> --- drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 4 ++-- .../i915/gt/uc/abi/guc_communication_ctb_abi.h | 6 +++--- .../gpu/drm/i915/gt/uc/abi/guc_messages_abi.h | 14 +++++++------- drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 12 ++++++------ drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++-------- 5 files changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h index be9ac47fa9d0..cb16fd0ba8dd 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h @@ -50,8 +50,8 @@ #define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 3u) #define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0 -#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffff << 16) -#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0xffff << 0) +#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffffu << 16) +#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0xffffu << 0) #define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32 GUC_HXG_REQUEST_MSG_n_DATAn #define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64 GUC_HXG_REQUEST_MSG_n_DATAn diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h index c9086a600bce..e5c782283309 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h @@ -82,11 +82,11 @@ static_assert(sizeof(struct guc_ct_buffer_desc) == 64); #define GUC_CTB_HDR_LEN 1u #define GUC_CTB_MSG_MIN_LEN GUC_CTB_HDR_LEN #define GUC_CTB_MSG_MAX_LEN 256u -#define GUC_CTB_MSG_0_FENCE (0xffff << 16) -#define GUC_CTB_MSG_0_FORMAT (0xf << 12) +#define GUC_CTB_MSG_0_FENCE (0xffffu << 16) +#define GUC_CTB_MSG_0_FORMAT (0xfu << 12) #define GUC_CTB_FORMAT_HXG 0u #define GUC_CTB_MSG_0_RESERVED (0xf << 8) -#define GUC_CTB_MSG_0_NUM_DWORDS (0xff << 0) +#define GUC_CTB_MSG_0_NUM_DWORDS (0xffu << 0) /** * DOC: CTB HXG Message diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h index 29ac823acd4c..30e3cc06b0b7 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h @@ -40,17 +40,17 @@ */ #define GUC_HXG_MSG_MIN_LEN 1u -#define GUC_HXG_MSG_0_ORIGIN (0x1 << 31) +#define GUC_HXG_MSG_0_ORIGIN (0x1u << 31) #define GUC_HXG_ORIGIN_HOST 0u #define GUC_HXG_ORIGIN_GUC 1u -#define GUC_HXG_MSG_0_TYPE (0x7 << 28) +#define GUC_HXG_MSG_0_TYPE (0x7u << 28) #define GUC_HXG_TYPE_REQUEST 0u #define GUC_HXG_TYPE_EVENT 1u #define GUC_HXG_TYPE_NO_RESPONSE_BUSY 3u #define GUC_HXG_TYPE_NO_RESPONSE_RETRY 5u #define GUC_HXG_TYPE_RESPONSE_FAILURE 6u #define GUC_HXG_TYPE_RESPONSE_SUCCESS 7u -#define GUC_HXG_MSG_0_AUX (0xfffffff << 0) +#define GUC_HXG_MSG_0_AUX (0xfffffffu << 0) #define GUC_HXG_MSG_n_PAYLOAD (0xffffffff << 0) /** @@ -86,7 +86,7 @@ #define GUC_HXG_REQUEST_MSG_MIN_LEN GUC_HXG_MSG_MIN_LEN #define GUC_HXG_REQUEST_MSG_0_DATA0 (0xfff << 16) -#define GUC_HXG_REQUEST_MSG_0_ACTION (0xffff << 0) +#define GUC_HXG_REQUEST_MSG_0_ACTION (0xffffu << 0) #define GUC_HXG_REQUEST_MSG_n_DATAn GUC_HXG_MSG_n_PAYLOAD /** @@ -118,7 +118,7 @@ #define GUC_HXG_EVENT_MSG_MIN_LEN GUC_HXG_MSG_MIN_LEN #define GUC_HXG_EVENT_MSG_0_DATA0 (0xfff << 16) -#define GUC_HXG_EVENT_MSG_0_ACTION (0xffff << 0) +#define GUC_HXG_EVENT_MSG_0_ACTION (0xffffu << 0) #define GUC_HXG_EVENT_MSG_n_DATAn GUC_HXG_MSG_n_PAYLOAD /** @@ -188,8 +188,8 @@ */ #define GUC_HXG_FAILURE_MSG_LEN GUC_HXG_MSG_MIN_LEN -#define GUC_HXG_FAILURE_MSG_0_HINT (0xfff << 16) -#define GUC_HXG_FAILURE_MSG_0_ERROR (0xffff << 0) +#define GUC_HXG_FAILURE_MSG_0_HINT (0xfffu << 16) +#define GUC_HXG_FAILURE_MSG_0_ERROR (0xffffu << 0) /** * DOC: HXG Response diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h index 66027a42cda9..70154e522c51 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h @@ -15,20 +15,20 @@ #define GUC_STATUS _MMIO(0xc000) #define GS_RESET_SHIFT 0 -#define GS_MIA_IN_RESET (0x01 << GS_RESET_SHIFT) +#define GS_MIA_IN_RESET (0x01u << GS_RESET_SHIFT) #define GS_BOOTROM_SHIFT 1 -#define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT) -#define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT) +#define GS_BOOTROM_MASK (0x7Fu << GS_BOOTROM_SHIFT) +#define GS_BOOTROM_RSA_FAILED (0x50u << GS_BOOTROM_SHIFT) #define GS_BOOTROM_JUMP_PASSED (0x76 << GS_BOOTROM_SHIFT) #define GS_UKERNEL_SHIFT 8 -#define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT) +#define GS_UKERNEL_MASK (0xFFu << GS_UKERNEL_SHIFT) #define GS_MIA_SHIFT 16 -#define GS_MIA_MASK (0x07 << GS_MIA_SHIFT) +#define GS_MIA_MASK (0x07u << GS_MIA_SHIFT) #define GS_MIA_CORE_STATE (0x01 << GS_MIA_SHIFT) #define GS_MIA_HALT_REQUESTED (0x02 << GS_MIA_SHIFT) #define GS_MIA_ISR_ENTRY (0x04 << GS_MIA_SHIFT) #define GS_AUTH_STATUS_SHIFT 30 -#define GS_AUTH_STATUS_MASK (0x03 << GS_AUTH_STATUS_SHIFT) +#define GS_AUTH_STATUS_MASK (0x03u << GS_AUTH_STATUS_SHIFT) #define GS_AUTH_STATUS_BAD (0x01 << GS_AUTH_STATUS_SHIFT) #define GS_AUTH_STATUS_GOOD (0x02 << GS_AUTH_STATUS_SHIFT) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9ccb67eec1bd..8c10d66561b0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7566,19 +7566,19 @@ enum skl_power_gate { #define PORT_CLK_SEL_LCPLL_810 (2 << 29) #define PORT_CLK_SEL_SPLL (3 << 29) #define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29) -#define PORT_CLK_SEL_WRPLL1 (4 << 29) -#define PORT_CLK_SEL_WRPLL2 (5 << 29) -#define PORT_CLK_SEL_NONE (7 << 29) +#define PORT_CLK_SEL_WRPLL1 (4u << 29) +#define PORT_CLK_SEL_WRPLL2 (5u << 29) +#define PORT_CLK_SEL_NONE (7u << 29) #define PORT_CLK_SEL_MASK (7 << 29) /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) #define DDI_CLK_SEL_NONE (0x0 << 28) -#define DDI_CLK_SEL_MG (0x8 << 28) -#define DDI_CLK_SEL_TBT_162 (0xC << 28) -#define DDI_CLK_SEL_TBT_270 (0xD << 28) -#define DDI_CLK_SEL_TBT_540 (0xE << 28) -#define DDI_CLK_SEL_TBT_810 (0xF << 28) +#define DDI_CLK_SEL_MG (0x8u << 28) +#define DDI_CLK_SEL_TBT_162 (0xCu << 28) +#define DDI_CLK_SEL_TBT_270 (0xDu << 28) +#define DDI_CLK_SEL_TBT_540 (0xEu << 28) +#define DDI_CLK_SEL_TBT_810 (0xFu << 28) #define DDI_CLK_SEL_MASK (0xF << 28) /* Transcoder clock selection */ -- 2.17.1

2 1

[PATCH v3 1/2] dt-bindings: lcdif: Add compatible for i.MX8MP
by Marek Vasut 19 May '22

19 May '22

Add compatible string for i.MX8MP LCDIF variant. This is called LCDIFv3 and is completely different from the LCDIFv3 found in i.MX23 in that it has a completely scrambled register layout compared to all previous LCDIF variants. The new LCDIFv3 also supports 36bit address space. However, except for the complete bit reshuffling, this is still LCDIF and it still works like one. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Alexander Stein <alexander.stein(a)ew.tq-group.com> Cc: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Cc: Lucas Stach <l.stach(a)pengutronix.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Rob Herring <robh+dt(a)kernel.org> Cc: Robby Cai <robby.cai(a)nxp.com> Cc: Sam Ravnborg <sam(a)ravnborg.org> Cc: Stefan Agner <stefan(a)agner.ch> Cc: devicetree(a)vger.kernel.org --- V2: No change V3: No change --- Documentation/devicetree/bindings/display/fsl,lcdif.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml index 900a56cae80e6..876015a44a1e6 100644 --- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml @@ -20,6 +20,7 @@ properties: - fsl,imx23-lcdif - fsl,imx28-lcdif - fsl,imx6sx-lcdif + - fsl,imx8mp-lcdif - items: - enum: - fsl,imx6sl-lcdif -- 2.35.1

2 2

[PATCH v6, 0/4] Cooperate with DSI RX devices to modify dsi funcs and delay mipi high to cooperate with panel sequence
by xinlei.lee＠mediatek.com 19 May '22

19 May '22

From: Xinlei Lee <xinlei.lee(a)mediatek.com> In upstream-v5.8, dsi_enable will operate panel_enable, but this modification has been moved in v5.9. In order to ensure the timing of dsi_power_on/off and the timing of pulling up/down the MIPI signal, the modification of v5.9 is synchronized in this series of patches. Change since v5: 1. Merged [v5,1/5] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 to [v5,4/5] drm/mediatek: keep dsi as LP00 before dcs cmds transfer, because in (v5,1/5) to adjust the dsi func sequence in order to move to lane_ready func together in (v5, 4/5). Changes since v4: 1. Dsi func modified to atomic operation. 2. Added fix tag. 3. Removed lane_ready print statement. Changes since v3: 1. Rebase kernel-5.18-rc1. 2. Added dsi_enable protection. 3. Encapsulates the dsi_lane_ready function. Changes since v2: 1. Rebase linux-next. Changes since v1: 1. Dsi sequence marked with patch adjustment. 2. Fixes: mtk_dsi: Use the drm_panel_bridge. Jitao Shi (2): drm/mediatek: Separate poweron/poweroff from enable/disable and define new funcs drm/mediatek: keep dsi as LP00 before dcs cmds transfer Xinlei Lee (2): drm/mediatek: Modify dsi funcs to atomic operations drm/mediatek: Add pull-down MIPI operation in mtk_dsi_poweroff function drivers/gpu/drm/mediatek/mtk_dsi.c | 93 ++++++++++++++++++++---------- 1 file changed, 63 insertions(+), 30 deletions(-) -- 2.18.0

4 10

[PULL] drm-intel-fixes
by Joonas Lahtinen 19 May '22

19 May '22

Hi Dave & Daniel, Two final -fixes for v5.18. One is to reject DMC with out-of-spec MMIO (Cc: stable) and another to correctly mark guilty contexts on GuC reset. Regards, Joonas *** drm-intel-fixes-2022-05-19: - Reject DMC firmware with out-of-spec MMIO addresses. - Correctly mark guilty context on GuC reset The following changes since commit 42226c989789d8da4af1de0c31070c96726d990c: Linux 5.18-rc7 (2022-05-15 18:08:58 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2022-05-19 for you to fetch changes up to 89e96d822bd51f7afe2d3e95a34099480b5c3d55: i915/guc/reset: Make __guc_reset_context aware of guilty engines (2022-05-16 10:13:39 +0300) ---------------------------------------------------------------- - Reject DMC firmware with out-of-spec MMIO addresses. - Correctly mark guilty context on GuC reset ---------------------------------------------------------------- Anusha Srivatsa (1): drm/i915/dmc: Add MMIO range restrictions Umesh Nerlige Ramappa (1): i915/guc/reset: Make __guc_reset_context aware of guilty engines drivers/gpu/drm/i915/display/intel_dmc.c | 44 +++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_reset.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 16 ++++----- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 16 +++++++++ 7 files changed, 72 insertions(+), 12 deletions(-)

1 0

[PATCH v4 0/3] eDP/DP Phy vdda realted function
by Kuogee Hsieh 19 May '22

19 May '22

1) add regulator_set_load() to eDP phy 2) add regulator_set_load() to DP phy 3) remove vdda related function out of eDP/DP controller Kuogee Hsieh (3): phy/qualcomm: add regulator_set_load to edp phy phy/qualcomm: add regulator_set_load to dp phy drm/msm/dp: delete vdda regulator related functions from eDP/DP controller drivers/gpu/drm/msm/dp/dp_parser.c | 14 ------ drivers/gpu/drm/msm/dp/dp_parser.h | 6 --- drivers/gpu/drm/msm/dp/dp_power.c | 95 +------------------------------------ drivers/phy/qualcomm/phy-qcom-edp.c | 10 +++- drivers/phy/qualcomm/phy-qcom-qmp.c | 12 +++++ 5 files changed, 23 insertions(+), 114 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

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