dri-devel June 2022

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[PATCH v2] drm/tegra: dc: rgb: Fix refcount leak in tegra_dc_rgb_probe
by Miaoqian Lin 03 Jun '22

03 Jun '22

of_get_child_by_name() returns a node pointer with refcount incremented, we should use of_node_put() on it when not need anymore. So add of_node_put() in error paths. Fixes: d8f4a9eda006 ("drm: Add NVIDIA Tegra20 support") Signed-off-by: Miaoqian Lin <linmq006(a)gmail.com> --- changes in v2: - update Fixes tag. v1 Link: https://lore.kernel.org/r/20220602155615.43277-1-linmq006@gmail.com --- drivers/gpu/drm/tegra/rgb.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c index ff8fce36d2aa..cef2b1b72385 100644 --- a/drivers/gpu/drm/tegra/rgb.c +++ b/drivers/gpu/drm/tegra/rgb.c @@ -196,12 +196,16 @@ int tegra_dc_rgb_probe(struct tegra_dc *dc) int err; np = of_get_child_by_name(dc->dev->of_node, "rgb"); - if (!np || !of_device_is_available(np)) - return -ENODEV; + if (!np || !of_device_is_available(np)) { + err = -ENODEV; + goto err_put_node; + } rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL); - if (!rgb) - return -ENOMEM; + if (!rgb) { + err = -ENOMEM; + goto err_put_node; + } rgb->output.dev = dc->dev; rgb->output.of_node = np; @@ -209,31 +213,34 @@ int tegra_dc_rgb_probe(struct tegra_dc *dc) err = tegra_output_probe(&rgb->output); if (err < 0) - return err; + goto err_put_node; + rgb->clk = devm_clk_get(dc->dev, NULL); if (IS_ERR(rgb->clk)) { dev_err(dc->dev, "failed to get clock\n"); - return PTR_ERR(rgb->clk); + err = PTR_ERR(rgb->clk); + goto err_put_node; } rgb->clk_parent = devm_clk_get(dc->dev, "parent"); if (IS_ERR(rgb->clk_parent)) { dev_err(dc->dev, "failed to get parent clock\n"); - return PTR_ERR(rgb->clk_parent); + err = PTR_ERR(rgb->clk_parent); + goto err_put_node; } err = clk_set_parent(rgb->clk, rgb->clk_parent); if (err < 0) { dev_err(dc->dev, "failed to set parent clock: %d\n", err); - return err; + goto err_put_node; } rgb->pll_d_out0 = clk_get_sys(NULL, "pll_d_out0"); if (IS_ERR(rgb->pll_d_out0)) { err = PTR_ERR(rgb->pll_d_out0); dev_err(dc->dev, "failed to get pll_d_out0: %d\n", err); - return err; + goto err_put_node; } if (dc->soc->has_pll_d2_out0) { @@ -241,13 +248,17 @@ int tegra_dc_rgb_probe(struct tegra_dc *dc) if (IS_ERR(rgb->pll_d2_out0)) { err = PTR_ERR(rgb->pll_d2_out0); dev_err(dc->dev, "failed to get pll_d2_out0: %d\n", err); - return err; + goto err_put_node; } } dc->rgb = &rgb->output; return 0; + +err_put_node: + of_node_put(np); + return err; } int tegra_dc_rgb_remove(struct tegra_dc *dc) -- 2.25.1

2 1

[PATCH] drm/stm: ltdc: update hardware error management
by Yannick Fertre 03 Jun '22

03 Jun '22

The latest hardware version (0x40100) supports a hardware threshold register (aka FUTR) to trigger a fifo underrun interrupt. A software threshold has been implemented for other hardware versions. The threshold is set to 128 by default. Signed-off-by: Yannick Fertre <yannick.fertre(a)foss.st.com> --- drivers/gpu/drm/stm/ltdc.c | 90 ++++++++++++++++++++++++++++++-------- drivers/gpu/drm/stm/ltdc.h | 6 ++- 2 files changed, 77 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index ff2075dd9474..42a3bd515477 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -162,16 +162,20 @@ #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ #define IER_LIE BIT(0) /* Line Interrupt Enable */ -#define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ +#define IER_FUWIE BIT(1) /* Fifo Underrun Warning Interrupt Enable */ #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ -#define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ +#define IER_RRIE BIT(3) /* Register Reload Interrupt Enable */ +#define IER_FUEIE BIT(6) /* Fifo Underrun Error Interrupt Enable */ +#define IER_CRCIE BIT(7) /* CRC Error Interrupt Enable */ #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ #define ISR_LIF BIT(0) /* Line Interrupt Flag */ -#define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ +#define ISR_FUWIF BIT(1) /* Fifo Underrun Warning Interrupt Flag */ #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ +#define ISR_FUEIF BIT(6) /* Fifo Underrun Error Interrupt Flag */ +#define ISR_CRCIF BIT(7) /* CRC Error Interrupt Flag */ #define EDCR_OCYEN BIT(25) /* Output Conversion to YCbCr 422: ENable */ #define EDCR_OCYSEL BIT(26) /* Output Conversion to YCbCr 422: SELection of the CCIR */ @@ -231,6 +235,8 @@ #define NB_PF 8 /* Max nb of HW pixel format */ +#define FUT_DFT 128 /* Default value of fifo underrun threshold */ + /* * Skip the first value and the second in case CRC was enabled during * the thread irq. This is to be sure CRC value is relevant for the @@ -711,12 +717,13 @@ static irqreturn_t ltdc_irq_thread(int irq, void *arg) ltdc_irq_crc_handle(ldev, crtc); } - /* Save FIFO Underrun & Transfer Error status */ mutex_lock(&ldev->err_lock); - if (ldev->irq_status & ISR_FUIF) - ldev->error_status |= ISR_FUIF; if (ldev->irq_status & ISR_TERRIF) - ldev->error_status |= ISR_TERRIF; + ldev->transfer_err++; + if (ldev->irq_status & ISR_FUEIF) + ldev->fifo_err++; + if (ldev->irq_status & ISR_FUWIF) + ldev->fifo_warn++; mutex_unlock(&ldev->err_lock); return IRQ_HANDLED; @@ -775,7 +782,7 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK); /* Enable IRQ */ - regmap_set_bits(ldev->regmap, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); + regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE); /* Commit shadow registers = update planes at next vblank */ if (!ldev->caps.plane_reg_shadow) @@ -801,13 +808,20 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, LXCR_CLUTEN | LXCR_LEN, 0); /* disable IRQ */ - regmap_clear_bits(ldev->regmap, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); + regmap_clear_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE); /* immediately commit disable of layers before switching off LTDC */ if (!ldev->caps.plane_reg_shadow) regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR); pm_runtime_put_sync(ddev->dev); + + /* clear interrupt error counters */ + mutex_lock(&ldev->err_lock); + ldev->transfer_err = 0; + ldev->fifo_err = 0; + ldev->fifo_warn = 0; + mutex_unlock(&ldev->err_lock); } #define CLK_TOLERANCE_HZ 50 @@ -1168,6 +1182,18 @@ static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc, return 0; } +static void ltdc_crtc_atomic_print_state(struct drm_printer *p, + const struct drm_crtc_state *state) +{ + struct drm_crtc *crtc = state->crtc; + struct ltdc_device *ldev = crtc_to_ltdc(crtc); + + drm_printf(p, "\ttransfer_error=%d\n", ldev->transfer_err); + drm_printf(p, "\tfifo_underrun_error=%d\n", ldev->fifo_err); + drm_printf(p, "\tfifo_underrun_warning=%d\n", ldev->fifo_warn); + drm_printf(p, "\tfifo_underrun_threshold=%d\n", ldev->fifo_threshold); +} + static const struct drm_crtc_funcs ltdc_crtc_funcs = { .destroy = drm_crtc_cleanup, .set_config = drm_atomic_helper_set_config, @@ -1178,6 +1204,7 @@ static const struct drm_crtc_funcs ltdc_crtc_funcs = { .enable_vblank = ltdc_crtc_enable_vblank, .disable_vblank = ltdc_crtc_disable_vblank, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, + .atomic_print_state = ltdc_crtc_atomic_print_state, }; static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = { @@ -1192,6 +1219,7 @@ static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = { .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, .set_crc_source = ltdc_crtc_set_crc_source, .verify_crc_source = ltdc_crtc_verify_crc_source, + .atomic_print_state = ltdc_crtc_atomic_print_state, }; /* @@ -1452,13 +1480,21 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, ldev->plane_fpsi[plane->index].counter++; mutex_lock(&ldev->err_lock); - if (ldev->error_status & ISR_FUIF) { - DRM_WARN("ltdc fifo underrun: please verify display mode\n"); - ldev->error_status &= ~ISR_FUIF; + if (ldev->transfer_err) { + DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err); + ldev->transfer_err = 0; } - if (ldev->error_status & ISR_TERRIF) { - DRM_WARN("ltdc transfer error\n"); - ldev->error_status &= ~ISR_TERRIF; + + if (ldev->caps.fifo_threshold) { + if (ldev->fifo_err) { + DRM_WARN("ltdc fifo underrun: please verify display mode\n"); + ldev->fifo_err = 0; + } + } else { + if (ldev->fifo_warn >= ldev->fifo_threshold) { + DRM_WARN("ltdc fifo underrun: please verify display mode\n"); + ldev->fifo_warn = 0; + } } mutex_unlock(&ldev->err_lock); } @@ -1700,6 +1736,10 @@ static void ltdc_encoder_enable(struct drm_encoder *encoder) DRM_DEBUG_DRIVER("\n"); + /* set fifo underrun threshold register */ + if (ldev->caps.fifo_threshold) + regmap_write(ldev->regmap, LTDC_FUT, ldev->fifo_threshold); + /* Enable LTDC */ regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); } @@ -1801,6 +1841,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.crc = false; ldev->caps.dynamic_zorder = false; ldev->caps.plane_rotation = false; + ldev->caps.fifo_threshold = false; break; case HWVER_20101: ldev->caps.layer_ofs = LAY_OFS_0; @@ -1818,6 +1859,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.crc = false; ldev->caps.dynamic_zorder = false; ldev->caps.plane_rotation = false; + ldev->caps.fifo_threshold = false; break; case HWVER_40100: ldev->caps.layer_ofs = LAY_OFS_1; @@ -1835,6 +1877,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.crc = true; ldev->caps.dynamic_zorder = true; ldev->caps.plane_rotation = true; + ldev->caps.fifo_threshold = true; break; default: return -ENODEV; @@ -1959,9 +2002,6 @@ int ltdc_load(struct drm_device *ddev) goto err; } - /* Disable interrupts */ - regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); - ret = ltdc_get_caps(ddev); if (ret) { DRM_ERROR("hardware identifier (0x%08x) not supported!\n", @@ -1969,8 +2009,22 @@ int ltdc_load(struct drm_device *ddev) goto err; } + /* Disable interrupts */ + if (ldev->caps.fifo_threshold) + regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE | + IER_TERRIE); + else + regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE | + IER_TERRIE | IER_FUEIE); + DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); + /* initialize default value for fifo underrun threshold & clear interrupt error counters */ + ldev->transfer_err = 0; + ldev->fifo_err = 0; + ldev->fifo_warn = 0; + ldev->fifo_threshold = FUT_DFT; + for (i = 0; i < ldev->caps.nb_irq; i++) { irq = platform_get_irq(pdev, i); if (irq < 0) { diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index 15139980d8ea..9d488043ffdb 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -30,6 +30,7 @@ struct ltdc_caps { bool crc; /* cyclic redundancy check supported */ bool dynamic_zorder; /* dynamic z-order */ bool plane_rotation; /* plane rotation */ + bool fifo_threshold; /* fifo underrun threshold supported */ }; #define LTDC_MAX_LAYER 4 @@ -45,8 +46,11 @@ struct ltdc_device { struct clk *pixel_clk; /* lcd pixel clock */ struct mutex err_lock; /* protecting error_status */ struct ltdc_caps caps; - u32 error_status; u32 irq_status; + u32 fifo_err; /* fifo underrun error counter */ + u32 fifo_warn; /* fifo underrun warning counter */ + u32 fifo_threshold; /* fifo underrun threshold */ + u32 transfer_err; /* transfer error counter */ struct fps_info plane_fpsi[LTDC_MAX_LAYER]; struct drm_atomic_state *suspend_state; int crc_skip_count; -- 2.25.1

1 0

[PATCH] drm/stm: ltdc: add support of horizontal & vertical mirroring
by Yannick Fertre 03 Jun '22

03 Jun '22

Support of vertical & horizontal mirroring features thanks to the plane rotation property. Signed-off-by: Yannick Fertre <yannick.fertre(a)foss.st.com> --- drivers/gpu/drm/stm/ltdc.c | 163 ++++++++++++++++++++++++------------- drivers/gpu/drm/stm/ltdc.h | 1 + 2 files changed, 108 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 00a6bc1b1d7c..ff2075dd9474 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -180,6 +180,7 @@ #define LXCR_LEN BIT(0) /* Layer ENable */ #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ +#define LXCR_HMEN BIT(8) /* Horizontal Mirroring ENable */ #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ @@ -197,7 +198,7 @@ #define LXBFCR_BOR GENMASK(18, 16) /* Blending ORder */ #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ -#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ +#define LXCFBLR_CFBP GENMASK(31, 16) /* Color Frame Buffer Pitch in bytes */ #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ @@ -1237,7 +1238,8 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, u32 y0 = newstate->crtc_y; u32 y1 = newstate->crtc_y + newstate->crtc_h - 1; u32 src_x, src_y, src_w, src_h; - u32 val, pitch_in_bytes, line_length, line_number, paddr, ahbp, avbp, bpcr; + u32 val, pitch_in_bytes, line_length, line_number, ahbp, avbp, bpcr; + u32 paddr, paddr1, paddr2; enum ltdc_pix_fmt pf; if (!newstate->crtc || !fb) { @@ -1289,13 +1291,6 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, } regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val); - /* Configures the color frame buffer pitch in bytes & line length */ - pitch_in_bytes = fb->pitches[0]; - line_length = fb->format->cpp[0] * - (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; - val = ((pitch_in_bytes << 16) | line_length); - regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); - /* Specifies the constant alpha value */ val = newstate->alpha >> 8; regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); @@ -1319,76 +1314,115 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, LXBFCR_BF2 | LXBFCR_BF1, val); } - /* Configures the frame buffer line number */ - line_number = y1 - y0 + 1; - regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number); - /* Sets the FB address */ paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 0); + if (newstate->rotation & DRM_MODE_REFLECT_X) + paddr += (fb->format->cpp[0] * (x1 - x0 + 1)) - 1; + + if (newstate->rotation & DRM_MODE_REFLECT_Y) + paddr += (fb->pitches[0] * (y1 - y0)); + DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr); + /* Configures the color frame buffer pitch in bytes & line length */ + line_length = fb->format->cpp[0] * + (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; + + if (newstate->rotation & DRM_MODE_REFLECT_Y) + /* Compute negative value (signed on 16 bits) for the picth */ + pitch_in_bytes = 0x10000 - fb->pitches[0]; + else + pitch_in_bytes = fb->pitches[0]; + + val = (pitch_in_bytes << 16) | line_length; + regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); + + /* Configures the frame buffer line number */ + line_number = y1 - y0 + 1; + regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number); + if (ldev->caps.ycbcr_input) { if (fb->format->is_yuv) { switch (fb->format->format) { case DRM_FORMAT_NV12: case DRM_FORMAT_NV21: - /* Configure the auxiliary frame buffer address 0 & 1 */ - paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1); - regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr); - regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr + 1); + /* Configure the auxiliary frame buffer address 0 */ + paddr1 = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1); + + if (newstate->rotation & DRM_MODE_REFLECT_X) + paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; - /* Configure the buffer length */ - val = ((pitch_in_bytes << 16) | line_length); - regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); + if (newstate->rotation & DRM_MODE_REFLECT_Y) + paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; - /* Configure the frame buffer line number */ - val = (line_number >> 1); - regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); + regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); break; case DRM_FORMAT_YUV420: - /* Configure the auxiliary frame buffer address 0 */ - paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1); - regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr); - - /* Configure the auxiliary frame buffer address 1 */ - paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2); - regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr); + /* Configure the auxiliary frame buffer address 0 & 1 */ + paddr1 = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1); + paddr2 = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2); - line_length = ((fb->format->cpp[0] * (x1 - x0 + 1)) >> 1) + - (ldev->caps.bus_width >> 3) - 1; + if (newstate->rotation & DRM_MODE_REFLECT_X) { + paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; + paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; + } - /* Configure the buffer length */ - val = (((pitch_in_bytes >> 1) << 16) | line_length); - regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); + if (newstate->rotation & DRM_MODE_REFLECT_Y) { + paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; + paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; + } - /* Configure the frame buffer line number */ - val = (line_number >> 1); - regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); + regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); + regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); break; case DRM_FORMAT_YVU420: - /* Configure the auxiliary frame buffer address 0 */ - paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2); - regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr); - - /* Configure the auxiliary frame buffer address 1 */ - paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1); - regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr); + /* Configure the auxiliary frame buffer address 0 & 1 */ + paddr1 = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2); + paddr2 = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1); - line_length = ((fb->format->cpp[0] * (x1 - x0 + 1)) >> 1) + - (ldev->caps.bus_width >> 3) - 1; + if (newstate->rotation & DRM_MODE_REFLECT_X) { + paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; + paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; + } - /* Configure the buffer length */ - val = (((pitch_in_bytes >> 1) << 16) | line_length); - regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); + if (newstate->rotation & DRM_MODE_REFLECT_Y) { + paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; + paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; + } - /* Configure the frame buffer line number */ - val = (line_number >> 1); - regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); + regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); + regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); break; } + /* + * Set the length and the number of lines of the auxiliary + * buffers if the framebuffer contains more than one plane. + */ + if (fb->format->num_planes > 1) { + if (newstate->rotation & DRM_MODE_REFLECT_Y) + /* + * Compute negative value (signed on 16 bits) + * for the picth + */ + pitch_in_bytes = 0x10000 - fb->pitches[1]; + else + pitch_in_bytes = fb->pitches[1]; + + line_length = ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) + + (ldev->caps.bus_width >> 3) - 1; + + /* Configure the auxiliary buffer length */ + val = (pitch_in_bytes << 16) | line_length; + regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); + + /* Configure the auxiliary frame buffer line number */ + val = line_number >> 1; + regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); + } + /* Configure YCbC conversion coefficient */ ltdc_set_ycbcr_coeffs(plane); @@ -1403,7 +1437,12 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, /* Enable layer and CLUT if needed */ val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; val |= LXCR_LEN; - regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN, val); + + /* Enable horizontal mirroring if requested */ + if (newstate->rotation & DRM_MODE_REFLECT_X) + val |= LXCR_HMEN; + + regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN | LXCR_HMEN, val); /* Commit shadow registers = update plane at next vblank */ if (ldev->caps.plane_reg_shadow) @@ -1432,8 +1471,8 @@ static void ltdc_plane_atomic_disable(struct drm_plane *plane, struct ltdc_device *ldev = plane_to_ltdc(plane); u32 lofs = plane->index * LAY_OFS; - /* disable layer */ - regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN, 0); + /* Disable layer */ + regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN | LXCR_HMEN, 0); /* Commit shadow registers = update plane at next vblank */ if (ldev->caps.plane_reg_shadow) @@ -1577,6 +1616,7 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) { struct ltdc_device *ldev = ddev->dev_private; struct drm_plane *primary, *overlay; + int supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; unsigned int i; int ret; @@ -1591,6 +1631,10 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) else drm_plane_create_zpos_immutable_property(primary, 0); + if (ldev->caps.plane_rotation) + drm_plane_create_rotation_property(primary, DRM_MODE_ROTATE_0, + supported_rotations); + /* Init CRTC according to its hardware features */ if (ldev->caps.crc) ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, @@ -1622,6 +1666,10 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1); else drm_plane_create_zpos_immutable_property(overlay, i); + + if (ldev->caps.plane_rotation) + drm_plane_create_rotation_property(overlay, DRM_MODE_ROTATE_0, + supported_rotations); } return 0; @@ -1752,6 +1800,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.plane_reg_shadow = false; ldev->caps.crc = false; ldev->caps.dynamic_zorder = false; + ldev->caps.plane_rotation = false; break; case HWVER_20101: ldev->caps.layer_ofs = LAY_OFS_0; @@ -1768,6 +1817,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.plane_reg_shadow = false; ldev->caps.crc = false; ldev->caps.dynamic_zorder = false; + ldev->caps.plane_rotation = false; break; case HWVER_40100: ldev->caps.layer_ofs = LAY_OFS_1; @@ -1784,6 +1834,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.plane_reg_shadow = true; ldev->caps.crc = true; ldev->caps.dynamic_zorder = true; + ldev->caps.plane_rotation = true; break; default: return -ENODEV; diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index 4855898bd4c0..15139980d8ea 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -29,6 +29,7 @@ struct ltdc_caps { bool plane_reg_shadow; /* plane shadow registers ability */ bool crc; /* cyclic redundancy check supported */ bool dynamic_zorder; /* dynamic z-order */ + bool plane_rotation; /* plane rotation */ }; #define LTDC_MAX_LAYER 4 -- 2.25.1

1 0

[PATCH] drm/stm: ltdc: add support of the dynamic z-order
by Yannick Fertre 03 Jun '22

03 Jun '22

Zpos property is immutable for all hardware versions except the last version (0x40100) which support the blending order feature (dynamic z-order). Signed-off-by: Yannick Fertre <yannick.fertre(a)foss.st.com> --- drivers/gpu/drm/stm/drv.c | 1 + drivers/gpu/drm/stm/ltdc.c | 23 ++++++++++++++++++++--- drivers/gpu/drm/stm/ltdc.h | 1 + 3 files changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c index 0da7cce2a1a2..c63945dc2260 100644 --- a/drivers/gpu/drm/stm/drv.c +++ b/drivers/gpu/drm/stm/drv.c @@ -95,6 +95,7 @@ static int drv_load(struct drm_device *ddev) ddev->mode_config.max_width = STM_MAX_FB_WIDTH; ddev->mode_config.max_height = STM_MAX_FB_HEIGHT; ddev->mode_config.funcs = &drv_mode_config_funcs; + ddev->mode_config.normalize_zpos = true; ret = ltdc_load(ddev); if (ret) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 6a9f613839b5..00a6bc1b1d7c 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -194,6 +194,7 @@ #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ +#define LXBFCR_BOR GENMASK(18, 16) /* Blending ORder */ #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ @@ -1309,7 +1310,14 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, plane->type != DRM_PLANE_TYPE_PRIMARY) val = BF1_PAXCA | BF2_1PAXCA; - regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, LXBFCR_BF2 | LXBFCR_BF1, val); + if (ldev->caps.dynamic_zorder) { + val |= (newstate->normalized_zpos << 16); + regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, + LXBFCR_BF2 | LXBFCR_BF1 | LXBFCR_BOR, val); + } else { + regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, + LXBFCR_BF2 | LXBFCR_BF1, val); + } /* Configures the frame buffer line number */ line_number = y1 - y0 + 1; @@ -1578,7 +1586,10 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) return -EINVAL; } - drm_plane_create_zpos_immutable_property(primary, 0); + if (ldev->caps.dynamic_zorder) + drm_plane_create_zpos_property(primary, 0, 0, ldev->caps.nb_layers - 1); + else + drm_plane_create_zpos_immutable_property(primary, 0); /* Init CRTC according to its hardware features */ if (ldev->caps.crc) @@ -1607,7 +1618,10 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) DRM_ERROR("Can not create overlay plane %d\n", i); goto cleanup; } - drm_plane_create_zpos_immutable_property(overlay, i); + if (ldev->caps.dynamic_zorder) + drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1); + else + drm_plane_create_zpos_immutable_property(overlay, i); } return 0; @@ -1737,6 +1751,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.ycbcr_output = false; ldev->caps.plane_reg_shadow = false; ldev->caps.crc = false; + ldev->caps.dynamic_zorder = false; break; case HWVER_20101: ldev->caps.layer_ofs = LAY_OFS_0; @@ -1752,6 +1767,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.ycbcr_output = false; ldev->caps.plane_reg_shadow = false; ldev->caps.crc = false; + ldev->caps.dynamic_zorder = false; break; case HWVER_40100: ldev->caps.layer_ofs = LAY_OFS_1; @@ -1767,6 +1783,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.ycbcr_output = true; ldev->caps.plane_reg_shadow = true; ldev->caps.crc = true; + ldev->caps.dynamic_zorder = true; break; default: return -ENODEV; diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index 59fc5d1bbbab..4855898bd4c0 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -28,6 +28,7 @@ struct ltdc_caps { bool ycbcr_output; /* ycbcr output converter supported */ bool plane_reg_shadow; /* plane shadow registers ability */ bool crc; /* cyclic redundancy check supported */ + bool dynamic_zorder; /* dynamic z-order */ }; #define LTDC_MAX_LAYER 4 -- 2.25.1

1 0

[PATCH] drm/stm: ltdc: disable all layers before crtc shutdown
by Yannick Fertre 03 Jun '22

03 Jun '22

All plans must be disabled before the CRTC shutdown helping the crtc to restart from a clean situation (without unwanted planes already enable). Signed-off-by: Yannick Fertre <yannick.fertre(a)foss.st.com> --- drivers/gpu/drm/stm/ltdc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 6bd45df8f5a7..eeefc3260c07 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -787,11 +787,17 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, { struct ltdc_device *ldev = crtc_to_ltdc(crtc); struct drm_device *ddev = crtc->dev; + int layer_index = 0; DRM_DEBUG_DRIVER("\n"); drm_crtc_vblank_off(crtc); + /* Disable all layers */ + for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++) + regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS, + LXCR_CLUTEN | LXCR_LEN, 0); + /* disable IRQ */ regmap_clear_bits(ldev->regmap, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); -- 2.25.1

1 0

[v1] drm/msm: add null checks for drm device to avoid crash during probe defer
by Vinod Polimera 03 Jun '22

03 Jun '22

During probe defer, drm device is not initialized and an external trigger to shutdown is trying to clean up drm device leading to crash. Add checks to avoid drm device cleanup in such cases. BUG: unable to handle kernel NULL pointer dereference at virtual address 00000000000000b8 Call trace: drm_atomic_helper_shutdown+0x44/0x144 msm_pdev_shutdown+0x2c/0x38 platform_shutdown+0x2c/0x38 device_shutdown+0x158/0x210 kernel_restart_prepare+0x40/0x4c kernel_restart+0x20/0x6c __arm64_sys_reboot+0x194/0x23c invoke_syscall+0x50/0x13c el0_svc_common+0xa0/0x17c do_el0_svc_compat+0x28/0x34 el0_svc_compat+0x20/0x70 el0t_32_sync_handler+0xa8/0xcc el0t_32_sync+0x1a8/0x1ac Signed-off-by: Vinod Polimera <quic_vpolimer(a)quicinc.com> --- drivers/gpu/drm/msm/msm_drv.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 4448536..d62ac66 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -142,6 +142,9 @@ static void msm_irq_uninstall(struct drm_device *dev) struct msm_drm_private *priv = dev->dev_private; struct msm_kms *kms = priv->kms; + if (!irq_has_action(kms->irq)) + return; + kms->funcs->irq_uninstall(kms); if (kms->irq_requested) free_irq(kms->irq, dev); @@ -259,6 +262,7 @@ static int msm_drm_uninit(struct device *dev) ddev->dev_private = NULL; drm_dev_put(ddev); + priv->dev = NULL; destroy_workqueue(priv->wq); @@ -1167,7 +1171,7 @@ void msm_drv_shutdown(struct platform_device *pdev) struct msm_drm_private *priv = platform_get_drvdata(pdev); struct drm_device *drm = priv ? priv->dev : NULL; - if (!priv || !priv->kms) + if (!priv || !priv->kms || !drm) return; drm_atomic_helper_shutdown(drm); -- 2.7.4

3 2

[v3] drm/msm/disp/dpu1: avoid clearing hw interrupts if hw_intr is null during drm uninit
by Vinod Polimera 03 Jun '22

03 Jun '22

If dp modeset init is failed due to panel being not ready and probe defers during drm bind, avoid clearing irqs and dereference hw_intr when hw_intr is null. BUG: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 Call trace: dpu_core_irq_uninstall+0x50/0xb0 dpu_irq_uninstall+0x18/0x24 msm_drm_uninit+0xd8/0x16c msm_drm_bind+0x580/0x5fc try_to_bring_up_master+0x168/0x1c0 __component_add+0xb4/0x178 component_add+0x1c/0x28 dp_display_probe+0x38c/0x400 platform_probe+0xb0/0xd0 really_probe+0xcc/0x2c8 __driver_probe_device+0xbc/0xe8 driver_probe_device+0x48/0xf0 __device_attach_driver+0xa0/0xc8 bus_for_each_drv+0x8c/0xd8 __device_attach+0xc4/0x150 device_initial_probe+0x1c/0x28 Changes in V2: - Update commit message and correct fixes tag. Changes in V3: - Misc changes in commit text. Fixes: f25f656608e3 ("drm/msm/dpu: merge struct dpu_irq into struct dpu_hw_intr") Signed-off-by: Vinod Polimera <quic_vpolimer(a)quicinc.com> Reviewed-by: Stephen Boyd <swboyd(a)chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov(a)linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index c515b7c..ab28577 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -599,6 +599,9 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) { int i; + if (!dpu_kms->hw_intr) + return; + pm_runtime_get_sync(&dpu_kms->pdev->dev); for (i = 0; i < dpu_kms->hw_intr->total_irqs; i++) if (!list_empty(&dpu_kms->hw_intr->irq_cb_tbl[i])) -- 2.7.4

1 0

[PATCH V15 06/24] LoongArch: Add writecombine support for drm
by Huacai Chen 03 Jun '22

03 Jun '22

LoongArch maintains cache coherency in hardware, but its WUC attribute (Weak-ordered UnCached, which is similar to WC) is out of the scope of cache coherency machanism. This means WUC can only used for write-only memory regions. Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: dri-devel(a)lists.freedesktop.org Reviewed-by: WANG Xuerui <git(a)xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com> Signed-off-by: Huacai Chen <chenhuacai(a)loongson.cn> --- drivers/gpu/drm/drm_vm.c | 2 +- drivers/gpu/drm/ttm/ttm_module.c | 2 +- include/drm/drm_cache.h | 8 ++++++++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c index e957d4851dc0..f024dc93939e 100644 --- a/drivers/gpu/drm/drm_vm.c +++ b/drivers/gpu/drm/drm_vm.c @@ -69,7 +69,7 @@ static pgprot_t drm_io_prot(struct drm_local_map *map, pgprot_t tmp = vm_get_page_prot(vma->vm_flags); #if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || \ - defined(__mips__) + defined(__mips__) || defined(__loongarch__) if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING)) tmp = pgprot_noncached(tmp); else diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index a3ad7c9736ec..b3fffe7b5062 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c @@ -74,7 +74,7 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp) #endif /* CONFIG_UML */ #endif /* __i386__ || __x86_64__ */ #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \ - defined(__powerpc__) || defined(__mips__) + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) if (caching == ttm_write_combined) tmp = pgprot_writecombine(tmp); else diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h index 22deb216b59c..08e0e3ffad13 100644 --- a/include/drm/drm_cache.h +++ b/include/drm/drm_cache.h @@ -67,6 +67,14 @@ static inline bool drm_arch_can_wc_memory(void) * optimization entirely for ARM and arm64. */ return false; +#elif defined(CONFIG_LOONGARCH) + /* + * LoongArch maintains cache coherency in hardware, but its WUC attribute + * (Weak-ordered UnCached, which is similar to WC) is out of the scope of + * cache coherency machanism. This means WUC can only used for write-only + * memory regions. + */ + return false; #else return true; #endif -- 2.27.0

1 0

[PATCH v5 0/6] Raspberry PI 4 V3D enablement
by Peter Robinson 03 Jun '22

03 Jun '22

This is a follow up from my v4 patchset. The power management pieces have been split out to a separate independent set of patches by Stefan [1]. This version 5 of the DRM patches are independent and given the V3D driver has been upstream for some time the two patches to enable it in defconfigs can be taken at anytime independent of the enablement for the Raspberry Pi 4. I've tested this using mesa 22.0.x and Wayland/Gnome on Fedora 36, it's more or less stable with basic testing. Changes since v4: - Fixes for device tree and bindings - Split out the power management changes into an independent set - Rebase to 5.18 - Individual changes in patches [1] https://www.spinics.net/lists/arm-kernel/msg980342.html Nicolas Saenz Julienne (1): arm64: config: Enable DRM_V3D Peter Robinson (5): dt-bindings: gpu: v3d: Add BCM2711's compatible drm/v3d: Get rid of pm code drm/v3d: Add support for bcm2711 ARM: dts: bcm2711: Enable V3D ARM: configs: Enable DRM_V3D .../devicetree/bindings/gpu/brcm,bcm-v3d.yaml | 1 + arch/arm/boot/dts/bcm2711-rpi.dtsi | 4 ++++ arch/arm/boot/dts/bcm2711.dtsi | 11 +++++++++++ arch/arm/configs/bcm2835_defconfig | 1 + arch/arm/configs/multi_v7_defconfig | 1 + arch/arm64/configs/defconfig | 1 + drivers/gpu/drm/v3d/Kconfig | 2 +- drivers/gpu/drm/v3d/v3d_debugfs.c | 18 +----------------- drivers/gpu/drm/v3d/v3d_drv.c | 12 +----------- drivers/gpu/drm/v3d/v3d_gem.c | 12 +----------- 10 files changed, 23 insertions(+), 40 deletions(-) -- 2.36.1

6 21

[PATCH v2 0/8] Add a panel API to return panel orientation
by Hsin-Yi Wang 03 Jun '22

03 Jun '22

Panels usually call drm_connector_set_panel_orientation(), which is later than drm/kms driver calling drm_dev_register(). This leads to a WARN()[1]. The orientation property is known earlier. For example, some panels parse the property through device tree during probe. The series add a panel API drm_panel_get_orientation() for drm/kms drivers. The drivers can use the API to get panel's orientation, so they can call drm_connector_set_panel_orientation() before drm_dev_register(). Panel needs to implement .get_orientation callback to return the property. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20220530081910.39… Hsin-Yi Wang (8): drm/panel: Add an API drm_panel_get_orientation() to return panel orientation drm/panel: boe-tv101wum-nl6: Implement .get_orientation callback drm/panel: panel-edp: Implement .get_orientation callback drm/panel: lvds: Implement .get_orientation callback drm/panel: panel-simple: Implement .get_orientation callback drm/panel: ili9881c: Implement .get_orientation callback drm/panel: elida-kd35t133: Implement .get_orientation callback drm/mediatek: Config orientation property if panel provides it drivers/gpu/drm/drm_panel.c | 8 ++++++++ drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 8 ++++++++ drivers/gpu/drm/panel/panel-edp.c | 8 ++++++++ drivers/gpu/drm/panel/panel-elida-kd35t133.c | 8 ++++++++ drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 8 ++++++++ drivers/gpu/drm/panel/panel-lvds.c | 8 ++++++++ drivers/gpu/drm/panel/panel-simple.c | 9 +++++++++ include/drm/drm_panel.h | 10 ++++++++++ 9 files changed, 77 insertions(+) -- 2.36.1.255.ge46751e96f-goog

4 14

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