dri-devel June 2022

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697 discussions

[PATCH] drm/i915: Add extra registers to GPU error dump
by Matt Roper 02 Jun '22

02 Jun '22

From: Stuart Summers <stuart.summers(a)intel.com> Our internal teams have identified a few additional engine registers that are worth inspecting in error state dumps during development & debug. Let's capture and print them as part of our error dump. For simplicity we'll just dump these registers on gen11 and beyond. Most of these registers have existed since earlier platforms (e.g., gen6 or gen7) but were initially introduced only for a subset of the platforms' engines; gen11 seems to be where they became available on all engines. Signed-off-by: Stuart Summers <stuart.summers(a)intel.com> Signed-off-by: Matt Roper <matthew.d.roper(a)intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 5 +++++ drivers/gpu/drm/i915/i915_gpu_error.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/i915_gpu_error.h | 7 +++++++ 3 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h index 44de10cf7837..889f0df3940b 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h @@ -8,6 +8,7 @@ #include "i915_reg_defs.h" +#define RING_EXCC(base) _MMIO((base) + 0x28) #define RING_TAIL(base) _MMIO((base) + 0x30) #define TAIL_ADDR 0x001FFFF8 #define RING_HEAD(base) _MMIO((base) + 0x34) @@ -133,6 +134,8 @@ (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \ REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1)) +#define RING_CSCMDOP(base) _MMIO((base) + 0x20c) + /* * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. * The lsb of each can be considered a separate enabling bit for encryption. @@ -149,6 +152,7 @@ REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1)) #define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8) /* gen12+ */ + #define MI_PREDICATE_RESULT_2(base) _MMIO((base) + 0x3bc) #define LOWER_SLICE_ENABLED (1 << 0) #define LOWER_SLICE_DISABLED (0 << 0) @@ -172,6 +176,7 @@ #define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2) #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3) #define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8) +#define RING_CTX_SR_CTL(base) _MMIO((base) + 0x244) #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4) #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 0512c66fa4f3..bff8a111424a 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -581,6 +581,15 @@ static void error_print_engine(struct drm_i915_error_state_buf *m, err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); } + if (GRAPHICS_VER(m->i915) >= 11) { + err_printf(m, " NOPID: 0x%08x\n", ee->nopid); + err_printf(m, " EXCC: 0x%08x\n", ee->excc); + err_printf(m, " CMD_CCTL: 0x%08x\n", ee->cmd_cctl); + err_printf(m, " CSCMDOP: 0x%08x\n", ee->cscmdop); + err_printf(m, " CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl); + err_printf(m, " DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi); + err_printf(m, " DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo); + } if (HAS_PPGTT(m->i915)) { err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); @@ -1224,6 +1233,16 @@ static void engine_record_registers(struct intel_engine_coredump *ee) ee->ipehr = ENGINE_READ(engine, IPEHR); } + if (GRAPHICS_VER(i915) >= 11) { + ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL); + ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP); + ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL); + ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW); + ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD); + ee->nopid = ENGINE_READ(engine, RING_NOPID); + ee->excc = ENGINE_READ(engine, RING_EXCC); + } + intel_engine_get_instdone(engine, &ee->instdone); ee->instpm = ENGINE_READ(engine, RING_INSTPM); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h index a611abacd9c2..55a143b92d10 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.h +++ b/drivers/gpu/drm/i915/i915_gpu_error.h @@ -84,6 +84,13 @@ struct intel_engine_coredump { u32 fault_reg; u64 faddr; u32 rc_psmi; /* sleep state */ + u32 nopid; + u32 excc; + u32 cmd_cctl; + u32 cscmdop; + u32 ctx_sr_ctl; + u32 dma_faddr_hi; + u32 dma_faddr_lo; struct intel_instdone instdone; /* GuC matched capture-lists info */ -- 2.35.3

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[PATCH v2] drm: bridge: adv7511: Add check for mipi_dsi_driver_register
by Jiasheng Jiang 02 Jun '22

02 Jun '22

As mipi_dsi_driver_register could return error if fails, it should be better to check the return value and return error if fails. Moreover, if i2c_add_driver fails, mipi_dsi_driver_register should be reverted. Fixes: 1e4d58cd7f88 ("drm/bridge: adv7533: Create a MIPI DSI device") Signed-off-by: Jiasheng Jiang <jiasheng(a)iscas.ac.cn> --- Changelog: v1 -> v2 *Change 1. Add the mipi_dsi_driver_unregister if i2c_add_driver fails. --- drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c index 5bb9300040dd..2275d15d4a8b 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c @@ -1392,10 +1392,21 @@ static struct i2c_driver adv7511_driver = { static int __init adv7511_init(void) { - if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) - mipi_dsi_driver_register(&adv7533_dsi_driver); + int ret; + + if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { + ret = mipi_dsi_driver_register(&adv7533_dsi_driver); + if (ret) + return ret; + } - return i2c_add_driver(&adv7511_driver); + ret = i2c_add_driver(&adv7511_driver); + if (ret) { + if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) + mipi_dsi_driver_unregister(&adv7533_dsi_driver); + } + + return ret; } module_init(adv7511_init); -- 2.25.1

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Re: [PATCH 07/14] leds: flashlight: mt6370: Add Mediatek MT6370 flashlight support
by Andy Shevchenko 02 Jun '22

02 Jun '22

On Tue, May 31, 2022 at 1:32 PM ChiaEn Wu <peterwu.pub(a)gmail.com> wrote: > > From: Alice Chen <alice_chen(a)richtek.com> > > Add Mediatek MT6370 flashlight support Same comments about the commit message. ... > +#include <linux/platform_device.h> > +#include <linux/property.h> > +#include <linux/regmap.h> + blank line? > +#include <media/v4l2-flash-led-class.h> + blank line > +enum { > + MT6370_LED_FLASH1, > + MT6370_LED_FLASH2, > + MT6370_MAX_LEDS > +}; ... > + struct mt6370_led *led = container_of(fl_cdev, struct mt6370_led, > + flash); > + struct mt6370_led *led = container_of(fl_cdev, struct mt6370_led, > + flash); Make a helper out of this #define to_mt637_led() container_of() and reuse. ... > + /* > + * For the flash turn on/off, HW rampping up/down time is 5ms/500us, ramping > + * respectively Period! > + */ ... > + const char * const states[] = { "off", "keep", "on" }; > + const char *str; > + int ret; > + > + if (!fwnode_property_read_string(init_data->fwnode, > + "default-state", &str)) { > + ret = match_string(states, ARRAY_SIZE(states), str); > + if (ret < 0) > + ret = STATE_OFF; > + > + led->default_state = ret; > + } fwnode_property_match_string()? ... > + if (!count || count > MT6370_MAX_LEDS) { > + dev_err(&pdev->dev, > + "No child node or node count over max led number %lu\n", count); > + return -EINVAL; return dev_err_probe(...); > + } -- With Best Regards, Andy Shevchenko

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[PATCH v5 0/6] i915: SSEU handling updates
by Matt Roper 02 Jun '22

02 Jun '22

This series reworks i915's internal handling of slice/subslice/EU (SSEU) data to represent platforms like Xe_HP in a more natural manner and to prepare for future platforms where the masks will need to grow in size. One key idea of this series is that although we have a fixed ABI to convey SSEU data to userspace (i.e., multiple u8[] arrays with data stored at different strides), we don't need to use this cumbersome format for the driver's own internal storage. As long as we can convert into the uapi form properly when responding to the I915_QUERY ioctl, it's preferable to use an internal storage format that's easier for the driver to work with. Another key point here is that we're reaching the point where subslice (DSS) masks will soon not fit within simple u32/u64 integer values. Xe_HP SDV and DG2 platforms today have subslice (DSS) masks that are 32 bits, which maxes out the current storage of a u32. With PVC the masks are represented by a pair of 32-bit registers, requiring a bump up to at least 64-bits of storage internally. We could switch to u64 for that in the short term, but since we already know that upcoming architectures intend to provide DSS fuse bits via three or more registers it's best to switch to a representation that's more future-proof but still easy to work with in the driver code. To accomodate this, we start storing our subslice mask for Xe_HP and beyond in a new typedef that can be processed by the linux/bitmap.h operations. Finally, since no userspace for Xe_HP or beyond is using the legacy I915_GETPARAM ioctl lookups for I915_PARAM_SLICE_MASK and I915_PARAM_SUBSLICE_MASK (since they've migrated to the more flexible I915_QUERY ioctl that can return more than a simple u32 value), we take the opportunity to officially drop support for those GETPARAM lookups on modern platforms. Maintaining support for these GETPARAM lookups don't make sense for a number of reasons: * Traditional slices no longer exist, and newer ideas like gslices, cslices, mslices, etc. aren't something userspace needs to query since it can be inferred from other information. * The GETPARAM ioctl doesn't have a way to distinguish between geometry subslice masks and compute subslice masks, which are distinct on Xe_HP and beyond. * The I915_GETPARAM ioctl is limited to returning a 32-bit value, so when subslice masks begin to exceed 32-bits (on PVC), it simply can't return the entire mask. * The GETPARAM ioctl doesn't have a way to give sensible information for multi-tile devices. v2: - Switch to union of hsw/xehp formats to keep the representation in a natural format for different types of hardware. - Avoid accessing internals of intel_sseu_ss_mask_t directly outside of intel_sseu.[ch]. - Include PVC SSEU which needs the larger SS mask storage enabled by this series. v3: - Correct a BIT(s) typo that should have been BIT(ss), causing incorrect handling on gen9 platforms. v4: - Eliminate sseu->{ss,eu}_stride fields and just calculate the proper value in the UAPI code that needs them. - Handle unwanted ~u8 sign extension at the callsite instead of inside sseu_set_eus. - Use BITMAP_BITS() macro rather than passing I915_MAX_SS_FUSE_BITS around directly to bitmap operations. - Improved debugfs / dmesg reporting for Xe_HP dumps - Various assertion check improvements. v5: - Rebase to latest drm-tip (resolve trivial conflicts) - Move XEHP_BITMAP_BITS() to the header so that we can also replace a usage of I915_MAX_SS_FUSE_BITS in one of the inline functions. (Bala) - Change the local variable in intel_slicemask_from_xehp_dssmask() from u16 to 'unsigned long' to make it a bit more future-proof. - Incorporate ack's received from Tvrtko and Lionel. Cc: Tvrtko Ursulin <tvrtko.ursulin(a)linux.intel.com> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan(a)intel.com> Matt Roper (6): drm/i915/xehp: Use separate sseu init function drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK drm/i915/sseu: Simplify gen11+ SSEU handling drm/i915/sseu: Don't try to store EU mask internally in UAPI format drm/i915/sseu: Disassociate internal subslice mask representation from uapi drm/i915/pvc: Add SSEU changes drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +- drivers/gpu/drm/i915/gt/intel_gt.c | 12 +- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c | 450 ++++++++++++------- drivers/gpu/drm/i915/gt/intel_sseu.h | 92 ++-- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_getparam.c | 11 +- drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_query.c | 26 +- drivers/gpu/drm/i915/intel_device_info.h | 1 + 13 files changed, 397 insertions(+), 264 deletions(-) -- 2.35.3

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[PATCH V14 06/24] LoongArch: Add writecombine support for drm
by Huacai Chen 02 Jun '22

02 Jun '22

LoongArch maintains cache coherency in hardware, but its WUC attribute (Weak-ordered UnCached, which is similar to WC) is out of the scope of cache coherency machanism. This means WUC can only used for write-only memory regions. Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: dri-devel(a)lists.freedesktop.org Reviewed-by: WANG Xuerui <git(a)xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com> Signed-off-by: Huacai Chen <chenhuacai(a)loongson.cn> --- drivers/gpu/drm/drm_vm.c | 2 +- drivers/gpu/drm/ttm/ttm_module.c | 2 +- include/drm/drm_cache.h | 8 ++++++++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c index e957d4851dc0..f024dc93939e 100644 --- a/drivers/gpu/drm/drm_vm.c +++ b/drivers/gpu/drm/drm_vm.c @@ -69,7 +69,7 @@ static pgprot_t drm_io_prot(struct drm_local_map *map, pgprot_t tmp = vm_get_page_prot(vma->vm_flags); #if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || \ - defined(__mips__) + defined(__mips__) || defined(__loongarch__) if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING)) tmp = pgprot_noncached(tmp); else diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index a3ad7c9736ec..b3fffe7b5062 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c @@ -74,7 +74,7 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp) #endif /* CONFIG_UML */ #endif /* __i386__ || __x86_64__ */ #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \ - defined(__powerpc__) || defined(__mips__) + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) if (caching == ttm_write_combined) tmp = pgprot_writecombine(tmp); else diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h index 22deb216b59c..08e0e3ffad13 100644 --- a/include/drm/drm_cache.h +++ b/include/drm/drm_cache.h @@ -67,6 +67,14 @@ static inline bool drm_arch_can_wc_memory(void) * optimization entirely for ARM and arm64. */ return false; +#elif defined(CONFIG_LOONGARCH) + /* + * LoongArch maintains cache coherency in hardware, but its WUC attribute + * (Weak-ordered UnCached, which is similar to WC) is out of the scope of + * cache coherency machanism. This means WUC can only used for write-only + * memory regions. + */ + return false; #else return true; #endif -- 2.27.0

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[PATCH 00/10] drm/mgag200: Convert device init to use device-info structure
by Thomas Zimmermann 02 Jun '22

02 Jun '22

Convert the device-init code to use a device-info structure for each model. The device info contains constants and flags that were previously located in different places of the code. Also refactor the PCI and VRAM initialization handling. A later patchset could convert the PCI magic numbers into constants. For modesetting, the per-model init functions currently don't do much. This will change when more model-specific code gets moved there. The modesetting and PLL code contains model-specific handling that should be refactored. Tested with G200 and G200EV hardware. Thomas Zimmermann (10): drm/mgag200: Remove special case for G200SE with <2 MiB drm/mgag200: Initialize each model in separate function drm/mgag200: Move PCI-option setup into model-specific code drm/mgag200: Call mgag200_device_probe_vram() from per-model init drm/mgag200: Implement new init logic drm/mgag200: Add struct mgag200_device_info drm/mgag200: Store HW_BUG_NO_STARTADD flag in device info drm/mgag200: Store maximum resolution and memory bandwith in device info drm/mgag200: Store vidrst flag in device info drm/mgag200: Store positions of I2C data and clock bits in device info drivers/gpu/drm/mgag200/Makefile | 14 +- drivers/gpu/drm/mgag200/mgag200_drv.c | 386 ++++++++-------------- drivers/gpu/drm/mgag200/mgag200_drv.h | 135 ++++++-- drivers/gpu/drm/mgag200/mgag200_g200.c | 200 +++++++++++ drivers/gpu/drm/mgag200/mgag200_g200eh.c | 50 +++ drivers/gpu/drm/mgag200/mgag200_g200eh3.c | 51 +++ drivers/gpu/drm/mgag200/mgag200_g200er.c | 46 +++ drivers/gpu/drm/mgag200/mgag200_g200ev.c | 50 +++ drivers/gpu/drm/mgag200/mgag200_g200ew3.c | 60 ++++ drivers/gpu/drm/mgag200/mgag200_g200se.c | 130 ++++++++ drivers/gpu/drm/mgag200/mgag200_g200wb.c | 50 +++ drivers/gpu/drm/mgag200/mgag200_i2c.c | 27 +- drivers/gpu/drm/mgag200/mgag200_mm.c | 116 ------- drivers/gpu/drm/mgag200/mgag200_mode.c | 100 ++---- drivers/gpu/drm/mgag200/mgag200_pll.c | 12 +- drivers/gpu/drm/mgag200/mgag200_reg.h | 2 + 16 files changed, 942 insertions(+), 487 deletions(-) create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200eh.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200eh3.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200er.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200ev.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200ew3.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200se.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200wb.c delete mode 100644 drivers/gpu/drm/mgag200/mgag200_mm.c base-commit: 2c8cc5cd20e28afe6b63acb28890e5f57d9bf055 prerequisite-patch-id: c2b2f08f0eccc9f5df0c0da49fa1d36267deb11d prerequisite-patch-id: c67e5d886a47b7d0266d81100837557fda34cb24 -- 2.36.1

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[PATCH V13 06/24] LoongArch: Add writecombine support for drm
by Huacai Chen 02 Jun '22

02 Jun '22

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[Bug 205089] New: amdgpu : drm:amdgpu_cs_ioctl : Failed to initialize parser -125
by bugzilla-daemon＠bugzilla.kernel.org 02 Jun '22

02 Jun '22

https://bugzilla.kernel.org/show_bug.cgi?id=205089 Bug ID: 205089 Summary: amdgpu : drm:amdgpu_cs_ioctl : Failed to initialize parser -125 Product: Drivers Version: 2.5 Kernel Version: 5.3.2 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: maxijac(a)free.fr Regression: No Hello, I am experiencing freezes with kernel 5.3.2 and amdgpu on a Vega 64 card. This happens during games (I experience it on CS:GO) but it is a bit random and takes time to eventually trigger. Once it triggers my dmesg is filled with errors: [ 9156.537524] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to initialize parser -125! [ 9156.747176] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to initialize parser -125! [ 9156.747224] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to initialize parser -125! [ 9156.883220] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to initialize parser -125! [ 9156.883285] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to initialize parser -125! When it happens, the image hangs and PC is unresponsive. Sometimes I manage to switch to a TTY, but then the screen is corrupted. HW: - AMD Ryzen 2700X CPU - AMD RX vega 64 SW: - Kernel 5.3.2 - Mesa 19.2.0 -- You are receiving this mail because: You are watching the assignee of the bug.

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[PATCH] drm/sun4i: Enable output signal premultiplication for DE2/DE3
by Roman Stratiienko 02 Jun '22

02 Jun '22

Otherwise alpha value is discarded, resulting incorrect pixel apperance on the display. This also fixes missing transparency for the most bottom layer. Test applications and videos w/ w/o this patch are available at [1]. [1]: https://github.com/GloDroid/glodroid_tests/issues/1 Signed-off-by: Roman Stratiienko <r.stratiienko(a)gmail.com> --- drivers/gpu/drm/sun4i/sun8i_mixer.c | 2 ++ drivers/gpu/drm/sun4i/sun8i_mixer.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index 6b1711a9a71f..71ab0a00b4de 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -320,6 +320,8 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, else val = 0; + val |= SUN8I_MIXER_BLEND_OUTCTL_PREMULTIPLY; + regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val); diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h index ebfc276b2464..bc12c95af6f3 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -65,6 +65,7 @@ #define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2)) #define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2) +#define SUN8I_MIXER_BLEND_OUTCTL_PREMULTIPLY BIT(0) #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1) #define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch) -- 2.30.2

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Re: [PATCH 06/14] leds: mt6370: Add Mediatek MT6370 Indicator support
by Andy Shevchenko 02 Jun '22

02 Jun '22

On Tue, May 31, 2022 at 1:16 PM ChiaEn Wu <peterwu.pub(a)gmail.com> wrote: > > From: Alice Chen <alice_chen(a)richtek.com> All below comments are applicable to the rest of the series as well (one way or another), so please fix all your patches where it's appropriate. > > Add Mediatek MT6370 Indicator support What indicator? Please also keep attention on English punctuation (missed period). ... > + help > + Support 4 channels and reg/pwm/breath mode. > + Isink4 can also use as a CHG_VIN power good Indicator. be used > + Say Y here to enable support for > + MT6370_RGB_LED device. ... > +#include <linux/module.h> > +#include <linux/mutex.h> > +#include <linux/platform_device.h> > +#include <linux/of.h> Are you sure this is the correct header? Seems you need mod_devicetable.h instead. > +#include <linux/property.h> > +#include <linux/regmap.h> ... > +struct mt6370_priv { > + struct mutex lock; Do you use regmap locking? > + struct device *dev; > + struct regmap *regmap; > + struct regmap_field *fields[F_MAX_FIELDS]; > + const struct reg_field *reg_fields; > + const struct linear_range *ranges; > + struct reg_cfg *reg_cfgs; > + unsigned int leds_count; > + unsigned int leds_active; > + bool is_mt6372; > + struct mt6370_led leds[]; > +}; ... > +static const unsigned int common_tfreqs[] = { > + 10000, 5000, 2000, 1000, 500, 200, 5, 1 Leave a comma at the end. > +}; > + > +static const unsigned int mt6372_tfreqs[] = { > + 8000, 4000, 2000, 1000, 500, 250, 8, 4 Ditto. > +}; -- With Best Regards, Andy Shevchenko

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dri-devel June 2022