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61998 discussions

[PATCH] soc: mediatek: mutex: add suffix 0 to DDP_COMPONENT_DITHER for mt8395
by Jason-JH.Lin 23 Jun '22

23 Jun '22

Add suffix 0 to DDP_COMPONENT_DITHER for mt8395. Fixes: 141311b856d8 ("soc: mediatek: mutex: add MT8365 support") Signed-off-by: Jason-JH.Lin <jason-jh.lin(a)mediatek.com> --- drivers/soc/mediatek/mtk-mutex.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index fa8e0ba38803..3b25fd6b91aa 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -130,7 +130,7 @@ #define MT8365_MUTEX_MOD_DISP_CCORR 13 #define MT8365_MUTEX_MOD_DISP_AAL 14 #define MT8365_MUTEX_MOD_DISP_GAMMA 15 -#define MT8365_MUTEX_MOD_DISP_DITHER 16 +#define MT8365_MUTEX_MOD_DISP_DITHER0 16 #define MT8365_MUTEX_MOD_DISP_DSI0 17 #define MT8365_MUTEX_MOD_DISP_PWM0 20 #define MT8365_MUTEX_MOD_DISP_DPI0 22 @@ -358,7 +358,7 @@ static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR, [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0, - [DDP_COMPONENT_DITHER] = MT8365_MUTEX_MOD_DISP_DITHER, + [DDP_COMPONENT_DITHER0] = MT8365_MUTEX_MOD_DISP_DITHER0, [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0, [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA, -- 2.18.0

3 3

[PATCH] drm/i915/guc/slpc: Use non-blocking H2G for waitboost
by Vinay Belgaumkar 23 Jun '22

23 Jun '22

SLPC min/max frequency updates require H2G calls. We are seeing timeouts when GuC channel is backed up and it is unable to respond in a timely fashion causing warnings and affecting CI. This is seen when waitboosting happens during a stress test. this patch updates the waitboost path to use a non-blocking H2G call instead, which returns as soon as the message is successfully transmitted. v2: Use drm_notice to report any errors that might occur while sending the waitboost H2G request (Tvrtko) Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar(a)intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 44 +++++++++++++++++---- 1 file changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c index 1db833da42df..e5e869c96262 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -98,6 +98,30 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc) return data->header.global_state; } +static int guc_action_slpc_set_param_nb(struct intel_guc *guc, u8 id, u32 value) +{ + u32 request[] = { + GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, + SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2), + id, + value, + }; + int ret; + + ret = intel_guc_send_nb(guc, request, ARRAY_SIZE(request), 0); + + return ret > 0 ? -EPROTO : ret; +} + +static int slpc_set_param_nb(struct intel_guc_slpc *slpc, u8 id, u32 value) +{ + struct intel_guc *guc = slpc_to_guc(slpc); + + GEM_BUG_ON(id >= SLPC_MAX_PARAM); + + return guc_action_slpc_set_param_nb(guc, id, value); +} + static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value) { u32 request[] = { @@ -208,12 +232,10 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq) */ with_intel_runtime_pm(&i915->runtime_pm, wakeref) { - ret = slpc_set_param(slpc, - SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, - freq); - if (ret) - i915_probe_error(i915, "Unable to force min freq to %u: %d", - freq, ret); + /* Non-blocking request will avoid stalls */ + ret = slpc_set_param_nb(slpc, + SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, + freq); } return ret; @@ -222,6 +244,8 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq) static void slpc_boost_work(struct work_struct *work) { struct intel_guc_slpc *slpc = container_of(work, typeof(*slpc), boost_work); + struct drm_i915_private *i915 = slpc_to_i915(slpc); + int err; /* * Raise min freq to boost. It's possible that @@ -231,8 +255,12 @@ static void slpc_boost_work(struct work_struct *work) */ mutex_lock(&slpc->lock); if (atomic_read(&slpc->num_waiters)) { - slpc_force_min_freq(slpc, slpc->boost_freq); - slpc->num_boosts++; + err = slpc_force_min_freq(slpc, slpc->boost_freq); + if (!err) + slpc->num_boosts++; + else + drm_notice(&i915->drm, "Failed to send waitboost request (%d)\n", + err); } mutex_unlock(&slpc->lock); } -- 2.35.1

6 12

[PATCH] drm/fb-helper: Fix out-of-bounds access
by Thomas Zimmermann 23 Jun '22

23 Jun '22

Clip memory range to screen-buffer size to avoid out-of-bounds access in fbdev deferred I/O's damage handling. Fbdev's deferred I/O can only track pages. From the range of pages, the damage handler computes the clipping rectangle for the display update. If the fbdev screen buffer ends near the beginning of a page, that page could contain more scanlines. The damage handler would then track these non-existing scanlines as dirty and provoke an out-of-bounds access during the screen update. Hence, clip the maximum memory range to the size of the screen buffer. While at it, rename the variables min/max to min_off/max_off in drm_fb_helper_deferred_io(). This avoids confusion with the macros of the same name. Reported-by: Nuno Gonçalves <nunojpg(a)gmail.com> Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> Tested-by: Nuno Gonçalves <nunojpg(a)gmail.com> Fixes: 67b723f5b742 ("drm/fb-helper: Calculate damaged area in separate helper") Cc: Thomas Zimmermann <tzimmermann(a)suse.de> Cc: Javier Martinez Canillas <javierm(a)redhat.com> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Maxime Ripard <mripard(a)kernel.org> Cc: <stable(a)vger.kernel.org> # v5.18+ --- drivers/gpu/drm/drm_fb_helper.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 5ad2b6a2778c..1705e8d345ab 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -680,7 +680,11 @@ static void drm_fb_helper_damage(struct fb_info *info, u32 x, u32 y, schedule_work(&helper->damage_work); } -/* Convert memory region into area of scanlines and pixels per scanline */ +/* + * Convert memory region into area of scanlines and pixels per + * scanline. The parameters off and len must not reach beyond + * the end of the framebuffer. + */ static void drm_fb_helper_memory_range_to_clip(struct fb_info *info, off_t off, size_t len, struct drm_rect *clip) { @@ -715,22 +719,29 @@ static void drm_fb_helper_memory_range_to_clip(struct fb_info *info, off_t off, */ void drm_fb_helper_deferred_io(struct fb_info *info, struct list_head *pagereflist) { - unsigned long start, end, min, max; + unsigned long start, end, min_off, max_off; struct fb_deferred_io_pageref *pageref; struct drm_rect damage_area; - min = ULONG_MAX; - max = 0; + min_off = ULONG_MAX; + max_off = 0; list_for_each_entry(pageref, pagereflist, list) { start = pageref->offset; end = start + PAGE_SIZE; - min = min(min, start); - max = max(max, end); + min_off = min(min_off, start); + max_off = max(max_off, end); } - if (min >= max) + if (min_off >= max_off) return; - drm_fb_helper_memory_range_to_clip(info, min, max - min, &damage_area); + /* + * As we can only track pages, we might reach beyond the end + * of the screen and account for non-existing scanlines. Hence, + * keep the covered memory area within the screen buffer. + */ + max_off = min(max_off, info->screen_size); + + drm_fb_helper_memory_range_to_clip(info, min_off, max_off - min_off, &damage_area); drm_fb_helper_damage(info, damage_area.x1, damage_area.y1, drm_rect_width(&damage_area), drm_rect_height(&damage_area)); -- 2.36.1

2 1

[PULL] drm-misc-fixes
by Maxime Ripard 23 Jun '22

23 Jun '22

Hi Dave, Daniel, Here's this week drm-misc-fixes PR Maxime drm-misc-fixes-2022-06-23: Multiple fixes in sun4i for suspend, DDC, DMA setup; A rework of vc4 to properly split the driver between hardware capabilities that wasn't done properly causing multiple crashes; and a panel quirk for Aya Neo Next The following changes since commit 0f9cd1ea10d307cad221d6693b648a8956e812b0: drm/ttm: fix bulk move handling v2 (2022-06-14 11:15:19 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2022-06-23 for you to fetch changes up to 85016f66af8506cb601fd4f4fde23ed327a266be: drm/sun4i: Return if frontend is not present (2022-06-22 16:42:25 +0200) ---------------------------------------------------------------- Multiple fixes in sun4i for suspend, DDC, DMA setup; A rework of vc4 to properly split the driver between hardware capabilities that wasn't done properly causing multiple crashes; and a panel quirk for Aya Neo Next ---------------------------------------------------------------- Dan Carpenter (1): drm/vc4: fix error code in vc4_check_tex_size() Jernej Skrabec (1): drm/sun4i: Add DMA mask and segment size Maxime Ripard (14): drm/vc4: plane: Prevent async update if we don't have a dlist drm/vc4: Consolidate Hardware Revision Check drm/vc4: bo: Rename vc4_dumb_create drm/vc4: bo: Split out Dumb buffers fixup drm/vc4: drv: Register a different driver on BCM2711 drm/vc4: kms: Register a different drm_mode_config_funcs on BCM2711 drm/vc4: plane: Register a different drm_plane_helper_funcs on BCM2711 drm/vc4: drv: Skip BO Backend Initialization on BCM2711 drm/vc4: crtc: Use an union to store the page flip callback drm/vc4: crtc: Move the BO handling out of common page-flip callback drm/vc4: crtc: Move the BO Handling out of Common Page-Flip Handler drm/vc4: crtc: Don't call into BO Handling on Async Page-Flips on BCM2711 drm/vc4: crtc: Fix out of order frames during asynchronous page flips drm/vc4: Warn if some v3d code is run on BCM2711 Maya Matuszczyk (1): drm: panel-orientation-quirks: Add quirk for Aya Neo Next Samuel Holland (2): drm/sun4i: dw-hdmi: Fix ddc-en GPIO consumer conflict drm/sun4i: Fix crash during suspend after component bind failure Saud Farooqui (2): drm/vc4: hdmi: Fixed possible integer overflow drm/sun4i: Return if frontend is not present drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 + drivers/gpu/drm/sun4i/sun4i_drv.c | 12 +- drivers/gpu/drm/sun4i/sun4i_layer.c | 2 +- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 54 +------ drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 - drivers/gpu/drm/vc4/vc4_bo.c | 62 +++++++- drivers/gpu/drm/vc4/vc4_crtc.c | 200 ++++++++++++++++++------- drivers/gpu/drm/vc4/vc4_drv.c | 97 ++++++++++-- drivers/gpu/drm/vc4/vc4_drv.h | 19 ++- drivers/gpu/drm/vc4/vc4_gem.c | 40 +++++ drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +- drivers/gpu/drm/vc4/vc4_hvs.c | 18 +-- drivers/gpu/drm/vc4/vc4_irq.c | 16 ++ drivers/gpu/drm/vc4/vc4_kms.c | 24 ++- drivers/gpu/drm/vc4/vc4_perfmon.c | 47 +++++- drivers/gpu/drm/vc4/vc4_plane.c | 29 +++- drivers/gpu/drm/vc4/vc4_render_cl.c | 4 + drivers/gpu/drm/vc4/vc4_v3d.c | 15 ++ drivers/gpu/drm/vc4/vc4_validate.c | 16 ++ drivers/gpu/drm/vc4/vc4_validate_shaders.c | 4 + 20 files changed, 505 insertions(+), 164 deletions(-)

1 0

[PATCH v13 00/14] drm/mediatek: Add MT8195 dp_intf driver
by Bo-Chen Chen 23 Jun '22

23 Jun '22

The dpi/dpintf driver and the added helper functions are required for the DisplayPort driver to work. This series is separated from [1] which is original from Guillaume. The display port driver is [2]. Changes for v13: 1. Change mediatek,mt8195-dp_intf to mediatek,mt8195-dp-intf. 2. Add kernel doc for mtk_dpi_conf. 3. Drop patch of tvd_pll enable. 4. Squash some color format transfer related patches. 5. Add new patch to support setting of direct connection to pins. 6. Change fix tag of "drm/mediatek: dpi: Only enable dpi after the bridge is enabled". Changes for v12: 1. Remove pll_gate. 2. Add more detailed commit message. 3. Separate tvd_clk patch and yuv422 output support from add dpintf support patch 4. Remove limit patch and use common driver codes to determine this. Changes for v11: 1. Rename ck_cg to pll_gate. 2. Add some commit message to clarify the modification reason. 3. Fix some driver order and modify for reviewers' comments. [1]:https://lore.kernel.org/all/20220523104758.29531-1-granquet@baylibre.com/ [2]:https://lore.kernel.org/all/20220610105522.13449-1-rex-bc.chen@mediatek.… Bo-Chen Chen (4): drm/mediatek: dpi: Add kernel document for struct mtk_dpi_conf drm/mediatek: dpi: Add support for quantization range drm/mediatek: dpi: Add YUV422 output support drm/mediatek: dpi: add config to control setting of direct connection to pins Guillaume Ranquet (9): drm/mediatek: dpi: implement a CK/DE pol toggle in SoC config drm/mediatek: dpi: implement a swap_input toggle in SoC config drm/mediatek: dpi: move dimension mask to SoC config drm/mediatek: dpi: move hvsize_mask to SoC config drm/mediatek: dpi: move swap_shift to SoC config drm/mediatek: dpi: move the yuv422_en_bit to SoC config drm/mediatek: dpi: move the csc_enable bit to SoC config drm/mediatek: dpi: Add dp_intf support drm/mediatek: dpi: Only enable dpi after the bridge is enabled Markus Schneider-Pargmann (1): dt-bindings: mediatek,dpi: Add DP_INTF compatible .../display/mediatek/mediatek,dpi.yaml | 11 +- drivers/gpu/drm/mediatek/mtk_dpi.c | 266 +++++++++++++++--- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 15 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 6 files changed, 253 insertions(+), 47 deletions(-) -- 2.18.0

4 24

[PATCH] drm: bridge: sii8620: fix possible off-by-one
by Hangyu Hua 23 Jun '22

23 Jun '22

The next call to sii8620_burst_get_tx_buf will result in off-by-one When ctx->burst.tx_count + size == ARRAY_SIZE(ctx->burst.tx_buf). The same thing happens in sii8620_burst_get_rx_buf. This patch also change tx_count and tx_buf to rx_count and rx_buf in sii8620_burst_get_rx_buf. It is unreasonable to check tx_buf's size and use rx_buf. Fixes: e19e9c692f81 ("drm/bridge/sii8620: add support for burst eMSC transmissions") Signed-off-by: Hangyu Hua <hbh25y(a)gmail.com> --- drivers/gpu/drm/bridge/sil-sii8620.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c index ec7745c31da0..ab0bce4a988c 100644 --- a/drivers/gpu/drm/bridge/sil-sii8620.c +++ b/drivers/gpu/drm/bridge/sil-sii8620.c @@ -605,7 +605,7 @@ static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len) u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count]; int size = len + 2; - if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { + if (ctx->burst.tx_count + size >= ARRAY_SIZE(ctx->burst.tx_buf)) { dev_err(ctx->dev, "TX-BLK buffer exhausted\n"); ctx->error = -EINVAL; return NULL; @@ -622,7 +622,7 @@ static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len) u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count]; int size = len + 1; - if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) { + if (ctx->burst.rx_count + size >= ARRAY_SIZE(ctx->burst.rx_buf)) { dev_err(ctx->dev, "RX-BLK buffer exhausted\n"); ctx->error = -EINVAL; return NULL; -- 2.25.1

2 2

[PATCH] gpu: drm: fix possible memory leak in drm_addmap_core()
by Hangyu Hua 23 Jun '22

23 Jun '22

map->handle need to be handled correctly when map->type is _DRM_SHM or _DRM_CONSISTENT just like map->type is _DRM_REGISTERS. Fixes: 8d153f7107ff ("drm: update user token hashing and map handles") Signed-off-by: Hangyu Hua <hbh25y(a)gmail.com> --- drivers/gpu/drm/drm_bufs.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c index fcca21e8efac..2b3f504c5f9c 100644 --- a/drivers/gpu/drm/drm_bufs.c +++ b/drivers/gpu/drm/drm_bufs.c @@ -344,6 +344,15 @@ static int drm_addmap_core(struct drm_device *dev, resource_size_t offset, if (!list) { if (map->type == _DRM_REGISTERS) iounmap(map->handle); + else if (map->type == _DRM_SHM) { + dev->sigdata.lock = dev->master->lock.hw_lock = NULL; + vfree(map->handle); + } else if (map->type == _DRM_CONSISTENT) { + dma_free_coherent(dev->dev, + map->size, + map->handle, + map->offset); + } kfree(map); return -EINVAL; } @@ -361,6 +370,15 @@ static int drm_addmap_core(struct drm_device *dev, resource_size_t offset, if (ret) { if (map->type == _DRM_REGISTERS) iounmap(map->handle); + else if (map->type == _DRM_SHM) { + dev->sigdata.lock = dev->master->lock.hw_lock = NULL; + vfree(map->handle); + } else if (map->type == _DRM_CONSISTENT) { + dma_free_coherent(dev->dev, + map->size, + map->handle, + map->offset); + } kfree(map); kfree(list); mutex_unlock(&dev->struct_mutex); -- 2.25.1

1 2

[PATCH] drm/i915/guc/slpc: Use non-blocking H2G for waitboost
by Vinay Belgaumkar 23 Jun '22

23 Jun '22

SLPC min/max frequency updates require H2G calls. We are seeing timeouts when GuC channel is backed up and it is unable to respond in a timely fashion causing warnings and affecting CI. This is seen when waitboosting happens during a stress test. this patch updates the waitboost path to use a non-blocking H2G call instead, which returns as soon as the message is successfully transmitted. v2: Use drm_notice to report any errors that might occur while sending the waitboost H2G request (Tvrtko) v3: Add drm_notice inside force_min_freq (Ashutosh) Cc: Ashutosh Dixit <ashutosh.dixit(a)intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar(a)intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 42 +++++++++++++++++---- 1 file changed, 35 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c index 2df31af70d63..ec9c4ca0f615 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -98,6 +98,30 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc) return data->header.global_state; } +static int guc_action_slpc_set_param_nb(struct intel_guc *guc, u8 id, u32 value) +{ + u32 request[] = { + GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, + SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2), + id, + value, + }; + int ret; + + ret = intel_guc_send_nb(guc, request, ARRAY_SIZE(request), 0); + + return ret > 0 ? -EPROTO : ret; +} + +static int slpc_set_param_nb(struct intel_guc_slpc *slpc, u8 id, u32 value) +{ + struct intel_guc *guc = slpc_to_guc(slpc); + + GEM_BUG_ON(id >= SLPC_MAX_PARAM); + + return guc_action_slpc_set_param_nb(guc, id, value); +} + static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value) { u32 request[] = { @@ -208,12 +232,14 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq) */ with_intel_runtime_pm(&i915->runtime_pm, wakeref) { - ret = slpc_set_param(slpc, - SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, - freq); + /* Non-blocking request will avoid stalls */ + ret = slpc_set_param_nb(slpc, + SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, + freq); if (ret) - i915_probe_error(i915, "Unable to force min freq to %u: %d", - freq, ret); + drm_notice(&i915->drm, + "Failed to send set_param for min freq(%d): (%d)\n", + freq, ret); } return ret; @@ -222,6 +248,7 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq) static void slpc_boost_work(struct work_struct *work) { struct intel_guc_slpc *slpc = container_of(work, typeof(*slpc), boost_work); + int err; /* * Raise min freq to boost. It's possible that @@ -231,8 +258,9 @@ static void slpc_boost_work(struct work_struct *work) */ mutex_lock(&slpc->lock); if (atomic_read(&slpc->num_waiters)) { - slpc_force_min_freq(slpc, slpc->boost_freq); - slpc->num_boosts++; + err = slpc_force_min_freq(slpc, slpc->boost_freq); + if (!err) + slpc->num_boosts++; } mutex_unlock(&slpc->lock); } -- 2.35.1

2 1

[PATCH v2 0/3] drm/msm/dp: More cleanups for force link train
by Stephen Boyd 23 Jun '22

23 Jun '22

These patches do a little cleanup on the v9 patch[1] from Kuogee. Changes from v1: * Reduce code even more in second patch * Pick up tags on first patch Stephen Boyd (3): drm/msm/dp: Reorganize code to avoid forward declaration drm/msm/dp: Remove pixel_rate from struct dp_ctrl drm/msm/dp: Get rid of dp_ctrl_on_stream_phy_test_report() drivers/gpu/drm/msm/dp/dp_ctrl.c | 148 ++++++++++++------------------- drivers/gpu/drm/msm/dp/dp_ctrl.h | 1 - 2 files changed, 59 insertions(+), 90 deletions(-) [1] https://lore.kernel.org/r/1655411200-7255-1-git-send-email-quic_khsieh@quic… base-commit: f2906aa863381afb0015a9eb7fefad885d4e5a56 prerequisite-patch-id: 2fc33a2830ec84d922023fddb585728c48a59525 -- https://chromeos.dev

1 3

[PATCH v2 1/2] agp/intel: Rename intel-gtt symbols
by Lucas De Marchi 22 Jun '22

22 Jun '22

Exporting the symbols like intel_gtt_* creates some confusion inside i915 that has symbols named similarly. In an attempt to isolate platforms needing intel-gtt.ko, commit 7a5c922377b4 ("drm/i915/gt: Split intel-gtt functions by arch") moved way too much inside gt/intel_gt_gmch.c, even the functions that don't callout to this module. Rename the symbols to make the separation clear. Signed-off-by: Lucas De Marchi <lucas.demarchi(a)intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> --- drivers/char/agp/intel-gtt.c | 58 ++++++++++++------------- drivers/gpu/drm/i915/gt/intel_gt_gmch.c | 16 +++---- include/drm/intel-gtt.h | 24 +++++----- 3 files changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 79a1b65527c2..fe7e2105e766 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -744,7 +744,7 @@ static void i830_write_entry(dma_addr_t addr, unsigned int entry, writel_relaxed(addr | pte_flags, intel_private.gtt + entry); } -bool intel_enable_gtt(void) +bool intel_gmch_enable_gtt(void) { u8 __iomem *reg; @@ -787,7 +787,7 @@ bool intel_enable_gtt(void) return true; } -EXPORT_SYMBOL(intel_enable_gtt); +EXPORT_SYMBOL(intel_gmch_enable_gtt); static int i830_setup(void) { @@ -821,8 +821,8 @@ static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) static int intel_fake_agp_configure(void) { - if (!intel_enable_gtt()) - return -EIO; + if (!intel_gmch_enable_gtt()) + return -EIO; intel_private.clear_fake_agp = true; agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; @@ -844,20 +844,20 @@ static bool i830_check_flags(unsigned int flags) return false; } -void intel_gtt_insert_page(dma_addr_t addr, - unsigned int pg, - unsigned int flags) +void intel_gmch_gtt_insert_page(dma_addr_t addr, + unsigned int pg, + unsigned int flags) { intel_private.driver->write_entry(addr, pg, flags); readl(intel_private.gtt + pg); if (intel_private.driver->chipset_flush) intel_private.driver->chipset_flush(); } -EXPORT_SYMBOL(intel_gtt_insert_page); +EXPORT_SYMBOL(intel_gmch_gtt_insert_page); -void intel_gtt_insert_sg_entries(struct sg_table *st, - unsigned int pg_start, - unsigned int flags) +void intel_gmch_gtt_insert_sg_entries(struct sg_table *st, + unsigned int pg_start, + unsigned int flags) { struct scatterlist *sg; unsigned int len, m; @@ -879,13 +879,13 @@ void intel_gtt_insert_sg_entries(struct sg_table *st, if (intel_private.driver->chipset_flush) intel_private.driver->chipset_flush(); } -EXPORT_SYMBOL(intel_gtt_insert_sg_entries); +EXPORT_SYMBOL(intel_gmch_gtt_insert_sg_entries); #if IS_ENABLED(CONFIG_AGP_INTEL) -static void intel_gtt_insert_pages(unsigned int first_entry, - unsigned int num_entries, - struct page **pages, - unsigned int flags) +static void intel_gmch_gtt_insert_pages(unsigned int first_entry, + unsigned int num_entries, + struct page **pages, + unsigned int flags) { int i, j; @@ -905,7 +905,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem, if (intel_private.clear_fake_agp) { int start = intel_private.stolen_size / PAGE_SIZE; int end = intel_private.gtt_mappable_entries; - intel_gtt_clear_range(start, end - start); + intel_gmch_gtt_clear_range(start, end - start); intel_private.clear_fake_agp = false; } @@ -934,12 +934,12 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem, if (ret != 0) return ret; - intel_gtt_insert_sg_entries(&st, pg_start, type); + intel_gmch_gtt_insert_sg_entries(&st, pg_start, type); mem->sg_list = st.sgl; mem->num_sg = st.nents; } else - intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, - type); + intel_gmch_gtt_insert_pages(pg_start, mem->page_count, mem->pages, + type); out: ret = 0; @@ -949,7 +949,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem, } #endif -void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) +void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) { unsigned int i; @@ -959,7 +959,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) } wmb(); } -EXPORT_SYMBOL(intel_gtt_clear_range); +EXPORT_SYMBOL(intel_gmch_gtt_clear_range); #if IS_ENABLED(CONFIG_AGP_INTEL) static int intel_fake_agp_remove_entries(struct agp_memory *mem, @@ -968,7 +968,7 @@ static int intel_fake_agp_remove_entries(struct agp_memory *mem, if (mem->page_count == 0) return 0; - intel_gtt_clear_range(pg_start, mem->page_count); + intel_gmch_gtt_clear_range(pg_start, mem->page_count); if (intel_private.needs_dmar) { intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); @@ -1431,22 +1431,22 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, } EXPORT_SYMBOL(intel_gmch_probe); -void intel_gtt_get(u64 *gtt_total, - phys_addr_t *mappable_base, - resource_size_t *mappable_end) +void intel_gmch_gtt_get(u64 *gtt_total, + phys_addr_t *mappable_base, + resource_size_t *mappable_end) { *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; *mappable_base = intel_private.gma_bus_addr; *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT; } -EXPORT_SYMBOL(intel_gtt_get); +EXPORT_SYMBOL(intel_gmch_gtt_get); -void intel_gtt_chipset_flush(void) +void intel_gmch_gtt_flush(void) { if (intel_private.driver->chipset_flush) intel_private.driver->chipset_flush(); } -EXPORT_SYMBOL(intel_gtt_chipset_flush); +EXPORT_SYMBOL(intel_gmch_gtt_flush); void intel_gmch_remove(void) { diff --git a/drivers/gpu/drm/i915/gt/intel_gt_gmch.c b/drivers/gpu/drm/i915/gt/intel_gt_gmch.c index 18e488672d1b..b1a6ff4c9377 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_gmch.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_gmch.c @@ -134,7 +134,7 @@ static void gen5_ggtt_insert_page(struct i915_address_space *vm, unsigned int flags = (cache_level == I915_CACHE_NONE) ? AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; - intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); + intel_gmch_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); } static void gen6_ggtt_insert_page(struct i915_address_space *vm, @@ -175,8 +175,8 @@ static void gen5_ggtt_insert_entries(struct i915_address_space *vm, unsigned int flags = (cache_level == I915_CACHE_NONE) ? AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; - intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT, - flags); + intel_gmch_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT, + flags); } /* @@ -306,18 +306,18 @@ static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm, void intel_gt_gmch_gen5_chipset_flush(struct intel_gt *gt) { - intel_gtt_chipset_flush(); + intel_gmch_gtt_flush(); } static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt) { - intel_gtt_chipset_flush(); + intel_gmch_gtt_flush(); } static void gen5_ggtt_clear_range(struct i915_address_space *vm, u64 start, u64 length) { - intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); + intel_gmch_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); } static void gen6_ggtt_clear_range(struct i915_address_space *vm, @@ -494,7 +494,7 @@ int intel_gt_gmch_gen5_probe(struct i915_ggtt *ggtt) return -EIO; } - intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end); + intel_gmch_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end); ggtt->gmadr = (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end); @@ -647,7 +647,7 @@ int intel_gt_gmch_gen8_probe(struct i915_ggtt *ggtt) int intel_gt_gmch_gen5_enable_hw(struct drm_i915_private *i915) { - if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt()) + if (GRAPHICS_VER(i915) < 6 && !intel_gmch_enable_gtt()) return -EIO; return 0; diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h index 67530bfef129..cb0d5b7200c7 100644 --- a/include/drm/intel-gtt.h +++ b/include/drm/intel-gtt.h @@ -10,24 +10,24 @@ struct agp_bridge_data; struct pci_dev; struct sg_table; -void intel_gtt_get(u64 *gtt_total, - phys_addr_t *mappable_base, - resource_size_t *mappable_end); +void intel_gmch_gtt_get(u64 *gtt_total, + phys_addr_t *mappable_base, + resource_size_t *mappable_end); int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, struct agp_bridge_data *bridge); void intel_gmch_remove(void); -bool intel_enable_gtt(void); +bool intel_gmch_enable_gtt(void); -void intel_gtt_chipset_flush(void); -void intel_gtt_insert_page(dma_addr_t addr, - unsigned int pg, - unsigned int flags); -void intel_gtt_insert_sg_entries(struct sg_table *st, - unsigned int pg_start, - unsigned int flags); -void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries); +void intel_gmch_gtt_flush(void); +void intel_gmch_gtt_insert_page(dma_addr_t addr, + unsigned int pg, + unsigned int flags); +void intel_gmch_gtt_insert_sg_entries(struct sg_table *st, + unsigned int pg_start, + unsigned int flags); +void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries); /* Special gtt memory types */ #define AGP_DCACHE_MEMORY 1 -- 2.36.1

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