Remove the repeated word 'and' from comments
Signed-off-by: Jiang Jian <jiangjian(a)cdjrlc.com>
---
drivers/gpu/drm/radeon/r300_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
index 60d5413bafa1..9d341cff63ee 100644
--- a/drivers/gpu/drm/radeon/r300_reg.h
+++ b/drivers/gpu/drm/radeon/r300_reg.h
@@ -1103,7 +1103,7 @@
* The destination register index is in FPI1 (color) and FPI3 (alpha)
* …
[View More]together with enable bits.
* There are separate enable bits for writing into temporary registers
- * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
+ * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_*
* /DSTA_OUTPUT). You can write to both at once, or not write at all (the
* same index must be used for both).
*
--
2.17.1
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This is the i915 driver VM_BIND feature design RFC patch series along
with the required uapi definition and description of intended use cases.
v2: Reduce the scope to simple Mesa use case.
Remove all compute related uapi, vm_bind/unbind queue support and
only support a timeline out fence instead of an in/out timeline
fence array.
v3: Expand documentation on dma-resv usage, TLB flushing, execbuf3 and
VM_UNBIND. Add FENCE_VALID and TLB_FLUSH flags.
v4: Remove …
[View More]I915_GEM_VM_BIND_TLB_FLUSH flag and add additional
uapi documentation for vm_bind/unbind.
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura(a)intel.com>
Niranjana Vishwanathapura (3):
drm/doc/rfc: VM_BIND feature design document
drm/i915: Update i915 uapi documentation
drm/doc/rfc: VM_BIND uapi definition
Documentation/gpu/rfc/i915_vm_bind.h | 252 +++++++++++++++++++++++++
Documentation/gpu/rfc/i915_vm_bind.rst | 245 ++++++++++++++++++++++++
Documentation/gpu/rfc/index.rst | 4 +
include/uapi/drm/i915_drm.h | 205 +++++++++++++++-----
4 files changed, 661 insertions(+), 45 deletions(-)
create mode 100644 Documentation/gpu/rfc/i915_vm_bind.h
create mode 100644 Documentation/gpu/rfc/i915_vm_bind.rst
--
2.21.0.rc0.32.g243a4c7e27
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Kernel uapi headers are supposed to use __[us]{8,16,32,64} types defined
by <linux/types.h> as opposed to 'uint32_t' and similar. See [1] for the
relevant discussion about this topic. In this particular case, the usage
of 'uint64_t' escaped headers_check as these macros are not being called
here. However, the following program triggers a compilation error:
#include <drm/drm_fourcc.h>
int main()
{
unsigned long x = AMD_FMT_MOD_CLEAR(RB);
return 0;
}
gcc error:
drm.…
[View More]c:5:27: error: ‘uint64_t’ undeclared (first use in this function)
5 | unsigned long x = AMD_FMT_MOD_CLEAR(RB);
| ^~~~~~~~~~~~~~~~~
This patch changes AMD_FMT_MOD_{SET,CLEAR} macros to use the correct
integer types, which fixes the above issue.
[1] https://lkml.org/lkml/2019/6/5/18
Fixes: 8ba16d599374 ("drm/fourcc: Add AMD DRM modifiers.")
Signed-off-by: Carlos Llamas <cmllamas(a)google.com>
---
include/uapi/drm/drm_fourcc.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index f1972154a594..0980678d502d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -1444,11 +1444,11 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
#define AMD_FMT_MOD_PIPE_MASK 0x7
#define AMD_FMT_MOD_SET(field, value) \
- ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
+ ((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)
#define AMD_FMT_MOD_GET(field, value) \
(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
#define AMD_FMT_MOD_CLEAR(field) \
- (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
+ (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
#if defined(__cplusplus)
}
--
2.37.0.rc0.104.g0611611a94-goog
[View Less]
These patches do a little cleanup on the v9 patch from Kuogee.
Stephen Boyd (3):
drm/msm/dp: Reorganize code to avoid forward declaration
drm/msm/dp: Remove pixel_rate from struct dp_ctrl
drm/msm/dp: Get rid of dp_ctrl_on_stream_phy_test_report()
drivers/gpu/drm/msm/dp/dp_ctrl.c | 145 ++++++++++++++-----------------
drivers/gpu/drm/msm/dp/dp_ctrl.h | 1 -
2 files changed, 65 insertions(+), 81 deletions(-)
[1] https://lore.kernel.org/r/1655411200-7255-1-git-send-email-quic_khsieh@…
[View More]quic…
base-commit: 9639746eebb13068dc9de6f436151bd88da2b827
prerequisite-patch-id: 2fc33a2830ec84d922023fddb585728c48a59525
--
https://chromeos.dev
[View Less]
This series introduces a binding for Type-C data lane switches. These
control the routing and operating modes of USB Type-C data lanes based
on the PD messaging from the Type-C port driver regarding connected
peripherals.
The first patch introduces a change to the Type-C mux class mode-switch
matching code, while the second adds a config guard to a Type-C header.
The next couple of patches introduce the new "typec-switch" binding as
well as one user of it (the ANX7625 drm bridge).
The …
[View More]remaining patches add functionality to the anx7625 driver to
register the mode-switches, as well as program its crosspoint
switch depending on which Type-C port has a DisplayPort (DP) peripheral
connected to it.
v3: https://lore.kernel.org/linux-usb/20220614193558.1163205-1-pmalani@chromium…
Changes since v3:
- Some more modifications to the anx7625 binding patch (4/7).
- Picked up 1 more Reviewed-by tag.
Pin-Yen Lin (1):
drm/bridge: anx7625: Add typec_mux_set callback function
Prashant Malani (6):
usb: typec: mux: Allow muxes to specify mode-switch
usb: typec: mux: Add CONFIG guards for functions
dt-bindings: usb: Add Type-C switch binding
dt-bindings: drm/bridge: anx7625: Add mode-switch support
drm/bridge: anx7625: Register number of Type C switches
drm/bridge: anx7625: Register Type-C mode switches
.../display/bridge/analogix,anx7625.yaml | 64 ++++++++
.../devicetree/bindings/usb/typec-switch.yaml | 74 +++++++++
drivers/gpu/drm/bridge/analogix/anx7625.c | 148 ++++++++++++++++++
drivers/gpu/drm/bridge/analogix/anx7625.h | 20 +++
drivers/usb/typec/mux.c | 8 +-
include/linux/usb/typec_mux.h | 44 +++++-
6 files changed, 350 insertions(+), 8 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/typec-switch.yaml
--
2.36.1.476.g0c4daa206d-goog
[View Less]
Refactor existing CRC code for layer mixer and add CRC support for interface blocks
Changes since V1:
- Create helper methods for collect_misr and setup_misr in dpu_hw_util.c
- Move common bitmasks into dpu_hw_util.h
- Update copyrights
- Create a dynamically allocated crcs array in dpu_crtc_state
- Collect CRCs for all drm_encoders connected to the crtc
Changes since V2:
- Separate dpu_hw_util changes into a separate patch
- Revert back to using a static array and define a macro for …
[View More]MAX_CRC_ENTRIES
Changes since V3:
- Move crcs array into block-specific get_crc helper methods
- Rename "enc" source string to "encoder"
Jessica Zhang (4):
drm/msm/dpu: Move LM CRC code into separate method
drm/msm/dpu: Move MISR methods to dpu_hw_util
drm/msm/dpu: Add MISR register support for interface
drm/msm/dpu: Add interface support for CRC debugfs
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 111 +++++++++++++++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 5 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 64 +++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 22 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 19 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 42 +-------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 49 ++++++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 16 +++
9 files changed, 269 insertions(+), 67 deletions(-)
--
2.35.1
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The 'vsync_cnt' is used to count the number of frames for a crtc.
Unfortunately, we increment the count after waking up userspace via
dpu_crtc_vblank_callback() calling drm_crtc_handle_vblank().
drm_crtc_handle_vblank() wakes up userspace processes that have called
drm_wait_vblank_ioctl(), and if that ioctl is expecting the count to
increase it won't.
Increment the count before calling into the drm APIs so that we don't
have to worry about ordering the increment with anything else in drm.
This …
[View More]fixes a software video decode test that fails to see frame counts
increase on Trogdor boards.
Cc: Mark Yacoub <markyacoub(a)chromium.org>
Cc: Jessica Zhang <quic_jesszhan(a)quicinc.com>
Fixes: 885455d6bf82 ("drm/msm: Change dpu_crtc_get_vblank_counter to use vsync count.")
Signed-off-by: Stephen Boyd <swboyd(a)chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 3a462e327e0e..a1b8c4592943 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1251,12 +1251,13 @@ static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
DPU_ATRACE_BEGIN("encoder_vblank_callback");
dpu_enc = to_dpu_encoder_virt(drm_enc);
+ atomic_inc(&phy_enc->vsync_cnt);
+
spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
if (dpu_enc->crtc)
dpu_crtc_vblank_callback(dpu_enc->crtc);
spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
- atomic_inc(&phy_enc->vsync_cnt);
DPU_ATRACE_END("encoder_vblank_callback");
}
base-commit: f2906aa863381afb0015a9eb7fefad885d4e5a56
--
https://chromeos.dev
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