12 Jul
2013
12 Jul
'13
3:46 p.m.
https://bugs.freedesktop.org/show_bug.cgi?id=66384
--- Comment #1 from Michel Dänzer michel@daenzer.net --- I think this is because the DRI2 MSC counters differ between CRTCs, so a DRI2 buffer swap or MSC wait times out.
AFAICT it might be tricky to fix this, at least without DRI3.
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