dri-devel October 2010

dri-devel@lists.freedesktop.org

76 participants
345 discussions

[PATCH 0/9] Typo fixes of faild to failed
by Joe Perches 22 Oct '10

22 Oct '10

Joe Perches (9): drivers/ata: typo fix of faild to failed drivers/gpu: typo fix of faild to failed drivers/net: typo fix of faild to failed drivers/rtc: typo fix of faild to failed drivers/video: typo fix of faild to failed fs/exofs: typo fix of faild to failed fs/jfs: typo fix of faild to failed kernel/trace: typo fix of faild to failed net/wanrouter: typo fix of faild to failed drivers/ata/pata_bf54x.c | 2 +- drivers/gpu/drm/radeon/radeon_cs.c | 2 +- drivers/net/ps3_gelic_net.c | 4 ++-- drivers/net/tulip/pnic2.c | 2 +- drivers/rtc/rtc-nuc900.c | 2 +- drivers/video/bf54x-lq043fb.c | 6 +++--- drivers/video/bfin-t350mcqb-fb.c | 2 +- fs/exofs/dir.c | 4 ++-- fs/exofs/inode.c | 14 +++++++------- fs/exofs/ios.c | 10 +++++----- fs/jfs/jfs_mount.c | 4 ++-- kernel/trace/trace_kprobe.c | 2 +- net/wanrouter/wanmain.c | 4 ++-- 13 files changed, 29 insertions(+), 29 deletions(-) -- 1.7.3.1.g432b3.dirty

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[067/103] drm/radeon/kms: fix possible sigbus in evergreen accel code
by Greg KH 22 Oct '10

22 Oct '10

2.6.35-stable review patch. If anyone has any objections, please let us know. ------------------ From: Alex Deucher <alexdeucher(a)gmail.com> Not upstream in Linus's tree as it was fixed by a much more intrusive patch in a different manner, commit c919b371cb734f42b11 2.6.35 and 2.6.36 do not contain blit support for evergreen asics so if they use unmappable vram, you can end up with an unreachable buffer address. This should not be applied to drm-next as that tree already contains evergreen blit support. This should only be applied to the 2.6.35 and 2.6.36 stable trees. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=30188 Signed-off-by: Alex Deucher <alexdeucher(a)gmail.com> Acked-by: Dave Airlie <airlied(a)redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh(a)suse.de> --- drivers/gpu/drm/radeon/evergreen.c | 2 ++ 1 file changed, 2 insertions(+) --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -1389,6 +1389,8 @@ int evergreen_mc_init(struct radeon_devi rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; rdev->mc.visible_vram_size = rdev->mc.aper_size; + /* limit it to the aperture size for now as there is no blit support in 2.6.35/36*/ + rdev->mc.real_vram_size = rdev->mc.visible_vram_size; r600_vram_gtt_location(rdev, &rdev->mc); radeon_update_bandwidth_info(rdev);

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[Bug 25718] gpu death at radeon_fence_wait
by bugzilla-daemon＠freedesktop.org 22 Oct '10

22 Oct '10

https://bugs.freedesktop.org/show_bug.cgi?id=25718 Alex Deucher <agd5f(a)yahoo.com> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|NEW |RESOLVED Resolution| |FIXED -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug.

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[PATCH 1/2] drm/kms: Lock mode_config.mutex consistently from the sysfs handling code.
by Francisco Jerez 22 Oct '10

22 Oct '10

Among other potential issues, this fixes a race between output polling and status_show() that could cause a load detection false positive with the nouveau driver. Signed-off-by: Francisco Jerez <currojerez(a)riseup.net> --- drivers/gpu/drm/drm_sysfs.c | 71 ++++++++++++++++++++++++++++--------------- 1 files changed, 46 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index 85da4c4..25a9d9e 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -157,9 +157,13 @@ static ssize_t status_show(struct device *device, char *buf) { struct drm_connector *connector = to_drm_connector(device); + struct drm_device *dev = connector->dev; enum drm_connector_status status; + mutex_lock(&dev->mode_config.mutex); status = connector->funcs->detect(connector, true); + mutex_unlock(&dev->mode_config.mutex); + return snprintf(buf, PAGE_SIZE, "%s\n", drm_get_connector_status_name(status)); } @@ -173,9 +177,11 @@ static ssize_t dpms_show(struct device *device, uint64_t dpms_status; int ret; + mutex_lock(&dev->mode_config.mutex); ret = drm_connector_property_get_value(connector, dev->mode_config.dpms_property, &dpms_status); + mutex_unlock(&dev->mode_config.mutex); if (ret) return 0; @@ -199,25 +205,27 @@ static ssize_t edid_show(struct file *filp, struct kobject *kobj, { struct device *connector_dev = container_of(kobj, struct device, kobj); struct drm_connector *connector = to_drm_connector(connector_dev); + struct drm_device *dev = connector->dev; unsigned char *edid; - size_t size; + size_t size, n = 0; + mutex_lock(&dev->mode_config.mutex); if (!connector->edid_blob_ptr) - return 0; + goto out; edid = connector->edid_blob_ptr->data; size = connector->edid_blob_ptr->length; if (!edid) - return 0; + goto out; if (off >= size) - return 0; - - if (off + count > size) - count = size - off; - memcpy(buf, edid + off, count); + goto out; - return count; + n = min(count, size - (size_t)off); + memcpy(buf, edid + off, n); +out: + mutex_unlock(&dev->mode_config.mutex); + return n; } static ssize_t modes_show(struct device *device, @@ -225,13 +233,16 @@ static ssize_t modes_show(struct device *device, char *buf) { struct drm_connector *connector = to_drm_connector(device); + struct drm_device *dev = connector->dev; struct drm_display_mode *mode; int written = 0; + mutex_lock(&dev->mode_config.mutex); list_for_each_entry(mode, &connector->modes, head) { written += snprintf(buf + written, PAGE_SIZE - written, "%s\n", mode->name); } + mutex_unlock(&dev->mode_config.mutex); return written; } @@ -245,7 +256,9 @@ static ssize_t subconnector_show(struct device *device, struct drm_property *prop = NULL; uint64_t subconnector; int is_tv = 0; - int ret; + int ret = 0; + + mutex_lock(&dev->mode_config.mutex); switch (connector->connector_type) { case DRM_MODE_CONNECTOR_DVII: @@ -260,21 +273,24 @@ static ssize_t subconnector_show(struct device *device, break; default: DRM_ERROR("Wrong connector type for this property\n"); - return 0; + goto out; } if (!prop) { DRM_ERROR("Unable to find subconnector property\n"); - return 0; + goto out; } ret = drm_connector_property_get_value(connector, prop, &subconnector); if (ret) - return 0; + goto out; - return snprintf(buf, PAGE_SIZE, "%s", is_tv ? - drm_get_tv_subconnector_name((int)subconnector) : - drm_get_dvi_i_subconnector_name((int)subconnector)); + ret = snprintf(buf, PAGE_SIZE, "%s", is_tv ? + drm_get_tv_subconnector_name((int)subconnector) : + drm_get_dvi_i_subconnector_name((int)subconnector)); +out: + mutex_unlock(&dev->mode_config.mutex); + return ret; } static ssize_t select_subconnector_show(struct device *device, @@ -286,7 +302,9 @@ static ssize_t select_subconnector_show(struct device *device, struct drm_property *prop = NULL; uint64_t subconnector; int is_tv = 0; - int ret; + int ret = 0; + + mutex_lock(&dev->mode_config.mutex); switch (connector->connector_type) { case DRM_MODE_CONNECTOR_DVII: @@ -301,21 +319,24 @@ static ssize_t select_subconnector_show(struct device *device, break; default: DRM_ERROR("Wrong connector type for this property\n"); - return 0; + goto out; } if (!prop) { DRM_ERROR("Unable to find select subconnector property\n"); - return 0; + goto out; } ret = drm_connector_property_get_value(connector, prop, &subconnector); if (ret) - return 0; + goto out; - return snprintf(buf, PAGE_SIZE, "%s", is_tv ? - drm_get_tv_select_name((int)subconnector) : - drm_get_dvi_i_select_name((int)subconnector)); + ret = snprintf(buf, PAGE_SIZE, "%s", is_tv ? + drm_get_tv_select_name((int)subconnector) : + drm_get_dvi_i_select_name((int)subconnector)); +out: + mutex_unlock(&dev->mode_config.mutex); + return ret; } static struct device_attribute connector_attrs[] = { -- 1.6.4.4

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[Bug 25718] gpu death at radeon_fence_wait
by bugzilla-daemon＠freedesktop.org 22 Oct '10

22 Oct '10

https://bugs.freedesktop.org/show_bug.cgi?id=25718 --- Comment #15 from Tobias Jakobi <liquid.acid(a)gmx.net> 2010-10-22 03:34:14 PDT --- I can now longer reproduce any of these issues. Should be bug be closed? -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug.

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[PATCH] drm/radeon/kms: implement display watermark support for evergreen
by Alex Deucher 22 Oct '10

22 Oct '10

Improper display watermarks can result in underflow to the display controllers which can cause flickering or other artifacts. This patch implements display watermark support and line buffer allocation for evergreen asics. Signed-off-by: Alex Deucher <alexdeucher(a)gmail.com> --- drivers/gpu/drm/radeon/evergreen.c | 437 ++++++++++++++++++++++++++++++++++- drivers/gpu/drm/radeon/evergreend.h | 13 + 2 files changed, 449 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 34d6ecc..f12a5b3 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -285,9 +285,444 @@ void evergreen_hpd_fini(struct radeon_device *rdev) } } +/* watermark setup */ + +static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, + struct radeon_crtc *radeon_crtc, + struct drm_display_mode *mode, + struct drm_display_mode *other_mode) +{ + u32 tmp = 0; + /* + * Line Buffer Setup + * There are 3 line buffers, each one shared by 2 display controllers. + * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between + * the display controllers. The paritioning is done via one of four + * preset allocations specified in bits 2:0: + * first display controller + * 0 - first half of lb (3840 * 2) + * 1 - first 3/4 of lb (5760 * 2) + * 2 - whole lb (7680 * 2) + * 3 - first 1/4 of lb (1920 * 2) + * second display controller + * 4 - second half of lb (3840 * 2) + * 5 - second 3/4 of lb (5760 * 2) + * 6 - whole lb (7680 * 2) + * 7 - last 1/4 of lb (1920 * 2) + */ + if (mode && other_mode) { + if (mode->hdisplay > other_mode->hdisplay) { + if (mode->hdisplay > 2560) + tmp = 1; /* 3/4 */ + else + tmp = 0; /* 1/2 */ + } else if (other_mode->hdisplay > mode->hdisplay) { + if (other_mode->hdisplay > 2560) + tmp = 3; /* 1/4 */ + else + tmp = 0; /* 1/2 */ + } else + tmp = 0; /* 1/2 */ + } else if (mode) + tmp = 2; /* whole */ + else if (other_mode) + tmp = 3; /* 1/4 */ + + /* second controller of the pair uses second half of the lb */ + if (radeon_crtc->crtc_id % 2) + tmp += 4; + WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); + + switch (tmp) { + case 0: + case 4: + default: + return 3840 * 2; + case 1: + case 5: + return 5760 * 2; + case 2: + case 6: + return 7680 * 2; + case 3: + case 7: + return 1920 * 2; + } +} + +static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev) +{ + u32 tmp = RREG32(MC_SHARED_CHMAP); + + switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { + case 0: + default: + return 1; + case 1: + return 2; + case 2: + return 4; + case 3: + return 8; + } +} + +struct evergreen_wm_params { + u32 dram_channels; /* number of dram channels */ + u32 yclk; /* bandwidth per dram data pin in kHz */ + u32 sclk; /* engine clock in kHz */ + u32 disp_clk; /* display clock in kHz */ + u32 src_width; /* viewport width */ + u32 active_time; /* active display time in ns */ + u32 blank_time; /* blank time in ns */ + bool interlaced; /* mode is interlaced */ + fixed20_12 vsc; /* vertical scale ratio */ + u32 num_heads; /* number of active crtcs */ + u32 bytes_per_pixel; /* bytes per pixel display + overlay */ + u32 lb_size; /* line buffer allocated to pipe */ + u32 vtaps; /* vertical scaler taps */ +}; + +static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm) +{ + /* Calculate DRAM Bandwidth and the part allocated to display. */ + fixed20_12 dram_efficiency; /* 0.7 */ + fixed20_12 yclk, dram_channels, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + yclk.full = dfixed_const(wm->yclk); + yclk.full = dfixed_div(yclk, a); + dram_channels.full = dfixed_const(wm->dram_channels * 4); + a.full = dfixed_const(10); + dram_efficiency.full = dfixed_const(7); + dram_efficiency.full = dfixed_div(dram_efficiency, a); + bandwidth.full = dfixed_mul(dram_channels, yclk); + bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); + + return dfixed_trunc(bandwidth); +} + +static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm) +{ + /* Calculate DRAM Bandwidth and the part allocated to display. */ + fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ + fixed20_12 yclk, dram_channels, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + yclk.full = dfixed_const(wm->yclk); + yclk.full = dfixed_div(yclk, a); + dram_channels.full = dfixed_const(wm->dram_channels * 4); + a.full = dfixed_const(10); + disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ + disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); + bandwidth.full = dfixed_mul(dram_channels, yclk); + bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); + + return dfixed_trunc(bandwidth); +} + +static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm) +{ + /* Calculate the display Data return Bandwidth */ + fixed20_12 return_efficiency; /* 0.8 */ + fixed20_12 sclk, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + sclk.full = dfixed_const(wm->sclk); + sclk.full = dfixed_div(sclk, a); + a.full = dfixed_const(10); + return_efficiency.full = dfixed_const(8); + return_efficiency.full = dfixed_div(return_efficiency, a); + a.full = dfixed_const(32); + bandwidth.full = dfixed_mul(a, sclk); + bandwidth.full = dfixed_mul(bandwidth, return_efficiency); + + return dfixed_trunc(bandwidth); +} + +static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm) +{ + /* Calculate the DMIF Request Bandwidth */ + fixed20_12 disp_clk_request_efficiency; /* 0.8 */ + fixed20_12 disp_clk, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + disp_clk.full = dfixed_const(wm->disp_clk); + disp_clk.full = dfixed_div(disp_clk, a); + a.full = dfixed_const(10); + disp_clk_request_efficiency.full = dfixed_const(8); + disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); + a.full = dfixed_const(32); + bandwidth.full = dfixed_mul(a, disp_clk); + bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency); + + return dfixed_trunc(bandwidth); +} + +static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm) +{ + /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ + u32 dram_bandwidth = evergreen_dram_bandwidth(wm); + u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm); + u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm); + + return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); +} + +static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm) +{ + /* Calculate the display mode Average Bandwidth + * DisplayMode should contain the source and destination dimensions, + * timing, etc. + */ + fixed20_12 bpp; + fixed20_12 line_time; + fixed20_12 src_width; + fixed20_12 bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + line_time.full = dfixed_const(wm->active_time + wm->blank_time); + line_time.full = dfixed_div(line_time, a); + bpp.full = dfixed_const(wm->bytes_per_pixel); + src_width.full = dfixed_const(wm->src_width); + bandwidth.full = dfixed_mul(src_width, bpp); + bandwidth.full = dfixed_mul(bandwidth, wm->vsc); + bandwidth.full = dfixed_div(bandwidth, line_time); + + return dfixed_trunc(bandwidth); +} + +static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm) +{ + /* First calcualte the latency in ns */ + u32 mc_latency = 2000; /* 2000 ns. */ + u32 available_bandwidth = evergreen_available_bandwidth(wm); + u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; + u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; + u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ + u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + + (wm->num_heads * cursor_line_pair_return_time); + u32 latency = mc_latency + other_heads_data_return_time + dc_latency; + u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; + fixed20_12 a, b, c; + + if (wm->num_heads == 0) + return 0; + + a.full = dfixed_const(2); + b.full = dfixed_const(1); + if ((wm->vsc.full > a.full) || + ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || + (wm->vtaps >= 5) || + ((wm->vsc.full >= a.full) && wm->interlaced)) + max_src_lines_per_dst_line = 4; + else + max_src_lines_per_dst_line = 2; + + a.full = dfixed_const(available_bandwidth); + b.full = dfixed_const(wm->num_heads); + a.full = dfixed_div(a, b); + + b.full = dfixed_const(1000); + c.full = dfixed_const(wm->disp_clk); + b.full = dfixed_div(c, b); + c.full = dfixed_const(wm->bytes_per_pixel); + b.full = dfixed_mul(b, c); + + lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b)); + + a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); + b.full = dfixed_const(1000); + c.full = dfixed_const(lb_fill_bw); + b.full = dfixed_div(c, b); + a.full = dfixed_div(a, b); + line_fill_time = dfixed_trunc(a); + + if (line_fill_time < wm->active_time) + return latency; + else + return latency + (line_fill_time - wm->active_time); + +} + +static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm) +{ + if (evergreen_average_bandwidth(wm) <= + (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) + return true; + else + return false; +}; + +static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm) +{ + if (evergreen_average_bandwidth(wm) <= + (evergreen_available_bandwidth(wm) / wm->num_heads)) + return true; + else + return false; +}; + +static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm) +{ + u32 lb_partitions = wm->lb_size / wm->src_width; + u32 line_time = wm->active_time + wm->blank_time; + u32 latency_tolerant_lines; + u32 latency_hiding; + fixed20_12 a; + + a.full = dfixed_const(1); + if (wm->vsc.full > a.full) + latency_tolerant_lines = 1; + else { + if (lb_partitions <= (wm->vtaps + 1)) + latency_tolerant_lines = 1; + else + latency_tolerant_lines = 2; + } + + latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); + + if (evergreen_latency_watermark(wm) <= latency_hiding) + return true; + else + return false; +} + +static void evergreen_program_watermarks(struct radeon_device *rdev, + struct radeon_crtc *radeon_crtc, + u32 lb_size, u32 num_heads) +{ + struct drm_display_mode *mode = &radeon_crtc->base.mode; + struct evergreen_wm_params wm; + u32 pixel_period; + u32 line_time = 0; + u32 latency_watermark_a = 0, latency_watermark_b = 0; + u32 priority_a_mark = 0, priority_b_mark = 0; + u32 priority_a_cnt = PRIORITY_OFF; + u32 priority_b_cnt = PRIORITY_OFF; + u32 pipe_offset = radeon_crtc->crtc_id * 16; + u32 tmp, arb_control3; + fixed20_12 a, b, c; + + if (radeon_crtc->base.enabled && num_heads && mode) { + pixel_period = 1000000 / (u32)mode->clock; + line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); + priority_a_cnt = 0; + priority_b_cnt = 0; + + wm.yclk = rdev->pm.current_mclk * 10; + wm.sclk = rdev->pm.current_sclk * 10; + wm.disp_clk = mode->clock; + wm.src_width = mode->crtc_hdisplay; + wm.active_time = mode->crtc_hdisplay * pixel_period; + wm.blank_time = line_time - wm.active_time; + wm.interlaced = false; + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + wm.interlaced = true; + wm.vsc = radeon_crtc->vsc; + wm.vtaps = 1; + if (radeon_crtc->rmx_type != RMX_OFF) + wm.vtaps = 2; + wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ + wm.lb_size = lb_size; + wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); + wm.num_heads = num_heads; + + /* set for high clocks */ + latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535); + /* set for low clocks */ + /* wm.yclk = low clk; wm.sclk = low clk */ + latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535); + + /* possibly force display priority to high */ + /* should really do this at mode validation time... */ + if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || + !evergreen_average_bandwidth_vs_available_bandwidth(&wm) || + !evergreen_check_latency_hiding(&wm) || + (rdev->disp_priority == 2)) { + DRM_INFO("force priority to high\n"); + priority_a_cnt |= PRIORITY_ALWAYS_ON; + priority_b_cnt |= PRIORITY_ALWAYS_ON; + } + + a.full = dfixed_const(1000); + b.full = dfixed_const(mode->clock); + b.full = dfixed_div(b, a); + c.full = dfixed_const(latency_watermark_a); + c.full = dfixed_mul(c, b); + c.full = dfixed_mul(c, radeon_crtc->hsc); + c.full = dfixed_div(c, a); + a.full = dfixed_const(16); + c.full = dfixed_div(c, a); + priority_a_mark = dfixed_trunc(c); + priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; + + a.full = dfixed_const(1000); + b.full = dfixed_const(mode->clock); + b.full = dfixed_div(b, a); + c.full = dfixed_const(latency_watermark_b); + c.full = dfixed_mul(c, b); + c.full = dfixed_mul(c, radeon_crtc->hsc); + c.full = dfixed_div(c, a); + a.full = dfixed_const(16); + c.full = dfixed_div(c, a); + priority_b_mark = dfixed_trunc(c); + priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; + } + + /* select wm A */ + arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); + tmp = arb_control3; + tmp &= ~LATENCY_WATERMARK_MASK(3); + tmp |= LATENCY_WATERMARK_MASK(1); + WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); + WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, + (LATENCY_LOW_WATERMARK(latency_watermark_a) | + LATENCY_HIGH_WATERMARK(line_time))); + /* select wm B */ + tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); + tmp &= ~LATENCY_WATERMARK_MASK(3); + tmp |= LATENCY_WATERMARK_MASK(2); + WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); + WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, + (LATENCY_LOW_WATERMARK(latency_watermark_b) | + LATENCY_HIGH_WATERMARK(line_time))); + /* restore original selection */ + WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); + + /* write the priority marks */ + WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); + WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); + +} + void evergreen_bandwidth_update(struct radeon_device *rdev) { - /* XXX */ + struct drm_display_mode *mode0 = NULL; + struct drm_display_mode *mode1 = NULL; + u32 num_heads = 0, lb_size; + int i; + + radeon_update_display_priority(rdev); + + for (i = 0; i < rdev->num_crtc; i++) { + if (rdev->mode_info.crtcs[i]->base.enabled) + num_heads++; + } + for (i = 0; i < rdev->num_crtc; i += 2) { + mode0 = &rdev->mode_info.crtcs[i]->base.mode; + mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; + lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); + evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); + lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); + evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); + } } static int evergreen_mc_wait_for_idle(struct radeon_device *rdev) diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index c41b49c..113c70c 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h @@ -412,6 +412,19 @@ #define SOFT_RESET_REGBB (1 << 22) #define SOFT_RESET_ORB (1 << 23) +/* display watermarks */ +#define DC_LB_MEMORY_SPLIT 0x6b0c +#define PRIORITY_A_CNT 0x6b18 +#define PRIORITY_MARK_MASK 0x7fff +#define PRIORITY_OFF (1 << 16) +#define PRIORITY_ALWAYS_ON (1 << 20) +#define PRIORITY_B_CNT 0x6b1c +#define PIPE0_ARBITRATION_CONTROL3 0x0bf0 +# define LATENCY_WATERMARK_MASK(x) ((x) << 16) +#define PIPE0_LATENCY_CONTROL 0x0bf4 +# define LATENCY_LOW_WATERMARK(x) ((x) << 0) +# define LATENCY_HIGH_WATERMARK(x) ((x) << 16) + #define IH_RB_CNTL 0x3e00 # define IH_RB_ENABLE (1 << 0) # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ -- 1.7.1.1

1 0

[Bug 28402] random radeon/kms/drm related freezes with kernel 2.6.34
by bugzilla-daemon＠freedesktop.org 21 Oct '10

21 Oct '10

https://bugs.freedesktop.org/show_bug.cgi?id=28402 --- Comment #84 from mrsteven(a)gmx.de 2010-10-21 15:56:00 PDT --- (In reply to comment #44) > I am currently testing d594e46ace22afa1621254f6f669e65430048153 + > 8e36113082821980c60ce89a6c5d45fc9492fc26 and the following patch as suggested > by Dave Airlie on IRC: > > ---8<--------- > diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c > index c827738..d1a7803 100644 > --- a/drivers/gpu/drm/radeon/r300.c > +++ b/drivers/gpu/drm/radeon/r300.c > @@ -477,7 +477,7 @@ void r300_mc_init(struct radeon_device *rdev) > default: rdev->mc.vram_width = 128; break; > } > r100_vram_init_sizes(rdev); > - base = rdev->mc.aper_base; > + base = 0; > if (rdev->flags & RADEON_IS_IGP) > base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; > radeon_vram_location(rdev, &rdev->mc, base); I have the same problem since 2.6.34. The above hack fixes it for me (tested with 2.6.35.7 and a few earlier 2.6.35 releases, in frequent use for more than a month now), while the patch from comment #82 does not help in my case (last freeze was while using the search bar of firefox). Video chip is a: 01:00.0 VGA compatible controller: ATI Technologies Inc RV350 [Mobility Radeon 9600 M10] (prog-if 00 [VGA controller]) Subsystem: ASUSTeK Computer Inc. Device 1772 Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 11 Memory at d0000000 (32-bit, prefetchable) [size=128M] I/O ports at d800 [size=256] Memory at ff8f0000 (32-bit, non-prefetchable) [size=64K] Expansion ROM at ff8c0000 [disabled] [size=128K] Capabilities: [58] AGP version 2.0 Capabilities: [50] Power Management version 2 Kernel driver in use: radeon With the updated patch I get these messages: Oct 21 16:12:28 [kernel] [drm] initializing kernel modesetting (RV350 0x1002:0x4E50). Oct 21 16:12:28 [kernel] [drm] register mmio base: 0xFF8F0000 Oct 21 16:12:28 [kernel] [drm] register mmio size: 65536 Oct 21 16:12:28 [kernel] agpgart-intel 0000:00:00.0: AGP 2.0 bridge Oct 21 16:12:28 [kernel] agpgart-intel 0000:00:00.0: putting AGP V2 device into 4x mode Oct 21 16:12:28 [kernel] radeon 0000:01:00.0: putting AGP V2 device into 4x mode Oct 21 16:12:28 [kernel] radeon 0000:01:00.0: GTT: 256M 0xE0000000 - 0xEFFFFFFF Oct 21 16:12:28 [kernel] [drm] Generation 2 PCI interface, using max accessible memory Oct 21 16:12:28 [kernel] radeon 0000:01:00.0: VRAM: 64M 0xD0000000 - 0xD3FFFFFF (64M used) Oct 21 16:12:28 [kernel] [drm] radeon: irq initialized. Oct 21 16:12:28 [kernel] [drm] Detected VRAM RAM=64M, BAR=128M Oct 21 16:12:28 [kernel] [drm] RAM width 128bits DDR Oct 21 16:12:28 [kernel] [TTM] Zone kernel: Available graphics memory: 442550 kiB. Oct 21 16:12:28 [kernel] [TTM] Zone highmem: Available graphics memory: 1036090 kiB. Oct 21 16:12:28 [kernel] [TTM] Initializing pool allocator. Oct 21 16:12:28 [kernel] [drm] radeon: 64M of VRAM memory ready Oct 21 16:12:28 [kernel] [drm] radeon: 256M of GTT memory ready. *SNIP* While with the hack from comment #44 it looks like this: Oct 22 00:28:16 [kernel] [drm] radeon kernel modesetting enabled. Oct 22 00:28:16 [kernel] radeon 0000:01:00.0: PCI INT A -> Link[LNKA] -> GSI 11 (level, low) -> IRQ 11 Oct 22 00:28:16 [kernel] [drm] initializing kernel modesetting (RV350 0x1002:0x4E50). Oct 22 00:28:16 [kernel] [drm] register mmio base: 0xFF8F0000 Oct 22 00:28:16 [kernel] [drm] register mmio size: 65536 Oct 22 00:28:16 [kernel] agpgart-intel 0000:00:00.0: AGP 2.0 bridge Oct 22 00:28:16 [kernel] agpgart-intel 0000:00:00.0: putting AGP V2 device into 4x mode Oct 22 00:28:16 [kernel] radeon 0000:01:00.0: putting AGP V2 device into 4x mode Oct 22 00:28:16 [kernel] radeon 0000:01:00.0: GTT: 256M 0xE0000000 - 0xEFFFFFFF Oct 22 00:28:16 [kernel] [drm] Generation 2 PCI interface, using max accessible memory Oct 22 00:28:16 [kernel] radeon 0000:01:00.0: VRAM: 64M 0x00000000 - 0x03FFFFFF (64M used) Oct 22 00:28:16 [kernel] [drm] radeon: irq initialized. Oct 22 00:28:16 [kernel] [drm] Detected VRAM RAM=64M, BAR=128M Oct 22 00:28:16 [kernel] [drm] RAM width 128bits DDR Oct 22 00:28:16 [kernel] [TTM] Zone kernel: Available graphics memory: 442550 kiB. Oct 22 00:28:16 [kernel] [TTM] Zone highmem: Available graphics memory: 1036090 kiB. Oct 22 00:28:16 [kernel] [TTM] Initializing pool allocator. Oct 22 00:28:16 [kernel] [drm] radeon: 64M of VRAM memory ready Oct 22 00:28:16 [kernel] [drm] radeon: 256M of GTT memory ready. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug.

1 0

[Bug 31035] New: HDMI Output detect the TV, but doesn't send image
by bugzilla-daemon＠freedesktop.org 21 Oct '10

21 Oct '10

https://bugs.freedesktop.org/show_bug.cgi?id=31035 Summary: HDMI Output detect the TV, but doesn't send image Product: DRI Version: XOrg CVS Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: DRM/Radeon AssignedTo: dri-devel(a)lists.freedesktop.org ReportedBy: maximi89(a)gmail.com Created an attachment (id=39614) --> (https://bugs.freedesktop.org/attachment.cgi?id=39614) Xorg.0.log Xrandr detects the TV, but doesn't send anyimage to the TV, the TV say NO SIGNAL. [maximi89@gateway gnash2]$ xrandr Screen 0: minimum 320 x 200, current 1366 x 768, maximum 8192 x 8192 LVDS connected 1366x768+0+0 (normal left inverted right x axis y axis) 344mm x 193mm 1366x768 59.6*+ 1280x720 59.9 1152x768 59.8 1024x768 60.0 59.9 800x600 60.3 59.9 56.2 640x480 59.9 VGA-0 disconnected (normal left inverted right x axis y axis) HDMI-0 connected 1280x720+0+0 (normal left inverted right x axis y axis) 708mm x 398mm 1280x720 60.0*+ 59.7 1360x768 59.8 1024x768 60.0 800x600 60.3 720x480 59.9 640x480 60.0 -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug.

1 3

[PATCH] drm/radeon/kms/evergreen: add some additional safe regs
by Alex Deucher 21 Oct '10

21 Oct '10

These are needed for enabling dynamic GPR allocation in the shaders in the userspace acceleration drivers. Signed-off-by: Alex Deucher <alexdeucher(a)gmail.com> --- drivers/gpu/drm/radeon/radeon_drv.c | 2 +- drivers/gpu/drm/radeon/reg_srcs/evergreen | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index f9e2286..c20669b 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -47,7 +47,7 @@ * - 2.4.0 - add crtc id query * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) - * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change) + * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs */ #define KMS_DRIVER_MAJOR 2 #define KMS_DRIVER_MINOR 7 diff --git a/drivers/gpu/drm/radeon/reg_srcs/evergreen b/drivers/gpu/drm/radeon/reg_srcs/evergreen index f78fd59..05a262b 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/evergreen +++ b/drivers/gpu/drm/radeon/reg_srcs/evergreen @@ -22,6 +22,10 @@ evergreen 0x9400 0x00008B10 PA_SC_LINE_STIPPLE_STATE 0x00008BF0 PA_SC_ENHANCE 0x00008D8C SQ_DYN_GPR_CNTL_PS_FLUSH_REQ +0x00008D90 SQ_DYN_GPR_OPIMIZATION +0x00008D94 SQ_DYN_GPR_SIMD_LOCK_EN +0x00008D98 SQ_DYN_GPR_THREAD_LIMIT +0x00008D9C SQ_DYN_GPR_LDS_LIMIT 0x00008C00 SQ_CONFIG 0x00008C04 SQ_GPR_RESOURCE_MGMT_1 0x00008C08 SQ_GPR_RESOURCE_MGMT_2 @@ -34,6 +38,10 @@ evergreen 0x9400 0x00008C24 SQ_STACK_RESOURCE_MGMT_2 0x00008C28 SQ_STACK_RESOURCE_MGMT_3 0x00008DF8 SQ_CONST_MEM_BASE +0x00008E20 SQ_STATIC_THREAD_MGMT_1 +0x00008E24 SQ_STATIC_THREAD_MGMT_2 +0x00008E28 SQ_STATIC_THREAD_MGMT_3 +0x00008E2C SQ_LDS_RESOURCE_MGMT 0x00008E48 SQ_EX_ALLOC_TABLE_SLOTS 0x00009100 SPI_CONFIG_CNTL 0x0000913C SPI_CONFIG_CNTL_1 -- 1.7.1.1

1 1

[PATCH] drm/radeon/kms/evergreen: set the clear state to the blit state
by Alex Deucher 21 Oct '10

21 Oct '10

The hw stores a default clear state for registers in the context range that can be initialized when the CP is set up. Set the blit state as the default clear state and use the CLEAR_STATE packet to load the blit state rather than loading it from an IB. This reduces overhead when doing bo moves using the 3D engine. Signed-off-by: Alex Deucher <alexdeucher(a)gmail.com> --- drivers/gpu/drm/radeon/evergreen.c | 38 ++++++++++++--- drivers/gpu/drm/radeon/evergreen_blit_kms.c | 60 +++++++++++------------ drivers/gpu/drm/radeon/evergreen_blit_shaders.c | 19 ++------ drivers/gpu/drm/radeon/evergreend.h | 2 + 4 files changed, 65 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 541ae39..2cee695 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -32,6 +32,7 @@ #include "atom.h" #include "avivod.h" #include "evergreen_reg.h" +#include "evergreen_blit_shaders.h" #define EVERGREEN_PFP_UCODE_SIZE 1120 #define EVERGREEN_PM4_UCODE_SIZE 1376 @@ -677,7 +678,7 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev) static int evergreen_cp_start(struct radeon_device *rdev) { - int r; + int r, i; uint32_t cp_me; r = radeon_ring_lock(rdev, 7); @@ -697,16 +698,39 @@ static int evergreen_cp_start(struct radeon_device *rdev) cp_me = 0xff; WREG32(CP_ME_CNTL, cp_me); - r = radeon_ring_lock(rdev, 4); + r = radeon_ring_lock(rdev, evergreen_default_size + 15); if (r) { DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); return r; } - /* init some VGT regs */ - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); - radeon_ring_write(rdev, (VGT_VERTEX_REUSE_BLOCK_CNTL - PACKET3_SET_CONTEXT_REG_START) >> 2); - radeon_ring_write(rdev, 0xe); - radeon_ring_write(rdev, 0x10); + + /* setup clear context state */ + radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); + + for (i = 0; i < evergreen_default_size; i++) + radeon_ring_write(rdev, evergreen_default_state[i]); + + radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); + + /* set clear context state */ + radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); + radeon_ring_write(rdev, 0); + + /* SQ_VTX_BASE_VTX_LOC */ + radeon_ring_write(rdev, 0xc0026f00); + radeon_ring_write(rdev, 0x00000000); + radeon_ring_write(rdev, 0x00000000); + radeon_ring_write(rdev, 0x00000000); + + /* Clear consts */ + radeon_ring_write(rdev, 0xc0036f00); + radeon_ring_write(rdev, 0x00000bc4); + radeon_ring_write(rdev, 0xffffffff); + radeon_ring_write(rdev, 0xffffffff); + radeon_ring_write(rdev, 0xffffffff); + radeon_ring_unlock_commit(rdev); return 0; diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c index 2eeb29d..ac3b6dd 100644 --- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c +++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c @@ -230,7 +230,7 @@ draw_auto(struct radeon_device *rdev) } -/* emits 20 */ +/* emits 30 */ static void set_default_state(struct radeon_device *rdev) { @@ -243,8 +243,6 @@ set_default_state(struct radeon_device *rdev) int num_hs_threads, num_ls_threads; int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; int num_hs_stack_entries, num_ls_stack_entries; - u64 gpu_addr; - int dwords; switch (rdev->family) { case CHIP_CEDAR: @@ -369,13 +367,9 @@ set_default_state(struct radeon_device *rdev) sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) | NUM_LS_STACK_ENTRIES(num_ls_stack_entries)); - /* emit an IB pointing at default state */ - dwords = ALIGN(rdev->r600_blit.state_len, 0x10); - gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; - radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); - radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); - radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); - radeon_ring_write(rdev, dwords); + /* set clear context state */ + radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); + radeon_ring_write(rdev, 0); /* disable dyn gprs */ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); @@ -396,6 +390,25 @@ set_default_state(struct radeon_device *rdev) radeon_ring_write(rdev, sq_stack_resource_mgmt_1); radeon_ring_write(rdev, sq_stack_resource_mgmt_2); radeon_ring_write(rdev, sq_stack_resource_mgmt_3); + + /* CONTEXT_CONTROL */ + radeon_ring_write(rdev, 0xc0012800); + radeon_ring_write(rdev, 0x80000000); + radeon_ring_write(rdev, 0x80000000); + + /* SQ_VTX_BASE_VTX_LOC */ + radeon_ring_write(rdev, 0xc0026f00); + radeon_ring_write(rdev, 0x00000000); + radeon_ring_write(rdev, 0x00000000); + radeon_ring_write(rdev, 0x00000000); + + /* SET_SAMPLER */ + radeon_ring_write(rdev, 0xc0036e00); + radeon_ring_write(rdev, 0x00000000); + radeon_ring_write(rdev, 0x00000012); + radeon_ring_write(rdev, 0x00000000); + radeon_ring_write(rdev, 0x00000000); + } static inline uint32_t i2f(uint32_t input) @@ -426,10 +439,8 @@ static inline uint32_t i2f(uint32_t input) int evergreen_blit_init(struct radeon_device *rdev) { u32 obj_size; - int r, dwords; + int r; void *ptr; - u32 packet2s[16]; - int num_packet2s = 0; /* pin copy shader into vram if already initialized */ if (rdev->r600_blit.shader_obj) @@ -437,17 +448,8 @@ int evergreen_blit_init(struct radeon_device *rdev) mutex_init(&rdev->r600_blit.mutex); rdev->r600_blit.state_offset = 0; - - rdev->r600_blit.state_len = evergreen_default_size; - - dwords = rdev->r600_blit.state_len; - while (dwords & 0xf) { - packet2s[num_packet2s++] = PACKET2(0); - dwords++; - } - - obj_size = dwords * 4; - obj_size = ALIGN(obj_size, 256); + rdev->r600_blit.state_len = 0; + obj_size = 0; rdev->r600_blit.vs_offset = obj_size; obj_size += evergreen_vs_size * 4; @@ -477,12 +479,6 @@ int evergreen_blit_init(struct radeon_device *rdev) return r; } - memcpy_toio(ptr + rdev->r600_blit.state_offset, - evergreen_default_state, rdev->r600_blit.state_len * 4); - - if (num_packet2s) - memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), - packet2s, num_packet2s * 4); memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4); memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4); radeon_bo_kunmap(rdev->r600_blit.shader_obj); @@ -568,7 +564,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) /* calculate number of loops correctly */ ring_size = num_loops * dwords_per_loop; /* set default + shaders */ - ring_size += 36; /* shaders + def state */ + ring_size += 46; /* shaders + def state */ ring_size += 10; /* fence emit for VB IB */ ring_size += 5; /* done copy */ ring_size += 10; /* fence emit for done copy */ @@ -576,7 +572,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) if (r) return r; - set_default_state(rdev); /* 20 */ + set_default_state(rdev); /* 30 */ set_shaders(rdev); /* 16 */ return 0; } diff --git a/drivers/gpu/drm/radeon/evergreen_blit_shaders.c b/drivers/gpu/drm/radeon/evergreen_blit_shaders.c index 5d50450..ef1d28c 100644 --- a/drivers/gpu/drm/radeon/evergreen_blit_shaders.c +++ b/drivers/gpu/drm/radeon/evergreen_blit_shaders.c @@ -39,10 +39,6 @@ const u32 evergreen_default_state[] = { - 0xc0012800, /* CONTEXT_CONTROL */ - 0x80000000, - 0x80000000, - 0xc0016900, 0x0000023b, 0x00000000, /* SQ_LDS_ALLOC_PS */ @@ -63,17 +59,11 @@ const u32 evergreen_default_state[] = 0x00000000, 0x00000000, - 0xc0026f00, - 0x00000000, - 0x00000000, /* SQ_VTX_BASE_VTX_LOC */ - 0x00000000, - 0xc0026900, 0x00000010, 0x00000000, /* DB_Z_INFO */ 0x00000000, /* DB_STENCIL_INFO */ - 0xc0016900, 0x00000200, 0x00000000, /* DB_DEPTH_CONTROL */ @@ -303,11 +293,10 @@ const u32 evergreen_default_state[] = 0x00000000, /* */ 0x00000000, /* */ - 0xc0036e00, /* SET_SAMPLER */ - 0x00000000, - 0x00000012, - 0x00000000, - 0x00000000, + 0xc0026900, + 0x00000316, + 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ + 0x00000010, /* */ }; const u32 evergreen_vs[] = diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 319aa97..c41b49c 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h @@ -645,6 +645,8 @@ #define PACKET3_EVENT_WRITE_EOP 0x47 #define PACKET3_EVENT_WRITE_EOS 0x48 #define PACKET3_PREAMBLE_CNTL 0x4A +# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) +# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) #define PACKET3_RB_OFFSET 0x4B #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D -- 1.7.1.1

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dri-devel October 2010