dri-devel April 2012

dri-devel@lists.freedesktop.org

119 participants
668 discussions

[PATCH] drm/edid: Adding common CVT inferred modes when monitor allows range limited ones trough EDID.
by Rodrigo Vivi 13 Apr '12

13 Apr '12

There are many bugs open on fd.o regarding missing modes that are supported on Windows and other closed source drivers. >From EDID spec we can (might?) infer modes using GTF and CVT when monitor allows it trough range limited flag... obviously limiting by the range. >From our code: * EDID spec says modes should be preferred in this order: * - preferred detailed mode * - other detailed modes from base block * - detailed modes from extension blocks * - CVT 3-byte code modes * - standard timing codes * - established timing codes * - modes inferred from GTF or CVT range information * * We get this pretty much right. Not actually so right... We were inferring just using GTF... not CVT or even GTF2. This patch not just add some common cvt modes but also allows some modes been inferred when using gtf2 as well. Cheers, Rodrigo. >From 4b7a88d0d812583d850ca691d1ac491355230d11 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi <rodrigo.vivi(a)intel.com> Date: Wed, 11 Apr 2012 15:36:31 -0300 Subject: [PATCH] drm/edid: Adding common CVT inferred modes when monitor allows range limited ones trough EDID. Signed-off-by: Rodrigo Vivi <rodrigo.vivi(a)intel.com> --- drivers/gpu/drm/drm_edid.c | 37 +++++++++++++- drivers/gpu/drm/drm_edid_modes.h | 101 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 136 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 7ee7be1..3179572 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1020,17 +1020,50 @@ drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, return modes; } +static int +drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, + struct detailed_timing *timing) +{ + int i, modes = 0; + struct drm_display_mode *newmode; + struct drm_device *dev = connector->dev; + + for (i = 0; i < drm_num_cvt_inferred_modes; i++) { + if (mode_in_range(drm_cvt_inferred_modes + i, edid, timing)) { + newmode = drm_mode_duplicate(dev, &drm_cvt_inferred_modes[i]); + if (newmode) { + drm_mode_probed_add(connector, newmode); + modes++; + } + } + } + + return modes; +} + static void do_inferred_modes(struct detailed_timing *timing, void *c) { struct detailed_mode_closure *closure = c; struct detailed_non_pixel *data = &timing->data.other_data; - int gtf = (closure->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF); + int timing_level = standard_timing_level(closure->edid); - if (gtf && data->type == EDID_DETAIL_MONITOR_RANGE) + if (data->type == EDID_DETAIL_MONITOR_RANGE) + switch (timing_level) { + case LEVEL_DMT: + break; + case LEVEL_GTF: + case LEVEL_GTF2: closure->modes += drm_gtf_modes_for_range(closure->connector, closure->edid, timing); + break; + case LEVEL_CVT: + closure->modes += drm_cvt_modes_for_range(closure->connector, + closure->edid, + timing); + break; + } } static int diff --git a/drivers/gpu/drm/drm_edid_modes.h b/drivers/gpu/drm/drm_edid_modes.h index a91ffb1..7e14a32 100644 --- a/drivers/gpu/drm/drm_edid_modes.h +++ b/drivers/gpu/drm/drm_edid_modes.h @@ -266,6 +266,107 @@ static const struct drm_display_mode drm_dmt_modes[] = { static const int drm_num_dmt_modes = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); +static const struct drm_display_mode drm_cvt_inferred_modes[] = { + /* 640x480@60Hz */ + { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 23750 640, 664, + 720, 800, 0, 480, 483, 487, 500, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 800x600@60Hz */ + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 38250, 800, 832, + 912, 1024, 0, 600, 603, 607, 624, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 900x600@60Hz */ + { DRM_MODE("900x600", DRM_MODE_TYPE_DRIVER, 45250, 960, 992, + 1088, 1216, 0, 600, 603, 609, 624, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1024x576@60Hz */ + { DRM_MODE("1024x576", DRM_MODE_TYPE_DRIVER, 46500, 1024, 1064, + 1160, 1296, 0, 576, 579, 584, 599, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1024x768@60Hz */ + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 63500, 1024, 1072, + 1176, 1328, 0, 768, 771, 775, 798, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1152x864@60Hz */ + { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 81750, 1152, 1216, + 1336, 1520, 0, 864, 867, 871, 897, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1280x720@60Hz */ + { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74500, 1280, 1344, + 1472, 1664, 0, 720, 723, 728, 748, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1280x768@60Hz */ + { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, + 1472, 1664, 0, 768, 771, 781, 798, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1280x800@60Hz */ + { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, + 1480, 1680, 0, 800, 803, 809, 831, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1280x1024@60Hz */ + { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 109000, 1280, 1368, + 1496, 1712, 0, 1024, 1027, 1034, 1063, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1360x768@60Hz */ + { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 84750, 1360, 1432, + 1568, 1776, 0, 768, 771, 781, 798, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1366x768@60Hz */ + { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85250, 1368, 1440, + 1576, 1784, 0, 768, 771, 781, 798, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1440x900@60Hz */ + { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1528, + 1672, 1904, 0, 900, 903, 909, 934, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1400x1050@60Hz */ + { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, + 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1600x900@60Hz */ + { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 118250, 1600, 1696, + 1856, 2112, 0, 900, 903, 908, 934, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1600x1200@60Hz */ + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 161000, 1600, 1712, + 1880, 2160, 0, 1200, 1203, 1207, 1245, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1680x945@60Hz */ + { DRM_MODE("1680x945", DRM_MODE_TYPE_DRIVER, 130750, 1680, 1776, + 1952, 2224, 0, 945, 948, 953, 981, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1680x1050@60Hz */ + { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, + 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1920x1080@60Hz */ + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 73000, 1920, 2048, + 2248, 2576, 0, 1080, 1083, 1088, 1120, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1920x1200@60Hz */ + { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, + 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1920x1440@60Hz */ + { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 233500, 1920, 2064, + 2264, 2608, 0, 1440, 1443, 1447, 1493, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 2048x1152@60Hz */ + { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 197000, 2048, 2184, + 2400, 2752, 0, 1152, 1155, 1160, 1195, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 2048x1536@60Hz */ + { DRM_MODE("2048x1536", DRM_MODE_TYPE_DRIVER, 272000, 2048, 2208, + 2424, 2800, 0, 1563, 1566, 1576, 1620, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 2560x1600@60Hz */ + { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2760, + 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, +}; +static const int drm_num_cvt_inferred_modes = + sizeof(drm_cvt_inferred_modes) / sizeof(struct drm_display_mode); + static const struct drm_display_mode edid_est_modes[] = { { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 968, 1056, 0, 600, 601, 605, 628, 0, -- 1.7.7.6

6 17

[PATCH] drm/radeon: disable MSI on RV515
by Dave Airlie 13 Apr '12

13 Apr '12

From: Dave Airlie <airlied(a)redhat.com> My rv515 card is very flaky with msi enabled. Every so often it loses a rearm and never comes back, manually banging the rearm brings it back. Signed-off-by: Dave Airlie <airlied(a)redhat.com> --- drivers/gpu/drm/radeon/radeon_irq_kms.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c index 66d5fe1..65060b7 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -147,6 +147,12 @@ static bool radeon_msi_ok(struct radeon_device *rdev) (rdev->pdev->subsystem_device == 0x01fd)) return true; + /* RV515 seems to have MSI issues where it loses + * MSI rearms occasionally. This leads to lockups and freezes. + * disable it by default. + */ + if (rdev->family == CHIP_RV515) + return false; if (rdev->flags & RADEON_IS_IGP) { /* APUs work fine with MSIs */ if (rdev->family >= CHIP_PALM) -- 1.7.7.6

2 1

[PATCH] drm/radeon/si: add missing radeon_bo_unreserve in si_rlc_init()
by alexdeucher＠gmail.com 13 Apr '12

13 Apr '12

From: Alex Deucher <alexander.deucher(a)amd.com> Forget to unreserve after pinning. This can lead to problems in soft reset and resume. Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> --- drivers/gpu/drm/radeon/si.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index ac7a199..23a114c 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -3005,6 +3005,7 @@ int si_rlc_init(struct radeon_device *rdev) si_rlc_fini(rdev); return r; } + radeon_bo_unreserve(rdev->rlc.save_restore_obj); /* clear state block */ if (rdev->rlc.clear_state_obj == NULL) { @@ -3024,12 +3025,12 @@ int si_rlc_init(struct radeon_device *rdev) r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, &rdev->rlc.clear_state_gpu_addr); if (r) { - radeon_bo_unreserve(rdev->rlc.clear_state_obj); dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); si_rlc_fini(rdev); return r; } + radeon_bo_unreserve(rdev->rlc.clear_state_obj); return 0; } -- 1.7.7.5

2 2

[PATCH 1/2] drm/i915/intel_i2c: handle zero-length reads
by Daniel Kurtz 13 Apr '12

13 Apr '12

A common method of probing an i2c bus is trying to do a zero-length read. Handle this case by checking the length first waiting for data to be read. This is actually important, since attempting a zero-length read is one of the ways that i2cdetect and i2c_new_probed_device detect whether there is device present on the bus with a given address. Signed-off-by: Daniel Kurtz <djkurtz(a)chromium.org> --- drivers/gpu/drm/i915/intel_i2c.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index cab879f..e249160 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -217,7 +217,7 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, (len << GMBUS_BYTE_COUNT_SHIFT) | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); - do { + while (len) { int ret; u32 val, loop = 0; u32 gmbus2; @@ -235,7 +235,7 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, *buf++ = val & 0xff; val >>= 8; } while (--len && ++loop < 4); - } while (len); + } return 0; } -- 1.7.7.3

3 4

[PATCH 0/8 v7] fix gmbus writes and related issues
by Daniel Kurtz 13 Apr '12

13 Apr '12

This patchset addresses a couple of issues with the i915 gmbus implementation. v7 adds a final patch to switch to using DRM_ERROR for reporting timeouts. Daniel Kurtz (8): drm/i915/intel_i2c: handle zero-length writes drm/i915/intel_i2c: use double-buffered writes drm/i915/intel_i2c: always wait for IDLE before clearing NAK drm/i915/intel_i2c: use WAIT cycle, not STOP drm/i915/intel_i2c: use INDEX cycles for i2c read transactions drm/i915/intel_i2c: reuse GMBUS2 value read in polling loop drm/i915/intel_i2c: remove POSTING_READ() from gmbus transfers drm/i915/intel_i2c: use DRM_ERROR on timeouts drivers/gpu/drm/i915/intel_i2c.c | 163 +++++++++++++++++++++++++++---------- 1 files changed, 119 insertions(+), 44 deletions(-) -- 1.7.7.3

3 22

[PATCH] nouveau: Set special lane map for the right chipset
by Henrik Rydberg 12 Apr '12

12 Apr '12

The refactoring of the nv50 logic, introduced in 8663bc7c, modified the test for the special lane map used on some Apple computers with Nvidia chipsets. The tested MBA3,1 would still boot, but resume from suspend stopped working. This patch restores the old test, which fixes the problem. Signed-off-by: Henrik Rydberg <rydberg(a)euromail.se> --- Hi Dave, This patch fixes a regression in 3.4, tested against -rc2. Resending for your convenience, in case it got lost. Thanks, Henrik drivers/gpu/drm/nouveau/nv50_sor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c index a7844ab..2746402 100644 --- a/drivers/gpu/drm/nouveau/nv50_sor.c +++ b/drivers/gpu/drm/nouveau/nv50_sor.c @@ -42,7 +42,7 @@ nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane) struct drm_nouveau_private *dev_priv = dev->dev_private; static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */ static const u8 nv50[] = { 16, 8, 0, 24 }; - if (dev_priv->card_type == 0xaf) + if (dev_priv->chipset == 0xaf) return nvaf[lane]; return nv50[lane]; } -- 1.7.9.5

1 0

[RFC v2] libdrm part of the render-node patch series
by Ilija Hadzic 12 Apr '12

12 Apr '12

The following two patches are the rework of the patch series sent two weeks ago [1] that add libdrm support for render node manipulation. All notes described in [1] apply. A new option to render_node_add utility has been added to specify the number of planes and plane IDs are supposed to be the last in the ID list. Regards, -- Ilija ---- [1] http://lists.freedesktop.org/archives/dri-devel/2012-March/020782.html

1 2

[git pull] drm fixes
by Dave Airlie 12 Apr '12

12 Apr '12

Hi Linus, mostly exynos and intel, intel has 3 regression fixers (more info in intel merge commit), along with some other make hw work fixes, exynos has some cleanups and an ioctl fix couple of radeon fixes, couple of build fixes, and a savage userspace interface possible overflow fix. Dave. The following changes since commit 258f742635360175564e9470eb060ff4d4b984e7: modpost: Fix modpost license checking of vmlinux.o (2012-04-09 20:52:56 -0700) are available in the git repository at: git://people.freedesktop.org/~airlied/linux drm-fixes Alex Deucher (2): drm/radeon/kms: fix DVO setup on some r4xx chips drm/radeon: only add the mm i2c bus if the hw_i2c module param is set Arnd Bergmann (1): drm/radeon: replace udelay with mdelay for long timeouts Chris Wilson (2): drm/i915: Finish any pending operations on the framebuffer before disabling drm/i915/ringbuffer: Exclude last 2 cachlines of ring on 845g Daniel Vetter (4): drm/i915: properly compute dp dithering for user-created modes Revert "drm/i915: reenable gmbus on gen3+ again" drm/i915: implement ColorBlt w/a drm/i915: clear fencing tracking state when retiring requests Dave Airlie (2): Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-intel-fixes Merge branch 'exynos-drm-fixes' of git://git.infradead.org/users/kmpark/linux-samsung into drm-intel-fixes Inki Dae (3): drm/exynos: fixed page align and code clean. drm/exynos: fixed duplicated page allocation bug. drm/exynos: fixed exynos broken ioctl Jesse Barnes (1): drm/i915: make rc6 module parameter read-only Joonyoung Shim (6): drm/exynos: remove unnecessary type conversion of hdmi and mixer drm/exynos: remove unused codes in hdmi and mixer drm/exynos: rename s/HDMI_OVERLAY_NUMBER/MIXER_WIN_NR drm/exynos: use define instead of default_win member in struct mixer_context drm/exynos: fix struct for operation callback functions to driver name drm/exynos: fix to pointer manager member of struct exynos_drm_subdrv Randy Dunlap (1): vgaarb.h: fix build warnings Seung-Woo Kim (1): drm/exynos: add format list of plane Xi Wang (1): drm/savage: fix integer overflows in savage_bci_cmdbuf() acreese (1): drm/i915: Removed IVB forced enable of sprite dest key. drivers/gpu/drm/exynos/exynos_drm_buf.c | 47 +++------- drivers/gpu/drm/exynos/exynos_drm_core.c | 14 ++-- drivers/gpu/drm/exynos/exynos_drm_drv.h | 10 +- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 20 +++-- drivers/gpu/drm/exynos/exynos_drm_gem.c | 45 ++++++++-- drivers/gpu/drm/exynos/exynos_drm_gem.h | 2 + drivers/gpu/drm/exynos/exynos_drm_hdmi.c | 107 ++++++++++------------- drivers/gpu/drm/exynos/exynos_drm_hdmi.h | 23 ++--- drivers/gpu/drm/exynos/exynos_drm_plane.c | 4 + drivers/gpu/drm/exynos/exynos_drm_vidi.c | 20 +++-- drivers/gpu/drm/exynos/exynos_hdmi.c | 42 ++++----- drivers/gpu/drm/exynos/exynos_mixer.c | 40 ++++----- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_gem.c | 2 + drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_display.c | 69 +++++++++++---- drivers/gpu/drm/i915/intel_dp.c | 49 ++++++++--- drivers/gpu/drm/i915/intel_i2c.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- drivers/gpu/drm/i915/intel_sprite.c | 1 - drivers/gpu/drm/radeon/atombios_encoders.c | 4 + drivers/gpu/drm/radeon/r100.c | 2 +- drivers/gpu/drm/radeon/r600.c | 2 +- drivers/gpu/drm/radeon/r600_cp.c | 6 +- drivers/gpu/drm/radeon/radeon_clocks.c | 24 +++--- drivers/gpu/drm/radeon/radeon_combios.c | 8 +- drivers/gpu/drm/radeon/radeon_i2c.c | 4 + drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 12 ++-- drivers/gpu/drm/savage/savage_state.c | 6 +- include/drm/exynos_drm.h | 5 +- include/linux/vgaarb.h | 2 + 31 files changed, 325 insertions(+), 254 deletions(-)

1 0

[PATCH 1/4] drm/radeon: make radeon_gpu_is_lockup a per ring function
by Christian König 12 Apr '12

12 Apr '12

Different rings have different criteria to test if they are stuck. Signed-off-by: Christian König <deathsimple(a)vodafone.de> --- drivers/gpu/drm/radeon/radeon.h | 4 +- drivers/gpu/drm/radeon/radeon_asic.c | 36 +++++++++++++++++--------------- drivers/gpu/drm/radeon/radeon_fence.c | 2 +- 3 files changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index d2870a0..4ee9a1a 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1128,7 +1128,6 @@ struct radeon_asic { int (*resume)(struct radeon_device *rdev); int (*suspend)(struct radeon_device *rdev); void (*vga_set_state)(struct radeon_device *rdev, bool state); - bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); int (*asic_reset)(struct radeon_device *rdev); /* ioctl hw specific callback. Some hw might want to perform special * operation on specific ioctl. For instance on wait idle some hw @@ -1157,6 +1156,7 @@ struct radeon_asic { void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); + bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); } ring[RADEON_NUM_RINGS]; /* irqs */ struct { @@ -1677,7 +1677,6 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) -#define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp)) #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) @@ -1686,6 +1685,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) +#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 479c89e..a99fc2b 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -134,7 +134,6 @@ static struct radeon_asic r100_asic = { .suspend = &r100_suspend, .resume = &r100_resume, .vga_set_state = &r100_vga_set_state, - .gpu_is_lockup = &r100_gpu_is_lockup, .asic_reset = &r100_asic_reset, .ioctl_wait_idle = NULL, .gui_idle = &r100_gui_idle, @@ -152,6 +151,7 @@ static struct radeon_asic r100_asic = { .ring_start = &r100_ring_start, .ring_test = &r100_ring_test, .ib_test = &r100_ib_test, + .is_lockup = &r100_gpu_is_lockup, } }, .irq = { @@ -208,7 +208,6 @@ static struct radeon_asic r200_asic = { .suspend = &r100_suspend, .resume = &r100_resume, .vga_set_state = &r100_vga_set_state, - .gpu_is_lockup = &r100_gpu_is_lockup, .asic_reset = &r100_asic_reset, .ioctl_wait_idle = NULL, .gui_idle = &r100_gui_idle, @@ -226,6 +225,7 @@ static struct radeon_asic r200_asic = { .ring_start = &r100_ring_start, .ring_test = &r100_ring_test, .ib_test = &r100_ib_test, + .is_lockup = &r100_gpu_is_lockup, } }, .irq = { @@ -282,7 +282,6 @@ static struct radeon_asic r300_asic = { .suspend = &r300_suspend, .resume = &r300_resume, .vga_set_state = &r100_vga_set_state, - .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &r300_asic_reset, .ioctl_wait_idle = NULL, .gui_idle = &r100_gui_idle, @@ -300,6 +299,7 @@ static struct radeon_asic r300_asic = { .ring_start = &r300_ring_start, .ring_test = &r100_ring_test, .ib_test = &r100_ib_test, + .is_lockup = &r300_gpu_is_lockup, } }, .irq = { @@ -356,7 +356,6 @@ static struct radeon_asic r300_asic_pcie = { .suspend = &r300_suspend, .resume = &r300_resume, .vga_set_state = &r100_vga_set_state, - .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &r300_asic_reset, .ioctl_wait_idle = NULL, .gui_idle = &r100_gui_idle, @@ -374,6 +373,7 @@ static struct radeon_asic r300_asic_pcie = { .ring_start = &r300_ring_start, .ring_test = &r100_ring_test, .ib_test = &r100_ib_test, + .is_lockup = &r300_gpu_is_lockup, } }, .irq = { @@ -430,7 +430,6 @@ static struct radeon_asic r420_asic = { .suspend = &r420_suspend, .resume = &r420_resume, .vga_set_state = &r100_vga_set_state, - .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &r300_asic_reset, .ioctl_wait_idle = NULL, .gui_idle = &r100_gui_idle, @@ -448,6 +447,7 @@ static struct radeon_asic r420_asic = { .ring_start = &r300_ring_start, .ring_test = &r100_ring_test, .ib_test = &r100_ib_test, + .is_lockup = &r300_gpu_is_lockup, } }, .irq = { @@ -504,7 +504,6 @@ static struct radeon_asic rs400_asic = { .suspend = &rs400_suspend, .resume = &rs400_resume, .vga_set_state = &r100_vga_set_state, - .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &r300_asic_reset, .ioctl_wait_idle = NULL, .gui_idle = &r100_gui_idle, @@ -522,6 +521,7 @@ static struct radeon_asic rs400_asic = { .ring_start = &r300_ring_start, .ring_test = &r100_ring_test, .ib_test = &r100_ib_test, + .is_lockup = &r300_gpu_is_lockup, } }, .irq = { @@ -578,7 +578,6 @@ static struct radeon_asic rs600_asic = { .suspend = &rs600_suspend, .resume = &rs600_resume, .vga_set_state = &r100_vga_set_state, - .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &rs600_asic_reset, .ioctl_wait_idle = NULL, .gui_idle = &r100_gui_idle, @@ -596,6 +595,7 @@ static struct radeon_asic rs600_asic = { .ring_start = &r300_ring_start, .ring_test = &r100_ring_test, .ib_test = &r100_ib_test, + .is_lockup = &r300_gpu_is_lockup, } }, .irq = { @@ -652,7 +652,6 @@ static struct radeon_asic rs690_asic = { .suspend = &rs690_suspend, .resume = &rs690_resume, .vga_set_state = &r100_vga_set_state, - .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &rs600_asic_reset, .ioctl_wait_idle = NULL, .gui_idle = &r100_gui_idle, @@ -670,6 +669,7 @@ static struct radeon_asic rs690_asic = { .ring_start = &r300_ring_start, .ring_test = &r100_ring_test, .ib_test = &r100_ib_test, + .is_lockup = &r300_gpu_is_lockup, } }, .irq = { @@ -726,7 +726,6 @@ static struct radeon_asic rv515_asic = { .suspend = &rv515_suspend, .resume = &rv515_resume, .vga_set_state = &r100_vga_set_state, - .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &rs600_asic_reset, .ioctl_wait_idle = NULL, .gui_idle = &r100_gui_idle, @@ -744,6 +743,7 @@ static struct radeon_asic rv515_asic = { .ring_start = &rv515_ring_start, .ring_test = &r100_ring_test, .ib_test = &r100_ib_test, + .is_lockup = &r300_gpu_is_lockup, } }, .irq = { @@ -800,7 +800,6 @@ static struct radeon_asic r520_asic = { .suspend = &rv515_suspend, .resume = &r520_resume, .vga_set_state = &r100_vga_set_state, - .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &rs600_asic_reset, .ioctl_wait_idle = NULL, .gui_idle = &r100_gui_idle, @@ -818,6 +817,7 @@ static struct radeon_asic r520_asic = { .ring_start = &rv515_ring_start, .ring_test = &r100_ring_test, .ib_test = &r100_ib_test, + .is_lockup = &r300_gpu_is_lockup, } }, .irq = { @@ -874,7 +874,6 @@ static struct radeon_asic r600_asic = { .suspend = &r600_suspend, .resume = &r600_resume, .vga_set_state = &r600_vga_set_state, - .gpu_is_lockup = &r600_gpu_is_lockup, .asic_reset = &r600_asic_reset, .ioctl_wait_idle = r600_ioctl_wait_idle, .gui_idle = &r600_gui_idle, @@ -891,6 +890,7 @@ static struct radeon_asic r600_asic = { .cs_parse = &r600_cs_parse, .ring_test = &r600_ring_test, .ib_test = &r600_ib_test, + .is_lockup = &r600_gpu_is_lockup, } }, .irq = { @@ -946,7 +946,6 @@ static struct radeon_asic rs780_asic = { .fini = &r600_fini, .suspend = &r600_suspend, .resume = &r600_resume, - .gpu_is_lockup = &r600_gpu_is_lockup, .vga_set_state = &r600_vga_set_state, .asic_reset = &r600_asic_reset, .ioctl_wait_idle = r600_ioctl_wait_idle, @@ -964,6 +963,7 @@ static struct radeon_asic rs780_asic = { .cs_parse = &r600_cs_parse, .ring_test = &r600_ring_test, .ib_test = &r600_ib_test, + .is_lockup = &r600_gpu_is_lockup, } }, .irq = { @@ -1020,7 +1020,6 @@ static struct radeon_asic rv770_asic = { .suspend = &rv770_suspend, .resume = &rv770_resume, .asic_reset = &r600_asic_reset, - .gpu_is_lockup = &r600_gpu_is_lockup, .vga_set_state = &r600_vga_set_state, .ioctl_wait_idle = r600_ioctl_wait_idle, .gui_idle = &r600_gui_idle, @@ -1037,6 +1036,7 @@ static struct radeon_asic rv770_asic = { .cs_parse = &r600_cs_parse, .ring_test = &r600_ring_test, .ib_test = &r600_ib_test, + .is_lockup = &r600_gpu_is_lockup, } }, .irq = { @@ -1092,7 +1092,6 @@ static struct radeon_asic evergreen_asic = { .fini = &evergreen_fini, .suspend = &evergreen_suspend, .resume = &evergreen_resume, - .gpu_is_lockup = &evergreen_gpu_is_lockup, .asic_reset = &evergreen_asic_reset, .vga_set_state = &r600_vga_set_state, .ioctl_wait_idle = r600_ioctl_wait_idle, @@ -1110,6 +1109,7 @@ static struct radeon_asic evergreen_asic = { .cs_parse = &evergreen_cs_parse, .ring_test = &r600_ring_test, .ib_test = &r600_ib_test, + .is_lockup = &evergreen_gpu_is_lockup, } }, .irq = { @@ -1165,7 +1165,6 @@ static struct radeon_asic sumo_asic = { .fini = &evergreen_fini, .suspend = &evergreen_suspend, .resume = &evergreen_resume, - .gpu_is_lockup = &evergreen_gpu_is_lockup, .asic_reset = &evergreen_asic_reset, .vga_set_state = &r600_vga_set_state, .ioctl_wait_idle = r600_ioctl_wait_idle, @@ -1183,6 +1182,7 @@ static struct radeon_asic sumo_asic = { .cs_parse = &evergreen_cs_parse, .ring_test = &r600_ring_test, .ib_test = &r600_ib_test, + .is_lockup = &evergreen_gpu_is_lockup, }, }, .irq = { @@ -1238,7 +1238,6 @@ static struct radeon_asic btc_asic = { .fini = &evergreen_fini, .suspend = &evergreen_suspend, .resume = &evergreen_resume, - .gpu_is_lockup = &evergreen_gpu_is_lockup, .asic_reset = &evergreen_asic_reset, .vga_set_state = &r600_vga_set_state, .ioctl_wait_idle = r600_ioctl_wait_idle, @@ -1256,6 +1255,7 @@ static struct radeon_asic btc_asic = { .cs_parse = &evergreen_cs_parse, .ring_test = &r600_ring_test, .ib_test = &r600_ib_test, + .is_lockup = &evergreen_gpu_is_lockup, } }, .irq = { @@ -1321,7 +1321,6 @@ static struct radeon_asic cayman_asic = { .fini = &cayman_fini, .suspend = &cayman_suspend, .resume = &cayman_resume, - .gpu_is_lockup = &cayman_gpu_is_lockup, .asic_reset = &cayman_asic_reset, .vga_set_state = &r600_vga_set_state, .ioctl_wait_idle = r600_ioctl_wait_idle, @@ -1340,6 +1339,7 @@ static struct radeon_asic cayman_asic = { .cs_parse = &evergreen_cs_parse, .ring_test = &r600_ring_test, .ib_test = &r600_ib_test, + .is_lockup = &cayman_gpu_is_lockup, }, [CAYMAN_RING_TYPE_CP1_INDEX] = { .ib_execute = &cayman_ring_ib_execute, @@ -1349,6 +1349,7 @@ static struct radeon_asic cayman_asic = { .cs_parse = &evergreen_cs_parse, .ring_test = &r600_ring_test, .ib_test = &r600_ib_test, + .is_lockup = &cayman_gpu_is_lockup, }, [CAYMAN_RING_TYPE_CP2_INDEX] = { .ib_execute = &cayman_ring_ib_execute, @@ -1358,6 +1359,7 @@ static struct radeon_asic cayman_asic = { .cs_parse = &evergreen_cs_parse, .ring_test = &r600_ring_test, .ib_test = &r600_ib_test, + .is_lockup = &cayman_gpu_is_lockup, } }, .irq = { diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c index 4bd36a3..66b2229 100644 --- a/drivers/gpu/drm/radeon/radeon_fence.c +++ b/drivers/gpu/drm/radeon/radeon_fence.c @@ -259,7 +259,7 @@ retry: * if we experiencing a lockup the value doesn't change */ if (seq == rdev->fence_drv[fence->ring].last_seq && - radeon_gpu_is_lockup(rdev, &rdev->ring[fence->ring])) { + radeon_ring_is_lockup(rdev, fence->ring, &rdev->ring[fence->ring])) { /* good news we believe it's a lockup */ printk(KERN_WARNING "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n", fence->seq, seq); -- 1.7.5.4

2 4

Fwd: [pull] drm-intel-next for 3.5
by Daniel Vetter 12 Apr '12

12 Apr '12

Forwarding the pull request to Dave to intel-gfx and dri-devel, I've fumbled the cc list on the original mail. -Daniel ---------- Forwarded message ---------- From: Daniel Vetter <daniel(a)ffwll.ch> Date: Thu, Apr 12, 2012 at 11:17 Subject: [pull] drm-intel-next for 3.5 To: Dave Airlie <airlied(a)gmail.com> Hi Dave First pull request for 3.5-next, slightly large than usual because new things kept coming in since the last pull for 3.4. Highlights: - first batch of hw enablement for vlv (Jesse et al) and hsw (Eugeni). pci ids are not yet added, and there's still quite a few patches to merge (mostly modesetting). To make QA easier I've decided to merge this stuff in pieces. - loads of cleanups and prep patches spurred by the above. Especially vlv is a real frankenstein chip, but also hsw is stretching our driver's code design. Expect more to come in this area for 3.5. - more gmbus fixes, cleanups and improvements by Daniel Kurtz. Again, there are more patches needed (and some already queued up), but I wanted to split this a bit for better testing. - pwrite/pread rework and retuning. This series has been in the works for a few months already and a lot of i-g-t tests have been created for it. Now it's finally ready to be merged. Note that one patch in this series touches include/pagemap.h, that patch is acked-by akpm. - reduce mappable pressure and relocation throughput improvements from Chris. - mmap offset exhaustion mitigation by Chris Wilson. - a start at figuring out which codepaths in our messy dri1/ums+gem/kms driver we actually need to support by bailing out of unsupported case. The driver now refuses to load without kms on gen6+ and disallows a few ioctls that userspace never used in certain cases. More of this will definitely come. - More decoupling of global gtt and ppgtt. - Improved dual-link lvds detection by Takashi Iwai. - Shut up the compiler + plus fix the fallout (Ben) - Inverted panel brightness handling (mostly Acer manages to break things in this way). - Small fixlets and adjustements and some minor things to help debugging. Regression-wise QA reported quite a few issues on ivb, but all of them turned out to be hw stability issues which are already fixed in drm-intel-fixes (QA runs the nightly regression tests on -next alone, without -fixes automatically merged in). There's still one issue open on snb, it looks like occlusion query writes are not quite as cache coherent as we've expected. With some of the pwrite adjustements we can now reliably hit this. Kernel workaround for it is in the works. QA (and myself) also had some fun with resume regressions introduced by upstream 3.4-rc1, but they all seem to be fixed in -rc2. Yours, Daniel The following changes since commit c501ae7f332cdaf42e31af30b72b4b66cbbb1604: drm/i915: Only clear the GPU domains upon a successful finish (2012-03-01 21:36:13 +0100) are available in the git repository at: git://people.freedesktop.org/~danvet/drm-intel tags/drm-intel-next-2012-04-09 for you to fetch changes up to ec34a01de31128e5c08e5f05c47f4a787f45a33c: drm/i915: VCS is not the last ring (2012-04-09 18:04:10 +0200) ---------------------------------------------------------------- Adam Jackson (2): drm/i915: Pull MTRR setup to its own function drm/i915: Don't do MTRR setup if PAT is enabled Ben Widawsky (5): drm/i915: [dinq] shut up two instances -Wunitialized drm/i915: [dinq] shut up six instances of -Warray-bounds drm/i915: ring irq cleanups drm/i915: open code gen6+ ring irqs drm/i915: VCS is not the last ring Carsten Emde (3): drm/i915: panel: invert brightness via parameter drm/i915: panel: invert brightness via quirk drm/i915: panel: invert brightness acer aspire 5734z Chris Wilson (5): drm/i915: Release the mmap offset when purging a buffer drm/i915: Batch copy_from_user for relocation processing drm/i915: Avoid using mappable space for relocation processing through the CPU drm/i915: Initialise GTT MTRR to -1 drm/i915/sdvo: Include YRPB as an additional TV output type Daniel Kurtz (7): drm/i915/intel_i2c: refactor gmbus_xfer drm/i915/intel_i2c: cleanup error messages and comments drm/i915/intel_i2c: assign HDMI port D to pin pair 6 drm/i915/intel_i2c: use i2c pre/post_xfer functions to setup gpio xfers drm/i915/intel_i2c: refactor using intel_gmbus_get_adapter drm/i915/intel_i2c: gmbus disabled and reserved ports are invalid drm/i915/intel_i2c: allocate gmbus array as part of drm_i915_private Daniel Vetter (38): drm/i915: split out dma mapping from global gtt bind/unbind functions drm/i915: bind objects to the global gtt only when needed drm/i915: implement SNB workaround for lazy global gtt drm/i915: enable lazy global-gtt binding drm/i915: add HAS_ALIASING_PPGTT parameter for userspace drm/i915/sdov: switch IS_SDVOB to a flag drm/i915: add an explict mmio base for gpio/gmbus io drm/i915: enable gmbus on gen2 drm/i915: reinstate GM45 TV detection fix drm/i915: s/i915_gem_do_init/i915_gem_init_global_gtt drm/i915: the intel gtt is _not_ an agp bridge! drm/i915: clear the entire gtt when using gem drm/i915: merge shmem_pwrite slow&fast-path drm/i915: merge shmem_pread slow&fast-path drm: add helper to clflush a virtual address range drm/i915: move clflushing into shmem_pread drm/i915: kill ranged cpu read domain support drm/i915: don't use gtt_pwrite on LLC cached objects drm/i915: don't call shmem_read_mapping unnecessarily drm/i915: drop gtt slowpath drm/i915: don't clobber userspace memory before commiting to the pread drm/i915: implement inline clflush for pwrite drm/i915: fall back to shmem pwrite when the buffer is not accessible drm/i915: use uncached writes in pwrite drm/i915: extract copy helpers from shmem_pread|pwrite mm: extend prefault helpers to fault in more than PAGE_SIZE drm/i915: fixup in-line clflushing on bit17 swizzled bos drm/i915: mark pwrite/pread slowpaths with unlikely drm/i915: split LVDS update code out of i9xx_crtc_mode_set drm/i915: split PLL update code out of i9xx_crtc_mode_set drm/i915: rip out old HWSTAM missed irq WA for vlv drm/i915: use render gen to switch ring irq functions drm/i915: extract gt interrupt handler drm/i915: refuse to load on gen6+ without kms drm/i915: disallow gem init ioctl on ilk drm/i915: dump the DMA fetch addr register on pre-gen6 drm/i915: make quirks more verbose drm/i915: Add a dual link lvds quirk for MacBook Pro 8,2 Eugeni Dodonov (19): drm/i915: transform HAS_PCH_SPLIT in a feature check drm/i915: add Haswell devices and their PCI IDs drm/i915: add support for LynxPoint PCH drm/i915: add support for power wells drm/i915: add enumeration for DDI ports drm/i915: add DDI registers drm/i915: add DP_TP_CTL registers drm/i915: add DP_TP_STATUS registers drm/i915: add definitions for DDI_BUF_CTL registers drm/i915: add definition of DDI buffer translations regs drm/i915: add SBI registers drm/i915: add PIXCLK_GATE register drm/i915: add S PLL control drm/i915: add port clock selection support for HSW drm/i915: add SSC offsets for SBI access drm/i915: add LCPLL control registers drm/i915: add WRPLL clocks drm/i915: add WM_LINETIME registers drm/i915: add SFUSE_STRAP registers for digital port detection Gajanan Bhat (1): drm/i915: program drain latency regs on ValleyView Jesse Barnes (14): drm/i915: remove ACPI related DRM_ERRORs drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c drm/i915: re-order GT IIR bit definitions drm/i915: add ValleyView driver structs and IS_VALLEYVIEW macro drm/i915: ValleyView watermark support drm/i915: PLL defines for VLV drm/i915: add DPIO support drm/i915: add ValleyView clock gating init agp/intel: map more registers for use by the GTT code agp/intel: add ValleyView AGP driver drm/i915: add ValleyView specific force wake get/put functions drm/i915: interrupt bit definitions for VLV drm/i915: ValleyView IRQ support drm/i915: check for disabled interrupts on ValleyView Joe Perches (1): i915: Add and use pr_fmt and pr_<level> Mathias Fröhlich (1): i915: Add option to bypass vbt table. Sean Paul (2): drm/i915: Retry reading the PCH FDI receiver ISR drm/i915: Add wait_for in init_ring_common Shobhit Kumar (1): drm/i915: Enable HDMI on ValleyView Takashi Iwai (2): drm/i915: Check VBIOS value for determining LVDS dual channel mode, too drm/i915: Add lvds_channel module option Documentation/kernel-parameters.txt | 14 + drivers/char/agp/intel-agp.c | 1 + drivers/char/agp/intel-agp.h | 14 + drivers/char/agp/intel-gtt.c | 45 ++- drivers/gpu/drm/drm_cache.c | 23 + drivers/gpu/drm/i915/i915_debugfs.c | 91 +++- drivers/gpu/drm/i915/i915_dma.c | 85 ++-- drivers/gpu/drm/i915/i915_drv.c | 88 +++- drivers/gpu/drm/i915/i915_drv.h | 74 ++- drivers/gpu/drm/i915/i915_gem.c | 824 +++++++++++----------------- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 94 +++- drivers/gpu/drm/i915/i915_gem_gtt.c | 69 ++- drivers/gpu/drm/i915/i915_irq.c | 450 +++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 389 +++++++++++++- drivers/gpu/drm/i915/intel_acpi.c | 2 - drivers/gpu/drm/i915/intel_bios.c | 45 ++- drivers/gpu/drm/i915/intel_crt.c | 16 +- drivers/gpu/drm/i915/intel_display.c | 784 ++++++++++++++++++++------- drivers/gpu/drm/i915/intel_drv.h | 17 +- drivers/gpu/drm/i915/intel_dvo.c | 6 +- drivers/gpu/drm/i915/intel_hdmi.c | 46 ++- drivers/gpu/drm/i915/intel_i2c.c | 295 ++++++----- drivers/gpu/drm/i915/intel_lvds.c | 11 +- drivers/gpu/drm/i915/intel_modes.c | 3 +- drivers/gpu/drm/i915/intel_opregion.c | 4 +- drivers/gpu/drm/i915/intel_panel.c | 28 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 92 +--- drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + drivers/gpu/drm/i915/intel_sdvo.c | 51 +- drivers/gpu/drm/i915/intel_tv.c | 9 + include/drm/drmP.h | 1 + include/drm/i915_drm.h | 3 +- include/linux/pagemap.h | 64 +++- 33 files changed, 2602 insertions(+), 1137 deletions(-) -- Daniel Vetter Mail: daniel(a)ffwll.ch Mobile: +41 (0)79 365 57 48 -- Daniel Vetter daniel.vetter(a)ffwll.ch - +41 (0) 79 364 57 48 - http://blog.ffwll.ch

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dri-devel April 2012