This patchset can also be found here, for easier browsing:
https://github.com/freedreno/kernel-msm/commits/ifc6410-drm-rfc1git://github.com/freedreno/kernel-msm.git ifc6410-drm-rfc1
NOTES about msm drm/kms driver:
In the current snapdragon SoC's, we have (at least) 3 different
display controller blocks at play:
+ MDP3 - ?? seems to be what is on geeksphone peak device
+ MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
+ MDSS - snapdragon 800
(I don't have a …
[View More]completely clear picture on which display controller
maps to which part #)
Plus a handful of blocks around them for HDMI/DSI/etc output.
And on gpu side of things:
+ zero, one, or two 2d cores (z180)
+ and either a2xx or a3xx 3d core.
But, HDMI/DSI/etc blocks seem like they can be shared across multiple
display controller blocks. And I for sure don't want to have to deal
with N different kms devices from xf86-video-freedreno. Plus, it
seems like we can do some clever tricks like use GPU to trigger
pageflip after rendering completes (ie. have the kms/crtc code build
up gpu cmdstream to update scanout and write FLUSH register after).
So, the approach is one drm driver, with some modularity. Different
'struct msm_kms' implementations, depending on display controller.
And one or more 'struct msm_gpu' for the various different gpu sub-
modules.
(Second part is not implemented yet. So far this is just basic KMS
driver, and not exposing any custom ioctls to userspace for now.)
The kms module provides the plane, crtc, and encoder objects, and
loads whatever connectors are appropriate.
For MDP4, the mapping is:
plane -> PIPE{RGBn,VGn} \
crtc -> OVLP{n} + DMA{P,S,E} (??) |-> MDP "device"
encoder -> DTV/LCDC/DSI (within MDP4) /
connector -> HDMI/DSI/etc --> other device(s)
Since the irq's that drm core mostly cares about are vblank/framedone,
we'll let msm_mdp4_kms provide the irq install/uninstall/etc functions
and treat the MDP4 block's irq as "the" irq. Even though the connectors
may have their own irqs which they install themselves. For this reason
the display controller is the "master" device.
Each connector probably ends up being a separate device, just for the
logistics of finding/mapping io region, irq, etc. Idealy we would
have a better way than just stashing the platform device in a global
(ie. like DT super-node.. but I don't have any snapdragon hw yet that
is using DT).
Note that so far I've not been able to get any docs on the hw, and it
seems that access to such docs would prevent me from working on the
freedreno gallium driver. So there may be some mistakes in register
names (I had to invent a few, since no sufficient hint was given in
the downstream android fbdev driver), bitfield sizes, etc. My current
state of understanding the registers is given in the envytools rnndb
files at:
https://github.com/freedreno/envytools/tree/master/rnndb
(the mdp4/hdmi/dsi directories)
These files are used both for a parser tool (in the same tree) to
parse logged register reads/writes (both from downstream android fbdev
driver, and this driver with register logging enabled), as well as to
generate the register level headers.
Rob Clark (2):
drm/msm: add register definitions
drm/msm: basic KMS driver for snapdragon
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/msm/Kconfig | 34 +
drivers/gpu/drm/msm/Makefile | 23 +
drivers/gpu/drm/msm/NOTES | 43 ++
drivers/gpu/drm/msm/dsi/dsi.xml.h | 262 +++++++
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h | 156 +++++
drivers/gpu/drm/msm/dsi/sfpb.xml.h | 46 ++
drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 508 ++++++++++++++
drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 528 ++++++++++++++
drivers/gpu/drm/msm/hdmi/hdmi_connector.h | 95 +++
drivers/gpu/drm/msm/hdmi/hdmi_i2c.c | 264 +++++++
drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 140 ++++
drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c | 215 ++++++
drivers/gpu/drm/msm/hdmi/qfprom.xml.h | 50 ++
drivers/gpu/drm/msm/mdp4/mdp4.xml.h | 1001 +++++++++++++++++++++++++++
drivers/gpu/drm/msm/mdp4/mdp4_crtc.c | 440 ++++++++++++
drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c | 306 ++++++++
drivers/gpu/drm/msm/mdp4/mdp4_irq.c | 194 ++++++
drivers/gpu/drm/msm/mdp4/mdp4_kms.c | 359 ++++++++++
drivers/gpu/drm/msm/mdp4/mdp4_kms.h | 161 +++++
drivers/gpu/drm/msm/mdp4/mdp4_plane.c | 241 +++++++
drivers/gpu/drm/msm/msm_connector.c | 34 +
drivers/gpu/drm/msm/msm_connector.h | 68 ++
drivers/gpu/drm/msm/msm_drv.c | 491 +++++++++++++
drivers/gpu/drm/msm/msm_drv.h | 161 +++++
drivers/gpu/drm/msm/msm_fb.c | 216 ++++++
drivers/gpu/drm/msm/msm_fbdev.c | 255 +++++++
drivers/gpu/drm/msm/msm_gem.c | 441 ++++++++++++
29 files changed, 6735 insertions(+)
create mode 100644 drivers/gpu/drm/msm/Kconfig
create mode 100644 drivers/gpu/drm/msm/Makefile
create mode 100644 drivers/gpu/drm/msm/NOTES
create mode 100644 drivers/gpu/drm/msm/dsi/dsi.xml.h
create mode 100644 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
create mode 100644 drivers/gpu/drm/msm/dsi/sfpb.xml.h
create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi.xml.h
create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_connector.c
create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_connector.h
create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c
create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c
create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c
create mode 100644 drivers/gpu/drm/msm/hdmi/qfprom.xml.h
create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4.xml.h
create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_crtc.c
create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c
create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_irq.c
create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_kms.c
create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_kms.h
create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_plane.c
create mode 100644 drivers/gpu/drm/msm/msm_connector.c
create mode 100644 drivers/gpu/drm/msm/msm_connector.h
create mode 100644 drivers/gpu/drm/msm/msm_drv.c
create mode 100644 drivers/gpu/drm/msm/msm_drv.h
create mode 100644 drivers/gpu/drm/msm/msm_fb.c
create mode 100644 drivers/gpu/drm/msm/msm_fbdev.c
create mode 100644 drivers/gpu/drm/msm/msm_gem.c
--
1.8.1.4
[View Less]
https://bugs.freedesktop.org/show_bug.cgi?id=26949
Timothy Arceri <t_arceri(a)yahoo.com.au> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |RESOLVED
Resolution|--- |INVALID
--- Comment #2 from Timothy Arceri <t_arceri(a)yahoo.com.au> ---
Marking as invalid as the old dynamic power code is made obsolete by …
[View More]the new
DPM code coming in the 3.11 kernal.
Also the reporter never retested with a newer kernal after the initial report.
--
You are receiving this mail because:
You are the assignee for the bug.
[View Less]
Driver authors are a forgetful breed, and having to manually clean up
all inodes from debugfs during module unload is tedious and rarely
encountered by users; leftover inodes fester. But behold, the drm core
already tracks all inodes created under the DRI debugfs minor so that we
can do all the teardown ourselves.
Signed-off-by: Chris Wilson <chris(a)chris-wilson.co.uk>
Cc: Dave Airlie <airlied(a)redhat.com>
---
drivers/gpu/drm/drm_debugfs.c | 11 ++++++++++-
1 file changed, 10 …
[View More]insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
index a05087c..b855fd7 100644
--- a/drivers/gpu/drm/drm_debugfs.c
+++ b/drivers/gpu/drm/drm_debugfs.c
@@ -229,7 +229,16 @@ int drm_debugfs_cleanup(struct drm_minor *minor)
if (dev->driver->debugfs_cleanup)
dev->driver->debugfs_cleanup(minor);
- drm_debugfs_remove_files(drm_debugfs_list, DRM_DEBUGFS_ENTRIES, minor);
+ while (!list_empty(&minor->debugfs_list)) {
+ struct drm_info_node *node =
+ list_first_entry(&minor->debugfs_list,
+ struct drm_info_node,
+ list);
+
+ debugfs_remove(node->dent);
+ list_del(&node->list);
+ kfree(node);
+ }
debugfs_remove(minor->debugfs_root);
minor->debugfs_root = NULL;
--
1.8.3.2
[View Less]
I am having problems using the new Radeon DPM patches on my AMD E-350
APU system. Running the kernel with radeon.dpm=0 works as expected (I
used it for several hours yesterday with no problems), but with
radeon.dpm=1 it locks up graphically as soon as X starts. I am able to
log in through the network though, and have retrieved a dmesg.
Visually, when X starts, the screen fills with non-moving colored random
static. After a few seconds, it changes color to red and then slowly
fades to white. No …
[View More]mouse pointer or anything else is visible.
The system is running Ubuntu Gnome 13.04. The kernel is 3.10.0 with the
latest agd5f/drm-next-3.11-wip merged in.
The two main differences between dmesg from a working boot and from a
failed one is the listing of the power states 0-5 and notes that it's
switching from the "boot" to "performance" power state; and then, later
when X starts, these errors:
radeon 0000:00:01.0: GPU lockup CP stall for more than 10000msec
radeon 0000:00:01.0: GPU lockup (waiting for 0x0000000000000003 last fence id 0x0000000000000001)
radeon 0000:00:01.0: fence driver on ring 5 use gpu addr 0x0000000000177118 and cpu addr 0xffffc90005318118
radeon 0000:00:01.0: Saved 55 dwords of commands on ring 0.
radeon 0000:00:01.0: GPU softreset: 0x00000009
radeon 0000:00:01.0: GRBM_STATUS = 0xB2433828
radeon 0000:00:01.0: GRBM_STATUS_SE0 = 0x08000007
radeon 0000:00:01.0: GRBM_STATUS_SE1 = 0x00000007
radeon 0000:00:01.0: SRBM_STATUS = 0x20000040
radeon 0000:00:01.0: SRBM_STATUS2 = 0x00000000
radeon 0000:00:01.0: R_008674_CP_STALLED_STAT1 = 0x00000000
radeon 0000:00:01.0: R_008678_CP_STALLED_STAT2 = 0x40000000
radeon 0000:00:01.0: R_00867C_CP_BUSY_STAT = 0x00008000
radeon 0000:00:01.0: R_008680_CP_STAT = 0x80228643
radeon 0000:00:01.0: R_00D034_DMA_STATUS_REG = 0x44C83D57
radeon 0000:00:01.0: GRBM_SOFT_RESET=0x00007F6B
radeon 0000:00:01.0: SRBM_SOFT_RESET=0x00000100
radeon 0000:00:01.0: GRBM_STATUS = 0x00003828
radeon 0000:00:01.0: GRBM_STATUS_SE0 = 0x00000007
radeon 0000:00:01.0: GRBM_STATUS_SE1 = 0x00000007
radeon 0000:00:01.0: SRBM_STATUS = 0x20000040
radeon 0000:00:01.0: SRBM_STATUS2 = 0x00000000
radeon 0000:00:01.0: R_008674_CP_STALLED_STAT1 = 0x00000000
radeon 0000:00:01.0: R_008678_CP_STALLED_STAT2 = 0x00000000
radeon 0000:00:01.0: R_00867C_CP_BUSY_STAT = 0x00000000
radeon 0000:00:01.0: R_008680_CP_STAT = 0x00000000
radeon 0000:00:01.0: R_00D034_DMA_STATUS_REG = 0x44C83D57
radeon 0000:00:01.0: GPU reset succeeded, trying to resume
[drm] PCIE GART of 512M enabled (table at 0x0000000000040000).
radeon 0000:00:01.0: WB enabled
radeon 0000:00:01.0: fence driver on ring 0 use gpu addr 0x0000000018000c00 and cpu addr 0xffff8801f7fe6c00
radeon 0000:00:01.0: fence driver on ring 3 use gpu addr 0x0000000018000c0c and cpu addr 0xffff8801f7fe6c0c
radeon 0000:00:01.0: fence driver on ring 5 use gpu addr 0x0000000000177118 and cpu addr 0xffffc90005db2118
[drm] ring test on 0 succeeded in 0 usecs
[drm] ring test on 3 succeeded in 0 usecs
[drm] ring test on 5 succeeded in 1 usecs
[drm] UVD initialized successfully.
radeon 0000:00:01.0: GPU lockup CP stall for more than 10000msec
radeon 0000:00:01.0: GPU lockup (waiting for 0x0000000000000004 last fence id 0x0000000000000001)
[drm:r600_ib_test] *ERROR* radeon: fence wait failed (-35).
[drm:radeon_ib_ring_tests] *ERROR* radeon: failed testing IB on GFX ring (-35).
radeon 0000:00:01.0: ib ring test failed (-35).
radeon 0000:00:01.0: fence driver on ring 5 use gpu addr 0x0000000000177118 and cpu addr 0xffffc90005318118
radeon 0000:00:01.0: GPU softreset: 0x00000009
radeon 0000:00:01.0: GRBM_STATUS = 0xB3533828
radeon 0000:00:01.0: GRBM_STATUS_SE0 = 0x2C000007
radeon 0000:00:01.0: GRBM_STATUS_SE1 = 0x00000007
radeon 0000:00:01.0: SRBM_STATUS = 0x20000040
radeon 0000:00:01.0: SRBM_STATUS2 = 0x00000000
radeon 0000:00:01.0: R_008674_CP_STALLED_STAT1 = 0x00000000
radeon 0000:00:01.0: R_008678_CP_STALLED_STAT2 = 0x400C0000
radeon 0000:00:01.0: R_00867C_CP_BUSY_STAT = 0x00048000
radeon 0000:00:01.0: R_008680_CP_STAT = 0x80268643
radeon 0000:00:01.0: R_00D034_DMA_STATUS_REG = 0x44C83D57
radeon 0000:00:01.0: GRBM_SOFT_RESET=0x00007F6B
radeon 0000:00:01.0: SRBM_SOFT_RESET=0x00000100
radeon 0000:00:01.0: GRBM_STATUS = 0x00003828
radeon 0000:00:01.0: GRBM_STATUS_SE0 = 0x00000007
radeon 0000:00:01.0: GRBM_STATUS_SE1 = 0x00000007
radeon 0000:00:01.0: SRBM_STATUS = 0x20000040
radeon 0000:00:01.0: SRBM_STATUS2 = 0x00000000
radeon 0000:00:01.0: R_008674_CP_STALLED_STAT1 = 0x00000000
radeon 0000:00:01.0: R_008678_CP_STALLED_STAT2 = 0x00000000
radeon 0000:00:01.0: R_00867C_CP_BUSY_STAT = 0x00000000
radeon 0000:00:01.0: R_008680_CP_STAT = 0x00000000
radeon 0000:00:01.0: R_00D034_DMA_STATUS_REG = 0x44C83D57
radeon 0000:00:01.0: GPU reset succeeded, trying to resume
[drm] PCIE GART of 512M enabled (table at 0x0000000000040000).
radeon 0000:00:01.0: WB enabled
radeon 0000:00:01.0: fence driver on ring 0 use gpu addr 0x0000000018000c00 and cpu addr 0xffff8801f7fe6c00
radeon 0000:00:01.0: fence driver on ring 3 use gpu addr 0x0000000018000c0c and cpu addr 0xffff8801f7fe6c0c
radeon 0000:00:01.0: fence driver on ring 5 use gpu addr 0x0000000000177118 and cpu addr 0xffffc90005c32118
[drm] ring test on 0 succeeded in 1 usecs
[drm] ring test on 3 succeeded in 1 usecs
[drm] ring test on 5 succeeded in 1 usecs
[drm] UVD initialized successfully.
--
Bruce Guenter <bruce(a)untroubled.org> http://untroubled.org/
[View Less]
Hi list,
In June 2012 I started a discussion on moving the radeon PM info out
from debugfs, into a proper place available to all, be it proc, sysfs,
or some other way. For the rationale please see the archives:
http://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg23401.html
Jerome's reply at the time was that since big changes are coming, he
didn't want to commit to any ABI at that time. DPM has now landed.
Jerome wanted to implement a custom ioctl for unprivileged apps to
query …
[View More]the power details (and ideally other GPU info too). As now the
big changes have happened, what's the status on this ioctl?
Pre-emptive -enopatch: I'm not the right person to design an ioctl, with
exactly zero such experience in making kernel ABIs. I do volunteer to
making the userspace app that displays the values and info.
- Lauri
[View Less]
Hello,
This is the second version patchset.
GEM CMA supports dma_buf but it needs GEM CMA specific functionality for
dma_buf. We can use prime helpers for dma_buf by commit
89177644a7b6306e6084a89eab7e290f4bfef397 "drm: add prime helpers", so
this patchset is to replace from using GEM CMA specific functions to
using prime helpers.
To Laurent,
It is merged a patch to cache mapping from DRM Prime, can this patchset
get your ack?
Changes from v1:
- rebased from drm-next branch of
git://…
[View More]people.freedesktop.org/~airlied/linux
- fix to check whether gem_prime_mmap field is NULL
from "drm: add mmap function to prime helpers" commit
Joonyoung Shim (3):
drm: add mmap function to prime helpers
drm/cma: add low-level hook functions to use prime helpers
drm/cma: remove GEM CMA specific dma_buf functionality
drivers/gpu/drm/drm_gem_cma_helper.c | 293
+++++------------------------------
drivers/gpu/drm/drm_prime.c | 8 +-
include/drm/drmP.h | 2 +
include/drm/drm_gem_cma_helper.h | 13 +-
4 files changed, 60 insertions(+), 256 deletions(-)
[View Less]