dri-devel February 2016

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1240 discussions

[PATCH 1/2] Support for adreno 430.
by C Stout 02 Feb '16

02 Feb '16

Change-Id: I6c891515d93a6f1a597e762090c3530a6810c6c6 --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 50 ++++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 41 ++++++++++++++++-------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++ 4 files changed, 85 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index ef20cb5..9ed3abe 100644 --- a/… [View More]drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -111,11 +111,17 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000222); gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_HLSQ , 0x00000000); gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000); - gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00020000); - gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA); + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000); + /* Early A430's have a timing issue with SP/TP power collapse; + disabling HW clock gating prevents it. */ + if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2) + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0); + else + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA); gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2, 0); } + static void a4xx_me_init(struct msm_gpu *gpu) { struct msm_ringbuffer *ring = gpu->rb; @@ -150,7 +156,7 @@ static int a4xx_hw_init(struct msm_gpu *gpu) uint32_t *ptr, len; int i, ret; - if (adreno_is_a4xx(adreno_gpu)) { + if (adreno_is_a420(adreno_gpu)) { gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F); gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4); gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001); @@ -159,6 +165,13 @@ static int a4xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818); gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018); gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); + } else if (adreno_is_a430(adreno_gpu)) { + gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001); + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818); + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018); + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818); + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018); + gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); } else { BUG(); } @@ -170,6 +183,10 @@ static int a4xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_RBBM_SP_HYST_CNT, 0x10); gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10); + if (adreno_is_a430(adreno_gpu)) { + gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2, 0x30); + } + /* Enable the RBBM error reporting bits */ gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL0, 0x00000001); @@ -192,6 +209,9 @@ static int a4xx_hw_init(struct msm_gpu *gpu) /* Turn on performance counters: */ gpu_write(gpu, REG_A4XX_RBBM_PERFCTR_CTL, 0x01); + if (adreno_is_a430(adreno_gpu)) + gpu_write(gpu, REG_A4XX_UCHE_CACHE_WAYS_VFD, 0x07); + /* Disable L2 bypass to avoid UCHE out of bounds errors */ gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, 0xffff0000); gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, 0xffff0000); @@ -199,6 +219,15 @@ static int a4xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) | (adreno_is_a420(adreno_gpu) ? (1 << 29) : 0)); + /* On A430 enable SP regfile sleep for power savings */ + /* TODO downstream does this for !420, so maybe applies for 405 too? */ + if (!adreno_is_a420(adreno_gpu)) { + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0, + 0x00000441); + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1, + 0x00000441); + } + a4xx_enable_hwcg(gpu); /* @@ -213,9 +242,11 @@ static int a4xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, val); } - ret = adreno_hw_init(gpu); - if (ret) - return ret; + if (!adreno_is_a430(adreno_gpu)) { + ret = adreno_hw_init(gpu); + if (ret) + return ret; + } /* setup access protection: */ gpu_write(gpu, REG_A4XX_CP_PROTECT_CTRL, 0x00000007); @@ -326,6 +357,13 @@ static irqreturn_t a4xx_irq(struct msm_gpu *gpu) status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); DBG("%s: Int status %08x", gpu->name, status); + if (status & (1 << A4XX_INT_CP_REG_PROTECT_FAULT)) { + uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); + printk("CP | Protected mode error| %s | addr=%x\n", + reg & (1 << 24) ? "WRITE" : "READ", + (reg & 0xFFFFF) >> 2); + } + gpu_write(gpu, REG_A4XX_RBBM_INT_CLEAR_CMD, status); msm_gpu_retire(gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 1ea2df5..43d5aaa 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -73,6 +73,14 @@ static const struct adreno_info gpulist[] = { .pfpfw = "a420_pfp.fw", .gmem = (SZ_1M + SZ_512K), .init = a4xx_gpu_init, + }, { + .rev = ADRENO_REV(4, 3, 0, ANY_ID), + .revn = 430, + .name = "A430", + .pm4fw = "a420_pm4.fw", + .pfpfw = "a420_pfp.fw", + .gmem = (SZ_1M + SZ_512K), + .init = a4xx_gpu_init, }, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index a3b54cc..33c96d0d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -68,18 +68,15 @@ int adreno_hw_init(struct msm_gpu *gpu) adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL, /* size is log2(quad-words): */ AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) | - AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8))); + AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) | + (adreno_is_a430(adreno_gpu) ? (1 << 27) : 0)); /* Setup ringbuffer address: */ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova); - adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, - rbmemptr(adreno_gpu, rptr)); - /* Setup scratch/timestamp: */ - adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_ADDR, - rbmemptr(adreno_gpu, fence)); - - adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_UMSK, 0x1); + if (!adreno_is_a430(adreno_gpu)) + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, + rbmemptr(adreno_gpu, rptr)); return 0; } @@ -89,6 +86,16 @@ static uint32_t get_wptr(struct msm_ringbuffer *ring) return ring->cur - ring->start; } +/* Use this helper to read rptr, since a430 doesn't update rptr in memory */ +static uint32_t get_rptr(struct adreno_gpu *adreno_gpu) +{ + if (adreno_is_a430(adreno_gpu)) + return adreno_gpu->memptrs->rptr = adreno_gpu_read( + adreno_gpu, REG_ADRENO_CP_RB_RPTR); + else + return adreno_gpu->memptrs->rptr; +} + uint32_t adreno_last_fence(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -137,7 +144,8 @@ int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, if (priv->lastctx == ctx) break; case MSM_SUBMIT_CMD_BUF: - OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2); + OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? + CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); OUT_RING(ring, submit->cmd[i].iova); OUT_RING(ring, submit->cmd[i].size); ibs++; @@ -216,9 +224,16 @@ void adreno_idle(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); uint32_t wptr = get_wptr(gpu->rb); + int ret; /* wait for CP to drain ringbuffer: */ - if (spin_until(adreno_gpu->memptrs->rptr == wptr)) + if (adreno_is_a430(adreno_gpu)) + ret = spin_until((adreno_gpu->memptrs->rptr = adreno_gpu_read( + adreno_gpu, REG_ADRENO_CP_RB_RPTR)) == wptr); + else + ret = spin_until(adreno_gpu->memptrs->rptr == wptr); + + if (ret) DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name); /* TODO maybe we need to reset GPU here to recover from hang? */ @@ -237,7 +252,7 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m) seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence, gpu->submitted_fence); - seq_printf(m, "rptr: %d\n", adreno_gpu->memptrs->rptr); + seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu)); seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr); seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb)); @@ -278,7 +293,7 @@ void adreno_dump_info(struct msm_gpu *gpu) printk("fence: %d/%d\n", adreno_gpu->memptrs->fence, gpu->submitted_fence); - printk("rptr: %d\n", adreno_gpu->memptrs->rptr); + printk("rptr: %d\n", get_rptr(adreno_gpu)); printk("wptr: %d\n", adreno_gpu->memptrs->wptr); printk("rb wptr: %d\n", get_wptr(gpu->rb)); @@ -313,7 +328,7 @@ static uint32_t ring_freewords(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); uint32_t size = gpu->rb->size / 4; uint32_t wptr = get_wptr(gpu->rb); - uint32_t rptr = adreno_gpu->memptrs->rptr; + uint32_t rptr = get_rptr(adreno_gpu); return (rptr + (size - 1) - wptr) % size; } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 0a312e9..c26aea1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -228,6 +228,11 @@ static inline int adreno_is_a420(struct adreno_gpu *gpu) return gpu->revn == 420; } +static inline int adreno_is_a430(struct adreno_gpu *gpu) +{ + return gpu->revn == 430; +} + int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); int adreno_hw_init(struct msm_gpu *gpu); uint32_t adreno_last_fence(struct msm_gpu *gpu); -- 2.1.4 [View Less]

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[PATCH 0/8] Enable Gen 7 Observation Architecture
by Robert Bragg 02 Feb '16

02 Feb '16

This series enables support for the Observation Architecture on Haswell Compared to the last series I sent out, the main changes are: * The terminology changed so we open a 'stream' not an 'event'. * A stream is configured with an array of u64 properties after finding the previous config struct quite awkward to validate and not well suited to supporting multiple kinds of streams sharing common config options (which arises with work Sourab Gupta is looking at based on this driver) * … [View More]No pre-defined enum of metric set IDs and metric sets are now advertised via sysfs. This is to allow for configs being loaded at runtime in the future and the use of uuids that can be unambiguously mapped to corresponding normalization equations in userspace. Another consideration here was that we might need to add new versions of a particular config like 'compute basic' (more likely for newer configs with less testing) at which point the enum doesn't really make life easier for userspace if you have to be aware of the versioning relationships and attempt different IDs to find the latest version the kernel supports. I haven't written igt tests for this yet, but can hopefully start looking at that next if there's no major issue with the general api. So far the interface has been tested and iterated based on what's worked out well for GPU Top[1], an implementation of GL_INTEL_performance_query in Mesa and an implementation of an API called MDAPI used by GPA/VTune to capture metrics (private a.t.m as I'm not sure there would be much general interest in it.) The PRM for Haswell's OA unit can be found here: https://01.org/sites/default/files/documentation/ observability_performance_counters_haswell.pdf (though unfortunately it's not very complete documentation) An example of opening an i915 perf stream can be seen in Mesa here: https://github.com/rib/mesa/blob/wip/rib/oa-next/src/mesa/drivers/ dri/i965/brw_performance_query.c#L904 A summary of the stream format can seen here: https://github.com/rib/linux/wiki/i915-perf-stream-format There's an open issue to do with how to properly clear the status bits in the OASTATUS1 register which I noticed the other day can't be right a.t.m and I'm waiting for feedback on from the Windows team or OA architect. I don't expect it will have much impact so it still seemed worth sending this series now. Another thing to mention is that I just noticed gputop is hitting the cpu more than expected in its overview mode, polling for OA data and I need to double check it's not a driver issue. Hopefully a minor issue; probably not worth holding things up for. Although this series only adds basic infrastructure and enables Haswell it's probably good to keep in mind other work that builds on top. I've also enabled Gen8+; there's some further work by Sourab Gupta to access metrics in sync with command stream processing and Matthew Auld has experimented with an interface for registering new OA configurations at runtime. In case it's helpful to reference, the Gen 8 enabling can be seen here: https://github.com/rib/linux/tree/wip/rib/oa-next Sourab's work can be seen here: https://github.com/sourabgu/linux/tree/rebase-4.4-testing Matt's patch for runtime configs can be seen here: https://github.com/matt-auld/linux/tree/wip/matt-auld/oa-4.4-dynamic-testing Regards, - Robert [1] https://github.com/rib/gputop https://github.com/rib/gputop/wiki/Build-Instructions Robert Bragg (8): drm/i915: Add i915 perf infrastructure drm/i915: rename OACONTROL GEN7_OACONTROL drm/i915: Add 'render basic' Haswell OA unit config drm/i915: Add i915 perf event for Haswell OA unit drm/i915: advertise available metrics via sysfs drm/i915: Add dev.i915.perf_event_paranoid sysctl option drm/i915: add oa_event_min_timer_exponent sysctl drm/i915: Add more Haswell OA metric sets drivers/gpu/drm/i915/Makefile | 4 + drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +- drivers/gpu/drm/i915/i915_dma.c | 7 + drivers/gpu/drm/i915/i915_drv.h | 154 ++++ drivers/gpu/drm/i915/i915_gem_context.c | 23 +- drivers/gpu/drm/i915/i915_oa_hsw.c | 658 ++++++++++++++++ drivers/gpu/drm/i915/i915_oa_hsw.h | 38 + drivers/gpu/drm/i915/i915_perf.c | 1283 +++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 340 +++++++- include/uapi/drm/i915_drm.h | 121 +++ 10 files changed, 2625 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_oa_hsw.c create mode 100644 drivers/gpu/drm/i915/i915_oa_hsw.h create mode 100644 drivers/gpu/drm/i915/i915_perf.c -- 2.7.0 [View Less]

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[PATCH] drm/dp/mst: deallocate payload on port destruction
by Harry Wentland 02 Feb '16

02 Feb '16

From: Mykola Lysenko <Mykola.Lysenko(a)amd.com> This is needed to properly deallocate port payload after downstream branch get unplugged. In order to do this unplugged MST topology should be preserved, to find first alive port on path to unplugged MST topology, and send payload deallocation request to branch device of found port. For this mstb and port kref's are used in reversed order to track when port and branch memory could be freed. Added additional functions to find appropriate … [View More]mstb as described above. Signed-off-by: Mykola Lysenko <Mykola.Lysenko(a)amd.com> Reviewed-by: Harry Wentland <Harry.Wentland(a)amd.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 91 ++++++++++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index fc589265068b..5662e68ecccd 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -803,6 +803,18 @@ static struct drm_dp_mst_branch *drm_dp_add_mst_branch_device(u8 lct, u8 *rad) return mstb; } +static void drm_dp_free_mst_port(struct kref *kref); + +static void drm_dp_free_mst_branch_device(struct kref *kref) +{ + struct drm_dp_mst_branch *mstb = container_of(kref, struct drm_dp_mst_branch, kref); + if (mstb->port_parent) { + if (list_empty(&mstb->port_parent->next)) + kref_put(&mstb->port_parent->kref, drm_dp_free_mst_port); + } + kfree(mstb); +} + static void drm_dp_destroy_mst_branch_device(struct kref *kref) { struct drm_dp_mst_branch *mstb = container_of(kref, struct drm_dp_mst_branch, kref); @@ -810,6 +822,15 @@ static void drm_dp_destroy_mst_branch_device(struct kref *kref) bool wake_tx = false; /* + * init kref again to be used by ports to remove mst branch when it is + * not needed anymore + */ + kref_init(kref); + + if (mstb->port_parent && list_empty(&mstb->port_parent->next)) + kref_get(&mstb->port_parent->kref); + + /* * destroy all ports - don't need lock * as there are no more references to the mst branch * device at this point. @@ -835,7 +856,8 @@ static void drm_dp_destroy_mst_branch_device(struct kref *kref) if (wake_tx) wake_up(&mstb->mgr->tx_waitq); - kfree(mstb); + + kref_put(kref, drm_dp_free_mst_branch_device); } static void drm_dp_put_mst_branch_device(struct drm_dp_mst_branch *mstb) @@ -883,6 +905,7 @@ static void drm_dp_destroy_port(struct kref *kref) * from an EDID retrieval */ mutex_lock(&mgr->destroy_connector_lock); + kref_get(&port->parent->kref); list_add(&port->next, &mgr->destroy_connector_list); mutex_unlock(&mgr->destroy_connector_lock); schedule_work(&mgr->destroy_connector_work); @@ -1617,6 +1640,37 @@ static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, return 0; } +static struct drm_dp_mst_port *drm_dp_get_last_connected_port_to_mstb(struct drm_dp_mst_branch *mstb) +{ + if (!mstb->port_parent) + return NULL; + + if (mstb->port_parent->mstb != mstb) + return mstb->port_parent; + + return drm_dp_get_last_connected_port_to_mstb(mstb->port_parent->parent); +} + +static struct drm_dp_mst_branch *drm_dp_get_last_connected_port_and_mstb(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_branch *mstb, + int *port_num) +{ + struct drm_dp_mst_branch *rmstb = NULL; + struct drm_dp_mst_port *found_port; + mutex_lock(&mgr->lock); + if (mgr->mst_primary) { + found_port = drm_dp_get_last_connected_port_to_mstb(mstb); + + if (found_port) { + rmstb = found_port->parent; + kref_get(&rmstb->kref); + *port_num = found_port->port_num; + } + } + mutex_unlock(&mgr->lock); + return rmstb; +} + static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int id, @@ -1624,13 +1678,18 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr, { struct drm_dp_sideband_msg_tx *txmsg; struct drm_dp_mst_branch *mstb; - int len, ret; + int len, ret, port_num; u8 sinks[DRM_DP_MAX_SDP_STREAMS]; int i; + port_num = port->port_num; mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent); - if (!mstb) - return -EINVAL; + if (!mstb) { + mstb = drm_dp_get_last_connected_port_and_mstb(mgr, port->parent, &port_num); + + if (!mstb) + return -EINVAL; + } txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); if (!txmsg) { @@ -1642,7 +1701,7 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr, sinks[i] = i; txmsg->dst = mstb; - len = build_allocate_payload(txmsg, port->port_num, + len = build_allocate_payload(txmsg, port_num, id, pbn, port->num_sdp_streams, sinks); @@ -2787,6 +2846,13 @@ static void drm_dp_tx_work(struct work_struct *work) mutex_unlock(&mgr->qlock); } +static void drm_dp_free_mst_port(struct kref *kref) +{ + struct drm_dp_mst_port *port = container_of(kref, struct drm_dp_mst_port, kref); + kref_put(&port->parent->kref, drm_dp_free_mst_branch_device); + kfree(port); +} + static void drm_dp_destroy_connector_work(struct work_struct *work) { struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct drm_dp_mst_topology_mgr, destroy_connector_work); @@ -2807,13 +2873,22 @@ static void drm_dp_destroy_connector_work(struct work_struct *work) list_del(&port->next); mutex_unlock(&mgr->destroy_connector_lock); + kref_init(&port->kref); + INIT_LIST_HEAD(&port->next); + mgr->cbs->destroy_connector(mgr, port->connector); drm_dp_port_teardown_pdt(port, port->pdt); - if (!port->input && port->vcpi.vcpi > 0) - drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi); - kfree(port); + if (!port->input && port->vcpi.vcpi > 0) { + if (mgr->mst_state) { + drm_dp_mst_reset_vcpi_slots(mgr, port); + drm_dp_update_payload_part1(mgr); + drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi); + } + } + + kref_put(&port->kref, drm_dp_free_mst_port); send_hotplug = true; } if (send_hotplug) -- 2.1.4 [View Less]

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[PATCH v2 0/2] Add a DRM display driver to the Allwinner H3
by Jean-Francois Moine 02 Feb '16

02 Feb '16

The proposed DRM driver works on a Orange PI 2 with a kernel 4.4.0 and the H3 patches found in Hans de Goede's GIT repository. As there is no documentation about the HDMI of the H3, the associated encoder/connector driver has not been included in this patch series. For tests, it may be built as a out-of-tree driver from the tarball: http://moinejf.free.fr/opi2/h3-hdmi.tar.gz and the DT files: http://moinejf.free.fr/opi2/sun8i-h3.dtsi http://moinejf.free.fr/opi2/sun8i-h3-orangepi-plus.dts … [View More]

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[PATCH v3 0/2] Add a DRM display driver to the Allwinner H3
by Jean-Francois Moine 02 Feb '16

02 Feb '16

The proposed DRM driver works on a Orange PI 2 with a kernel 4.5.0-rc1 and some H3 patches found in Hans de Goede's GIT repository. As there is no documentation about the HDMI of the H3, the associated encoder/connector driver has not been included in this patch series. For test purpose, it may be built as a out-of-tree driver from the tarball: http://moinejf.free.fr/opi2/h3-hdmi.tar.gz and the DT files: http://moinejf.free.fr/opi2/sun8i-h3.dtsi http://moinejf.free.fr/opi2/sun8i-h3-… [View More]

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[PATCH RFC 0/2] Add a display driver to the Allwinner H3
by Jean-Francois Moine 02 Feb '16

02 Feb '16

The proposed DRM driver works on a Orange PI 2 with a kernel 4.4-rc1 and the H3 patches found in Hans de Goede's GIT repository. As there is no documentation about the DE2 nor about the HDMI which are found in the H3, this driver has been built from Allwiiner's sources. So, there may be license problems, especially for the file de2_hdmi_h3.c which contains a lot of magic values. The associated DT and documentation will be submitted when the H3 DTs will be in the kernel. Jean-Francois Moine (… [View More]

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[PATCH 00/10] android sync framework: clean up IOCTLs and ABI.
by Gustavo Padovan 02 Feb '16

02 Feb '16

From: Gustavo Padovan <gustavo.padovan(a)collabora.co.uk> Hi, This patch series clean up IOCTLs and abi of sync framework and it is a follow up on the clean up series I've sent on Jan 21: http://thread.gmane.org/gmane.comp.video.dri.devel/145509 The main changes here are: * remove of SYNC_WAIT ioctl, poll() should be used instead. * rename some structs and macros to better reflect the new internal names. * clean up and improve ABI on SYNC_IOC_FILE_INFO * add flags filed to all … [View More]

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[PATCH 0/4] virtio-gpu: Fixes for atomic support
by Rob Herring 01 Feb '16

01 Feb '16

Dave, This series is the minimal changes to get virtio-gpu working with Android DRM based hwcomposer. The first 3 patches are fixes, but I assume they are only hit if using the atomic APIs which is dependent on the 4th patch. I suspect async commit support is also missing, but Android doesn't seem to need it. I also have a few more patches for fb emulation to support panning and mmapping the framebuffer. I'm not too sure that is really worth supporting though. Rob Rob Herring (4): … [View More]

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[PATCH] amdgpu acp support drm-fixes-4.5
by Alex Deucher 01 Feb '16

01 Feb '16

Hi Dave, These patches add ACP support to amdgpu. I would have sent these in for the merge window but they depended on audio and pm tree changes that all went upstream in 4.5 so they were not available in the drm tree at the time. Chances of regressions are low since this just adds support for a new hw block. It does not modify any existing functionality. This enables audio on CZ asics which use i2s audio rather than azalia audio. The following changes since commit … [View More]

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[PATCH libdrm 1/3] amdgpu: add libdrm as private requirement/dependency
by Emil Velikov 01 Feb '16

01 Feb '16

Otherwise libdrm.so won't end up in the --libs, when one static links libdrm_amdgpu. Cc: Michel Dänzer <michel.daenzer(a)amd.com> Cc: Christian König <christian.koenig(a)amd.com> Signed-off-by: Emil Velikov <emil.l.velikov(a)gmail.com> --- amdgpu/libdrm_amdgpu.pc.in | 1 + 1 file changed, 1 insertion(+) diff --git a/amdgpu/libdrm_amdgpu.pc.in b/amdgpu/libdrm_amdgpu.pc.in index 417865e..f1c552a 100644 --- a/amdgpu/libdrm_amdgpu.pc.in +++ b/amdgpu/libdrm_amdgpu.pc.in @@ -8,3 +… [View More]

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dri-devel February 2016