dri-devel March 2018

dri-devel@lists.freedesktop.org

263 participants
1856 discussions

[RFC 00/14] Per-instance pagetables for MSM GPUs
by Jordan Crouse 02 Mar '18

02 Mar '18

This is a request for comment for support in the iommu, arm-smmu and MSM GPU driver to support per (GPU) instance pagetables. The general idea behind per-instance pagetables is that each GPU client can have its own pagetable and virtual memory space which prevents malicious or accidental corruption or copying. We say per-instance because the pagetables are unique to each DRM file handle and there could be multiple instances per process. In newer arm-smmu implementations this behavior could be managed with hardware based PASIDs (see Jean Phillipe's epic SVA stack https://patchwork.kernel.org/patch/10214963/) but all the MSM GPU implementations in existence use arm-smmu-v2 which doesn't have the ability to support switching pagetables in hardware. As a result the vendor has added a bit of hardware specific glue to allow the GPU microcode to switch the pagetable asynchronously during execution (basically it reaches out and reprograms some of the context bank registers). To support all of this we need a handful of changes to allow the client driver to create a properly formatted pagetable and directly map and unmap buffers inside of that pagetable and get the parameters (i.e. the physical address of the pagetable) to program into the GPU at the appropriate time. This stack builds on the aforementioned code from Jean-Phillipe to add the needed support to iommu core and arm-smmu and then implement per-instance pagetables in the MSM DRM GPU driver for the a5xx family (tested on the db820c). The first two patches add support to create enable a TTBR1 pagetable for arm-smmuv-2 if the appropriate domain attribute is selected. It creates a pagetable and programs the appropriate registers to enable TTBR1. The sign extension bit is programmed as the highest bit in the ibs region (or the special 48th bit when the UBS is 49 bits). The correct pagetable is automatically selected for map/unmap based on the sign extension bit. The next three patches add "virtual" pasid support. This allows a client to allocate a pasid which is an index to a pagetable structure. The pasid token is used to map and unmap entries in that pagetable structure. The existing pasid idr for SVA is reused so that clients that also support hardware PASID entries can use both types if they wish. Th next patch adds a special side-band function for arm-smmu that registers two callbacks to inform the client driver when a new pasid is created/destroyed. This allows the arm-smmu driver to pass the pagetable information (ttbr and asid) to the client without needing changes to the IOMMU core. All the following patches are for the DRM/GPU driver. The first enables 64 bit mode for a5xx which lets us use all 48 bits. The next patch 5 patches are infrastructure patches to cleanup address spaces and prepare for having a per-instance address space and the final patch enables per-instance pagetables for a5xx and implements the PM4 to switch the pagetable at create time. Please know that nearly all of this is up for discussion. In particular since we all know that the two hardest problems in computer science are caches, naming and off-by-one errors I am open to fixing the vocabulary and terminology for "pasid" and "per-instance" and whatever - please paint that bikeshed if you feel so inclined. Thanks for reading this far. On with the code. Applies against git://linux-arm.org/linux-jpb.git sva/v1 Jordan Crouse (14): iommu: Add DOMAIN_ATTR_ENABLE_TTBR1 iommu/arm-smmu: Add support for TTBR1 iommu: Create a base struct for io_mm iommu: sva: Add support for pasid allocation iommu: arm-smmu: Add pasid implementation iommu: arm-smmu: Add side-band function to specific pasid callbacks drm/msm: Enable 64 bit mode by default drm/msm: Pass the MMU domain index in struct msm_file_private drm/msm/gpu: Support using TTBR1 for kernel buffer objects drm/msm: Add msm_mmu features drm/msm: Add support for iommu-sva PASIDs drm/msm: Add support for per-instance address spaces drm/msm: Support per-instance address spaces drm/msm/a5xx: Support per-instance pagetables drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 69 +++++++ drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 17 ++ drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 76 ++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 + drivers/gpu/drm/msm/msm_drv.c | 45 +++-- drivers/gpu/drm/msm/msm_drv.h | 4 + drivers/gpu/drm/msm/msm_gem.h | 1 + drivers/gpu/drm/msm/msm_gem_submit.c | 13 +- drivers/gpu/drm/msm/msm_gem_vma.c | 36 +++- drivers/gpu/drm/msm/msm_gpu.c | 25 ++- drivers/gpu/drm/msm/msm_gpu.h | 4 +- drivers/gpu/drm/msm/msm_iommu.c | 186 ++++++++++++++++++- drivers/gpu/drm/msm/msm_mmu.h | 19 ++ drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + drivers/iommu/arm-smmu-regs.h | 2 - drivers/iommu/arm-smmu-v3.c | 8 +- drivers/iommu/arm-smmu.c | 210 +++++++++++++++++++++- drivers/iommu/io-pgtable-arm.c | 160 +++++++++++++++-- drivers/iommu/io-pgtable-arm.h | 20 +++ drivers/iommu/io-pgtable.h | 16 +- drivers/iommu/iommu-sva.c | 289 ++++++++++++++++++++++++++++-- drivers/iommu/iommu.c | 3 +- include/linux/arm-smmu.h | 18 ++ include/linux/iommu.h | 68 ++++++- 25 files changed, 1205 insertions(+), 101 deletions(-) create mode 100644 include/linux/arm-smmu.h -- 2.16.1

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[PATCH libdrm 1/1] intel: allocate buffer with the requested size when reuse is disabled
by James Xiong 02 Mar '18

02 Mar '18

From: "Xiong, James" <james.xiong(a)intel.com> Previously a bucket size was used for buffer allocation whether bo_reuse is false or true. This patch returns NULL in function drm_intel_gem_bo_bucket_for_size() when bo_reuse is false, the original requested size is used instead. Signed-off-by: Xiong, James <james.xiong(a)intel.com> --- intel/intel_bufmgr_gem.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 386da30..43a3f38 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -402,6 +402,9 @@ drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem, { int i; + if (!bufmgr_gem->bo_reuse) + return NULL; + for (i = 0; i < bufmgr_gem->num_buckets; i++) { struct drm_intel_gem_bo_bucket *bucket = &bufmgr_gem->cache_bucket[i]; @@ -1382,7 +1385,7 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time) bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size); /* Put the buffer into our internal cache for reuse if we can. */ - if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL && + if (bo_gem->reusable && bucket != NULL && drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem, I915_MADV_DONTNEED)) { bo_gem->free_time = time; @@ -3806,6 +3809,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) drm_intel_gem_get_pipe_from_crtc_id; bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references; + bufmgr_gem->bo_reuse = false; /* explicitly set to false */ init_cache_buckets(bufmgr_gem); DRMINITLISTHEAD(&bufmgr_gem->vma_cache); -- 2.7.4

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[PATCH 1/2] drm/sun4i: increase lvds dclk max divisor
by Giulio Benetti 02 Mar '18

02 Mar '18

At the moment both min and max dclk div are set to 7. This doesn't allow to have lower frequencies. Increase dclk_max_div to 18 to achieve 30Mhz. Signed-off-by: Giulio Benetti <giulio.benetti(a)micronovasrl.com> --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 029d2ce..bb35f41 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -278,7 +278,7 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, u32 reg, val = 0; tcon->dclk_min_div = 7; - tcon->dclk_max_div = 7; + tcon->dclk_max_div = 18; sun4i_tcon0_mode_set_common(tcon, mode); /* Adjust clock delay */ -- 2.7.4

2 6

[PATCH v1 0/2] drm/panel: Add support for Raydium rm68200 panel
by Philippe Cornu 02 Mar '18

02 Mar '18

The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD panel connected using a MIPI-DSI video interface. Philippe Cornu (2): dt-bindings/display/panel: Add support for Raydium rm68200 dsi panel drm/panel: Add support for Raydium rm68200 panel driver .../bindings/display/panel/raydium,rm68200.txt | 25 ++ drivers/gpu/drm/panel/Kconfig | 8 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-raydium-rm68200.c | 464 +++++++++++++++++++++ 4 files changed, 498 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt create mode 100755 drivers/gpu/drm/panel/panel-raydium-rm68200.c -- 2.15.1

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[PATCH] drm/bridge: sii902x: Fall back to standard modes
by Linus Walleij 02 Mar '18

02 Mar '18

The following happens when connection a DVI output driven from the SiI9022 using a DVI-to-VGA adapter plug: i2c i2c-0: sendbytes: NAK bailout. i2c i2c-0: sendbytes: NAK bailout. Then no picture. Apparently the I2C engine inside the SiI9022 is not smart enough to try to fall back to DDC I2C. Or the vendor have not integrated the electronics properly. I don't know which one it is. By using standard modes as fallback, the bridge probes nicely with a minor warning and we get picture. This code is inspired by similar code in the dumb VGA bridge. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- drivers/gpu/drm/bridge/sii902x.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm/bridge/sii902x.c index b1ab4ab09532..4483095c4013 100644 --- a/drivers/gpu/drm/bridge/sii902x.c +++ b/drivers/gpu/drm/bridge/sii902x.c @@ -168,8 +168,19 @@ static int sii902x_get_modes(struct drm_connector *connector) return ret; edid = drm_get_edid(connector, sii902x->i2c->adapter); - drm_mode_connector_update_edid_property(connector, edid); - if (edid) { + if (!edid) { + /* + * This happens when using a simple DVI-to-VGA converter + * dongle for example: the I2C lines are not bridged over + * to VGA DDC. + */ + DRM_INFO("EDID readout failed, falling back to standard modes\n"); + ret = drm_add_modes_noedid(connector, 1920, 1080); + /* Set some standard resolution most monitors can handle */ + drm_set_preferred_mode(connector, 1024, 768); + } else { + /* Data from EDID readout */ + drm_mode_connector_update_edid_property(connector, edid); num = drm_add_edid_modes(connector, edid); kfree(edid); } -- 2.14.3

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[PATCH] drm: omapdrm: displays: panel-dsi-cm: Fix field access before set
by Laurent Pinchart 02 Mar '18

02 Mar '18

The driver accesses the ddata->in field before it gets set in the dsicm_connect() function. Use the local in pointer variable instead. Fixes: 7877632b4cd0 ("drm: omapdrm: displays: Get panel source at connect time") Signed-off-by: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> --- drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Tomi, This patch fixes a bug in a commit from your omapdrm-next branch that hasn't been merged upstream yet. I'll let you decide whether you want to squash it with the offending commit (and thus rebase) or apply it on top. Sorry for screwing up :-/ diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c index f960e55d64ea..428de90fced1 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c @@ -778,13 +778,13 @@ static int dsicm_connect(struct omap_dss_device *dssdev) goto err_connect; } - r = in->ops.dsi->request_vc(ddata->in, &ddata->channel); + r = in->ops.dsi->request_vc(in, &ddata->channel); if (r) { dev_err(dev, "failed to get virtual channel\n"); goto err_req_vc; } - r = in->ops.dsi->set_vc_id(ddata->in, ddata->channel, TCH); + r = in->ops.dsi->set_vc_id(in, ddata->channel, TCH); if (r) { dev_err(dev, "failed to set VC_ID\n"); goto err_vc_id; @@ -794,7 +794,7 @@ static int dsicm_connect(struct omap_dss_device *dssdev) return 0; err_vc_id: - in->ops.dsi->release_vc(ddata->in, ddata->channel); + in->ops.dsi->release_vc(in, ddata->channel); err_req_vc: in->ops.dsi->disconnect(in, dssdev); err_connect: -- Regards, Laurent Pinchart

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[PATCH v8 0/8] rockchip: kevin: Enable edp display
by Thierry Escande 02 Mar '18

02 Mar '18

Hi, This patchset makes edp display work on Chromebook kevin. This patchset has been originally posted by Jeffy Chen and the 2 first commits from a previous version (v6) are already merged in mainline. v8: Fixed compilation issue between patches #7 and #8 reported by Archit. v7: Rebased on top of next-20180108 and fixed conflicts Fixed a few warnings reported by checkpatch Jeffy Chen (8): drm/bridge: analogix: Do not use device's drvdata drm/bridge: analogix_dp: Fix connector and encoder cleanup drm/rockchip: analogix_dp: Add a sanity check for rockchip_drm_psr_register() drm/rockchip: dw-mipi-dsi: Fix error handling path drm/rockchip: inno_hdmi: Fix error handling path drm/bridge/synopsys: dw-hdmi: Add missing bridge detach drm/bridge/synopsys: dw-hdmi: Do not use device's drvdata drm/rockchip: dw_hdmi: Fix error handling path drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 52 +++++++---------- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 53 ++++++++--------- drivers/gpu/drm/exynos/exynos_dp.c | 29 ++++++---- drivers/gpu/drm/imx/dw_hdmi-imx.c | 22 ++++--- drivers/gpu/drm/meson/meson_dw_hdmi.c | 20 +++++-- drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c | 14 ++++- drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 67 +++++++++++++--------- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 21 ++++--- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 39 +++++++------ drivers/gpu/drm/rockchip/inno_hdmi.c | 22 +++++-- include/drm/bridge/analogix_dp.h | 19 +++--- include/drm/bridge/dw_hdmi.h | 17 +++--- 12 files changed, 214 insertions(+), 161 deletions(-) -- 2.14.1

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[PATCH] drm/sun4i: Handle DRM_BUS_FLAG_PIXDATA_*EDGE
by Giulio Benetti 02 Mar '18

02 Mar '18

Handle both positive and negative dclk polarity, according to bus_flags. Signed-off-by: Giulio Benetti <giulio.benetti(a)micronovasrl.com> --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index aaf911a..534e5ee 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -17,6 +17,7 @@ #include <drm/drm_encoder.h> #include <drm/drm_modes.h> #include <drm/drm_of.h> +#include <drm/drm_panel.h> #include <uapi/drm/drm_mode.h> @@ -340,6 +341,9 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, const struct drm_display_mode *mode) { + struct drm_panel *panel = tcon->panel; + struct drm_connector *connector = panel->connector; + struct drm_display_info display_info = connector->display_info; unsigned int bp, hsync, vsync; u8 clk_delay; u32 val = 0; @@ -395,8 +399,15 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, if (mode->flags & DRM_MODE_FLAG_PVSYNC) val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; + if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE) + clk_set_phase(tcon->dclk, 240); + + if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE) + clk_set_phase(tcon->dclk, 0); + regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, - SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE, + SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | + SUN4I_TCON0_IO_POL_VSYNC_POSITIVE, val); /* Map output pins to channel 0 */ -- 2.7.4

2 2

[PATCH v3 00/10] extend PWM framework to support PWM modes
by Claudiu Beznea 02 Mar '18

02 Mar '18

Hi all, Please give feedback on these patches which extends the PWM framework in order to support multiple PWM modes of operations. This series is a rework of [1] and [2]. The current patch series add the following PWM modes: - PWM mode normal - PWM mode complementary - PWM mode push-pull Normal mode - for PWM channels with one output; output waveforms looks like this: __ __ __ __ PWM __| |__| |__| |__| |__ <--T--> Where T is the signal period Since PWMs with more than one output per channel could be used as one output PWM the normal mode is the default mode for all PWMs (if not specified otherwise). Complementary mode - for PWM channels with two outputs; output waveforms for a PWM channel in complementary mode looks line this: __ __ __ __ PWMH1 __| |__| |__| |__| |__ __ __ __ __ __ PWML1 |__| |__| |__| |__| <--T--> Where T is the signal period. Push-pull mode - for PWM channels with two outputs; output waveforms for a PWM channel in push-pull mode with normal polarity looks like this: __ __ PWMH __| |________| |________ __ __ PWML ________| |________| |__ <--T--> If polarity is inversed: __ ________ ________ PWMH |__| |__| ________ ________ __ PWML |__| |__| <--T--> Where T is the signal period. The PWM working modes are per PWM channel registered as PWM's capabilities. The driver registers itself to PWM core a get_caps() function, in struct pwm_ops, that will be used by PWM core to retrieve PWM capabilities. If this function is not registered in driver's probe, a default function will be used to retrieve PWM capabilities. Currently, the default capabilities includes only PWM normal mode. PWM state has been updated to keep PWM mode. PWM mode could be configured via sysfs or via DT. pwm_apply_state() will do the preliminary validation for PWM mode to be applied. In sysfs, user could get PWM modes by reading mode file of PWM device: root@sama5d2-xplained:/sys/class/pwm/pwmchip0/pwm2# ls -l total 0 -r--r--r-- 1 root root 4096 Oct 9 09:07 capture lrwxrwxrwx 1 root root 0 Oct 9 09:07 device -> ../../pwmchip0 -rw-r--r-- 1 root root 4096 Oct 9 08:42 duty_cycle -rw-r--r-- 1 root root 4096 Oct 9 08:44 enable --w------- 1 root root 4096 Oct 9 09:07 export -rw-r--r-- 1 root root 4096 Oct 9 08:43 mode -r--r--r-- 1 root root 4096 Oct 9 09:07 npwm -rw-r--r-- 1 root root 4096 Oct 9 08:42 period -rw-r--r-- 1 root root 4096 Oct 9 08:44 polarity drwxr-xr-x 2 root root 0 Oct 9 09:07 power lrwxrwxrwx 1 root root 0 Oct 9 09:07 subsystem -> ../../../../../../../../class/pwm -rw-r--r-- 1 root root 4096 Oct 9 08:42 uevent --w------- 1 root root 4096 Oct 9 09:07 unexport root@sama5d2-xplained:/sys/class/pwm/pwmchip0/pwm2# cat mode normal complementary [push-pull] The mode enclosed in bracket is the currently active mode. The mode could be set, via sysfs, by writing to mode file one of the modes displayed at read: root@sama5d2-xplained:/sys/class/pwm/pwmchip0/pwm2# echo normal > mode root@sama5d2-xplained:/sys/class/pwm/pwmchip0/pwm2# cat mode [normal] complementary push-pull The PWM push-pull mode could be usefull in applications like half bridge converters. This series also add support for PWM modes on Atmel/Microchip SoCs. Thank you, Claudiu Beznea [1] https://www.spinics.net/lists/arm-kernel/msg580275.html [2] https://lkml.org/lkml/2018/1/12/359 Changes in v3: - removed changes related to only one of_xlate function for all PWM drivers - switch to PWM capabilities per PWM channel nor per PWM chip - squash documentation and bindings patches as requeted by reviewer - introduced PWM_MODE(name) macro and used a bit enum for pwm modes - related to DT bindings, used flags cell also for PWM modes - updated of_xlate specific functions with "state->mode = mode;" instructions to avoid pwm_apply_state() failures - use available modes for PWM channel in pwm_config() by first calling pwm_get_caps() to get caps.modes - use loops through available modes in mode_store()/mode_show() and also in of_pwm_xlate_with_flags() instead of "if else" instructions; in this way, the addition of a new mode is independent of this code sections - use DTLI=1, DTHI=0 register settings to obtain push-pull mode waveforms for Atmel/Microchip PWM controller. Changes in v2: - remove of_xlate and of_pwm_n_cells and use generic functions to pharse DT inputs; this is done in patches 1, 2, 3, 4, 5, 6, 7 of this series; this will make easy the addition of PWM mode support from DT - add PWM mode normal - register PWM modes as capabilities of PWM chips at driver probe and, in case driver doesn't provide these capabilities use default ones - change the way PWM mode is pharsed via DT by using a new input for pwms binding property Claudiu Beznea (10): pwm: extend PWM framework with PWM modes pwm: clps711x: populate PWM mode in of_xlate function pwm: cros-ec: populate PWM mode in of_xlate function pwm: pxa: populate PWM mode in of_xlate function pwm: add PWM mode to pwm_config() pwm: add PWM modes pwm: atmel: add pwm capabilities pwm: add push-pull mode support pwm: add documentation for pwm push-pull mode pwm: atmel: add push-pull mode support Documentation/devicetree/bindings/pwm/pwm.txt | 11 ++- Documentation/pwm.txt | 42 ++++++++- arch/arm/mach-s3c24xx/mach-rx1950.c | 11 ++- drivers/bus/ts-nbus.c | 2 +- drivers/clk/clk-pwm.c | 3 +- drivers/gpu/drm/i915/intel_panel.c | 17 +++- drivers/hwmon/pwm-fan.c | 2 +- drivers/input/misc/max77693-haptic.c | 2 +- drivers/input/misc/max8997_haptic.c | 6 +- drivers/leds/leds-pwm.c | 5 +- drivers/media/rc/ir-rx51.c | 5 +- drivers/media/rc/pwm-ir-tx.c | 5 +- drivers/pwm/core.c | 98 ++++++++++++++++++++- drivers/pwm/pwm-atmel.c | 118 +++++++++++++++++++------- drivers/pwm/pwm-clps711x.c | 12 ++- drivers/pwm/pwm-cros-ec.c | 4 + drivers/pwm/pwm-pxa.c | 4 + drivers/pwm/sysfs.c | 56 ++++++++++++ drivers/video/backlight/lm3630a_bl.c | 4 +- drivers/video/backlight/lp855x_bl.c | 4 +- drivers/video/backlight/lp8788_bl.c | 5 +- drivers/video/backlight/pwm_bl.c | 11 ++- drivers/video/fbdev/ssd1307fb.c | 3 +- include/dt-bindings/pwm/pwm.h | 2 + include/linux/pwm.h | 100 +++++++++++++++++++++- 25 files changed, 470 insertions(+), 62 deletions(-) -- 2.7.4

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[PATCH v3] bridge: Elaborate a bit on dumb VGA bridges in Kconfig
by Linus Walleij 02 Mar '18

02 Mar '18

It's better if we explain a bit that this pertains to non-programmable VGA DAC bridges. Reviewed-by: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- ChangeLog v2->v3: - Fix wording and commit message. - Collect Laurent's review tag. ChangeLog v1->v2: - Write that these bridges are non-programmable rather than discrete, as that reflects the name of the bridge being "dumb". Discrete is wrong as it has a specific electronic meaning, as in "non-integrated" and this is integrated. --- drivers/gpu/drm/bridge/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 3b99d5a06c16..3aa65bdecb0e 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -30,7 +30,8 @@ config DRM_DUMB_VGA_DAC depends on OF select DRM_KMS_HELPER help - Support for RGB to VGA DAC based bridges + Support for non-programmable RGB to VGA DAC bridges, such as ADI + ADV7123, TI THS8134 and THS8135 or passive resistor ladder DACs. config DRM_LVDS_ENCODER tristate "Transparent parallel to LVDS encoder support" -- 2.14.3

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dri-devel March 2018