dri-devel September 2019

dri-devel@lists.freedesktop.org

315 participants
2278 discussions

[RFC PATCH] drm:- Add a modifier to denote 'protected' framebuffer
by Ayan Halder 01 Oct '19

01 Oct '19

Add a modifier 'DRM_FORMAT_MOD_ARM_PROTECTED' which denotes that the framebuffer is allocated in a protected system memory. Essentially, we want to support EGL_EXT_protected_content in our komeda driver. Signed-off-by: Ayan Kumar Halder <ayan.halder(a)arm.com> /-- Note to reviewer Komeda driver is capable of rendering DRM (Digital Rights Management) protected content. The DRM content is stored in a framebuffer allocated in system memory (which needs some special hardware signals for access). Let us ignore how the protected system memory is allocated and for the scope of this discussion, we want to figure out the best way possible for the userspace to communicate to the drm driver to turn the protected mode on (for accessing the framebuffer with the DRM content) or off. The possible ways by which the userspace could achieve this is via:- 1. Modifiers :- This looks to me the best way by which the userspace can communicate to the kernel to turn the protected mode on for the komeda driver as it is going to access one of the protected framebuffers. The only problem is that the current modifiers describe the tiling/compression format. However, it does not hurt to extend the meaning of modifiers to denote other attributes of the framebuffer as well. The other reason is that on Android, we get an info from Gralloc (GRALLOC_USAGE_PROTECTED) which tells us that the buffer is protected. This can be used to set up the modifier/s (AddFB2) during framebuffer creation. 2. Framebuffer flags :- As of today, this can be one of the two values ie (DRM_MODE_FB_INTERLACED/DRM_MODE_FB_MODIFIERS). Unlike modifiers, the drm framebuffer flags are generic to the drm subsystem and ideally we should not introduce any driver specific constraint/feature. 3. Connector property:- I could see the following properties used for DRM protected content:- DRM_MODE_CONTENT_PROTECTION_DESIRED / ENABLED :- "This property is used by userspace to request the kernel protect future content communicated over the link". Clearly, we are not concerned with the protection attributes of the transmitter. So, we cannot use this property for our case. 4. DRM plane property:- Again, we want to communicate that the framebuffer(which can be attached to any plane) is protected. So introducing a new plane property does not help. 5. DRM crtc property:- For the same reason as above, introducing a new crtc property does not help. --/ --- include/uapi/drm/drm_fourcc.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3f987a..38e5e81d11fe 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -742,6 +742,15 @@ extern "C" { */ #define AFBC_FORMAT_MOD_BCH (1ULL << 11) +/* + * Protected framebuffer + * + * The framebuffer is allocated in a protected system memory which can be accessed + * via some special hardware signals from the dpu. This is used to support + * 'GRALLOC_USAGE_PROTECTED' in our framebuffer for EGL_EXT_protected_content. + */ +#define DRM_FORMAT_MOD_ARM_PROTECTED fourcc_mod_code(ARM, (1ULL << 55)) + /* * Allwinner tiled modifier * -- 2.23.0

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[PATCH 1/4] drm/rect: Add drm_rect_translate_to()
by Ville Syrjala 01 Oct '19

01 Oct '19

From: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Add a helper to translate a rectangle to an absolute position. Signed-off-by: Ville Syrjälä <ville.syrjala(a)linux.intel.com> --- include/drm/drm_rect.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/drm/drm_rect.h b/include/drm/drm_rect.h index 6195820aa5c5..fc7c14627ee2 100644 --- a/include/drm/drm_rect.h +++ b/include/drm/drm_rect.h @@ -106,6 +106,20 @@ static inline void drm_rect_translate(struct drm_rect *r, int dx, int dy) r->y2 += dy; } +/** + * drm_rect_translate_to - translate the rectangle to an absolute position + * @r: rectangle to be tranlated + * @x: horizontal position + * @y: vertical position + * + * Move rectangle @r to @x in the horizontal direction, + * and to @y in the vertical direction. + */ +static inline void drm_rect_translate_to(struct drm_rect *r, int x, int y) +{ + drm_rect_translate(r, x - r->x1, y - r->y1); +} + /** * drm_rect_downscale - downscale a rectangle * @r: rectangle to be downscaled -- 2.21.0

3 5

[PATCH] drm/komeda: Fix FLIP_COMPLETE timestamp on CRTC enable
by Mihail Atanassov 01 Oct '19

01 Oct '19

When initially turning a crtc on, drm_reset_vblank_timestamp will set the vblank timestamp to 0 for any driver that doesn't provide a ->get_vblank_timestamp() hook. Unfortunately, the FLIP_COMPLETE event depends on that timestamp, and the only way to regenerate a valid one is to have vblank interrupts enabled and have a valid in-ISR call to drm_crtc_handle_vblank. Wrap the call to komeda_crtc_do_flush in ->atomic_enable() with a drm_crtc_vblank_{get,put} pair so we can have a vblank ISR prior to the FLIP_COMPLETE ISR (or more likely, they'll get handled in the same ISR, which is equally valid). Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: Liviu Dudau <Liviu.Dudau(a)arm.com> Signed-off-by: Mihail Atanassov <mihail.atanassov(a)arm.com> --- drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index f4400788ab94..87420a767bc4 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -258,7 +258,9 @@ komeda_crtc_atomic_enable(struct drm_crtc *crtc, { komeda_crtc_prepare(to_kcrtc(crtc)); drm_crtc_vblank_on(crtc); + WARN_ON(drm_crtc_vblank_get(crtc)); komeda_crtc_do_flush(crtc, old); + drm_crtc_vblank_put(crtc); } static void -- 2.23.0

3 5

[PATCH 1/2] arm64: dts: juno: add GPU subsystem
by Robin Murphy 01 Oct '19

01 Oct '19

Since we now have bindings for Mali Midgard GPUs, let's use them to describe Juno's GPU subsystem, if only because we can. Juno sports a Mali-T624 integrated behind an MMU-400 (as a gesture towards virtualisation), in their own dedicated power domain with DVFS controlled by the SCP. CC: Liviu Dudau <liviu.dudau(a)arm.com> CC: Sudeep Holla <sudeep.holla(a)arm.com> CC: Lorenzo Pieralisi <lorenzo.pieralisi(a)arm.com> Signed-off-by: Robin Murphy <robin.murphy(a)arm.com> --- .../bindings/gpu/arm,mali-midgard.yaml | 5 +++- arch/arm64/boot/dts/arm/juno-base.dtsi | 27 +++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index 47bc1ac36426..018f3ae4b43c 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -22,6 +22,10 @@ properties: - enum: - amlogic,meson-gxm-mali - const: arm,mali-t820 + - items: + - enum: + - arm,juno-mali + - const: arm,mali-t624 - items: - enum: - rockchip,rk3288-mali @@ -39,7 +43,6 @@ properties: - samsung,exynos5433-mali - const: arm,mali-t760 - # "arm,mali-t624" # "arm,mali-t628" # "arm,mali-t830" # "arm,mali-t880" diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 26a039a028b8..9e3e8ce6adfe 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -35,6 +35,18 @@ clock-names = "apb_pclk"; }; + smmu_gpu: iommu@2b400000 { + compatible = "arm,mmu-400", "arm,smmu-v1"; + reg = <0x0 0x2b400000 0x0 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + #global-interrupts = <1>; + power-domains = <&scpi_devpd 1>; + dma-coherent; + status = "disabled"; + }; + smmu_pcie: iommu@2b500000 { compatible = "arm,mmu-401", "arm,smmu-v1"; reg = <0x0 0x2b500000 0x0 0x10000>; @@ -487,6 +499,21 @@ }; }; + gpu: gpu@2d000000 { + compatible = "arm,juno-mali", "arm,mali-t624"; + reg = <0 0x2d000000 0 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpu", "job", "mmu"; + clocks = <&scpi_dvfs 2>; + power-domains = <&scpi_devpd 1>; + dma-coherent; + /* The SMMU is only really of interest to bare-metal hypervisors */ + /* iommus = <&smmu_gpu 0>; */ + status = "disabled"; + }; + sram: sram@2e000000 { compatible = "arm,juno-sram-ns", "mmio-sram"; reg = <0x0 0x2e000000 0x0 0x8000>; -- 2.21.0.dirty

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[PATCH 00/15] DSC MST support for AMDGPU
by mikita.lipski＠amd.com 01 Oct '19

01 Oct '19

From: Mikita Lipski <mikita.lipski(a)amd.com> This set of patches is a continuation of DSC enablement patches for AMDGPU. This set enables DSC on MST. First 3 patches add atomic check functionality to encoder and connector to allocate and release VCPI slots on each state atomic check. These changes utilize newly added drm_mst_helper functions for better tracking of VCPI slots. Other 12 patches have been introduced in multiple iterations to the mailing list before. These patches were developed by David Francis as part of his work on DSC. David Francis (12): drm/dp_mst: Add PBN calculation for DSC modes drm/dp_mst: Parse FEC capability on MST ports drm/dp_mst: Add MST support to DP DPCD R/W functions drm/dp_mst: Fill branch->num_ports drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux drm/dp_mst: Add new quirk for Synaptics MST hubs drm/amd/display: Use correct helpers to compute timeslots drm/amd/display: Initialize DSC PPS variables to 0 drm/amd/display: Validate DSC caps on MST endpoints drm/amd/display: Write DSC enable to MST DPCD drm/amd/display: MST DSC compute fair share drm/amd/display: Trigger modesets on MST DSC connectors Mikita Lipski (3): drm/amdgpu: Add encoder atomic check drm/amdgpu: Add connector atomic check drm/amdgpu: validate mst topology in atomic check .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 153 ++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 + .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 37 +- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 451 +++++++++++++++++- .../display/amdgpu_dm/amdgpu_dm_mst_types.h | 4 + .../drm/amd/display/dc/core/dc_link_hwss.c | 3 + .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 3 + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +- .../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 + drivers/gpu/drm/drm_dp_aux_dev.c | 12 +- drivers/gpu/drm/drm_dp_helper.c | 34 +- drivers/gpu/drm/drm_dp_mst_topology.c | 174 ++++++- drivers/gpu/drm/i915/intel_dp_mst.c | 3 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_helper.h | 7 + include/drm/drm_dp_mst_helper.h | 8 +- 17 files changed, 866 insertions(+), 39 deletions(-) -- 2.17.1

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[PATCH v3] dt-bindings: gpu: Convert Samsung 2D Graphics Accelerator to dt-schema
by Marek Szyprowski 01 Oct '19

01 Oct '19

From: Maciej Falkowski <m.falkowski(a)samsung.com> Convert Samsung 2D Graphics Accelerator to newer dt-schema format Signed-off-by: Maciej Falkowski <m.falkowski(a)samsung.com> --- v3: - Merged two if-statements with single if-else statement - Added 'additionalProperties: false' - Listed all missing 'properties' in properties scope Best regards, Maciej Falkowski --- .../devicetree/bindings/gpu/samsung-g2d.txt | 27 ------- .../devicetree/bindings/gpu/samsung-g2d.yaml | 75 +++++++++++++++++++ 2 files changed, 75 insertions(+), 27 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpu/samsung-g2d.txt create mode 100644 Documentation/devicetree/bindings/gpu/samsung-g2d.yaml diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt deleted file mode 100644 index 1e7959332dbc..000000000000 --- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Samsung 2D Graphics Accelerator - -Required properties: - - compatible : value should be one among the following: - (a) "samsung,s5pv210-g2d" for G2D IP present in S5PV210 & Exynos4210 SoC - (b) "samsung,exynos4212-g2d" for G2D IP present in Exynos4x12 SoCs - (c) "samsung,exynos5250-g2d" for G2D IP present in Exynos5250 SoC - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : G2D interrupt number to the CPU. - - clocks : from common clock binding: handle to G2D clocks. - - clock-names : names of clocks listed in clocks property, in the same - order, depending on SoC type: - - for S5PV210 and Exynos4 based SoCs: "fimg2d" and - "sclk_fimg2d" - - for Exynos5250 SoC: "fimg2d". - -Example: - g2d@12800000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0x12800000 0x1000>; - interrupts = <0 89 0>; - clocks = <&clock 177>, <&clock 277>; - clock-names = "sclk_fimg2d", "fimg2d"; - }; diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.yaml b/Documentation/devicetree/bindings/gpu/samsung-g2d.yaml new file mode 100644 index 000000000000..e7daae862578 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/samsung-g2d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC 2D Graphics Accelerator + +maintainers: + - Inki Dae <inki.dae(a)samsung.com> + +properties: + compatible: + enum: + - samsung,s5pv210-g2d # in S5PV210 & Exynos4210 SoC + - samsung,exynos4212-g2d # in Exynos4x12 SoCs + - samsung,exynos5250-g2d + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: {} + clock-names: {} + iommus: {} + power-domains: {} + +if: + properties: + compatible: + contains: + const: samsung,exynos5250-g2d + +then: + properties: + clocks: + items: + - description: fimg2d clock + clock-names: + items: + - const: fimg2d + +else: + properties: + clocks: + items: + - description: sclk_fimg2d clock + - description: fimg2d clock + clock-names: + items: + - const: sclk_fimg2d + - const: fimg2d + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + g2d@12800000 { + compatible = "samsung,s5pv210-g2d"; + reg = <0x12800000 0x1000>; + interrupts = <0 89 0>; + clocks = <&clock 177>, <&clock 277>; + clock-names = "sclk_fimg2d", "fimg2d"; + }; + +... -- 2.17.1

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[PATCH v3] dt-bindings: gpu: Convert Samsung Image Scaler to dt-schema
by Marek Szyprowski 01 Oct '19

01 Oct '19

From: Maciej Falkowski <m.falkowski(a)samsung.com> Convert Samsung Image Scaler to newer dt-schema format. Signed-off-by: Maciej Falkowski <m.falkowski(a)samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski(a)samsung.com> --- v3: - Fixed description of 'clocks' property: rather than 'mscl clock', 'pclk clock' - Added empty line within if-else statement - Added 'additionalProperties: false' - Listed all missing 'properties' in properties scope Best regards, Maciej Falkowski --- .../bindings/gpu/samsung-scaler.txt | 27 ------- .../bindings/gpu/samsung-scaler.yaml | 81 +++++++++++++++++++ 2 files changed, 81 insertions(+), 27 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpu/samsung-scaler.txt create mode 100644 Documentation/devicetree/bindings/gpu/samsung-scaler.yaml diff --git a/Documentation/devicetree/bindings/gpu/samsung-scaler.txt b/Documentation/devicetree/bindings/gpu/samsung-scaler.txt deleted file mode 100644 index 9c3d98105dfd..000000000000 --- a/Documentation/devicetree/bindings/gpu/samsung-scaler.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Samsung Exynos Image Scaler - -Required properties: - - compatible : value should be one of the following: - (a) "samsung,exynos5420-scaler" for Scaler IP in Exynos5420 - (b) "samsung,exynos5433-scaler" for Scaler IP in Exynos5433 - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : Interrupt specifier for scaler interrupt, according to format - specific to interrupt parent. - - - clocks : Clock specifier for scaler clock, according to generic clock - bindings. (See Documentation/devicetree/bindings/clock/exynos*.txt) - - - clock-names : Names of clocks. For exynos scaler, it should be "mscl" - on 5420 and "pclk", "aclk" and "aclk_xiu" on 5433. - -Example: - scaler@12800000 { - compatible = "samsung,exynos5420-scaler"; - reg = <0x12800000 0x1294>; - interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MSCL0>; - clock-names = "mscl"; - }; diff --git a/Documentation/devicetree/bindings/gpu/samsung-scaler.yaml b/Documentation/devicetree/bindings/gpu/samsung-scaler.yaml new file mode 100644 index 000000000000..5317ac64426a --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/samsung-scaler.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/samsung-scaler.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC Image Scaler + +maintainers: + - Inki Dae <inki.dae(a)samsung.com> + +properties: + compatible: + enum: + - samsung,exynos5420-scaler + - samsung,exynos5433-scaler + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: {} + clock-names: {} + iommus: {} + power-domains: {} + +if: + properties: + compatible: + contains: + const: samsung,exynos5420-scaler + +then: + properties: + clocks: + items: + - description: mscl clock + + clock-names: + items: + - const: mscl + +else: + properties: + clocks: + items: + - description: pclk clock + - description: aclk clock + - description: aclk_xiu clock + + clock-names: + items: + - const: pclk + - const: aclk + - const: aclk_xiu + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5420.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + scaler@12800000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12800000 0x1294>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL0>; + clock-names = "mscl"; + }; + +... -- 2.17.1

4 3

[PATCH] Staging: fbtft: fix memory leak in fbtft_framebuffer_alloc
by Navid Emamdoost 01 Oct '19

01 Oct '19

In fbtft_framebuffer_alloc the error handling path should take care of releasing frame buffer after it is allocated via framebuffer_alloc, too. Therefore, in two failure cases the goto destination is changed to address this issue. Fixes: c296d5f9957c ("staging: fbtft: core support") Signed-off-by: Navid Emamdoost <navid.emamdoost(a)gmail.com> --- drivers/staging/fbtft/fbtft-core.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/staging/fbtft/fbtft-core.c b/drivers/staging/fbtft/fbtft-core.c index cf5700a2ea66..a0a67aa517f0 100644 --- a/drivers/staging/fbtft/fbtft-core.c +++ b/drivers/staging/fbtft/fbtft-core.c @@ -714,7 +714,7 @@ struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display, if (par->gamma.curves && gamma) { if (fbtft_gamma_parse_str(par, par->gamma.curves, gamma, strlen(gamma))) - goto alloc_fail; + goto release_framebuf; } /* Transmit buffer */ @@ -731,7 +731,7 @@ struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display, if (txbuflen > 0) { txbuf = devm_kzalloc(par->info->device, txbuflen, GFP_KERNEL); if (!txbuf) - goto alloc_fail; + goto release_framebuf; par->txbuf.buf = txbuf; par->txbuf.len = txbuflen; } @@ -753,6 +753,9 @@ struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display, return info; +release_framebuf: + framebuffer_release(info); + alloc_fail: vfree(vmem); -- 2.17.1

2 1

[PATCH] drm/omap: Migrate minimum FCK/PCK ratio from Kconfig to dts
by Adam Ford 01 Oct '19

01 Oct '19

Currently the source code is compiled using hard-coded values from CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK. This patch allows this clock divider value to be moved to the device tree and be changed without having to recompile the kernel. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt index cd02516a40b6..42449d07c47e 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt +++ b/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt @@ -40,7 +40,7 @@ Required properties: Optional properties: - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit in bytes per second - +- min-fck-pck-ratio: Make sure that DISPC FCK is at least n x PCK RFBI ---- diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 4043ecb38016..bf84a8487aae 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -751,7 +751,7 @@ #size-cells = <1>; ranges; - dispc@48050400 { + dispc: dispc@48050400 { compatible = "ti,omap3-dispc"; reg = <0x48050400 0x400>; interrupts = <25>; diff --git a/drivers/gpu/drm/omapdrm/dss/Kconfig b/drivers/gpu/drm/omapdrm/dss/Kconfig index f24ebf7f61dd..d0666edcdf2a 100644 --- a/drivers/gpu/drm/omapdrm/dss/Kconfig +++ b/drivers/gpu/drm/omapdrm/dss/Kconfig @@ -102,24 +102,6 @@ config OMAP2_DSS_DSI See http://www.mipi.org/ for DSI specifications. -config OMAP2_DSS_MIN_FCK_PER_PCK - int "Minimum FCK/PCK ratio (for scaling)" - range 0 32 - default 0 - help - This can be used to adjust the minimum FCK/PCK ratio. - - With this you can make sure that DISPC FCK is at least - n x PCK. Video plane scaling requires higher FCK than - normally. - - If this is set to 0, there's no extra constraint on the - DISPC FCK. However, the FCK will at minimum be - 2xPCK (if active matrix) or 3xPCK (if passive matrix). - - Max FCK is 173MHz, so this doesn't work if your PCK - is very high. - config OMAP2_DSS_SLEEP_AFTER_VENC_RESET bool "Sleep 20ms after VENC reset" default y diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index ba82d916719c..09a130c53da2 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -198,6 +198,9 @@ struct dispc_device { /* DISPC_CONTROL & DISPC_CONFIG lock*/ spinlock_t control_lock; + + /* Optional min-fck-pck-ratio */ + u32 min_fck_per_pck; }; enum omap_color_component { @@ -3683,15 +3686,8 @@ bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, unsigned long pck, lck; unsigned long lck_max; unsigned long pckd_hw_min, pckd_hw_max; - unsigned int min_fck_per_pck; unsigned long fck; -#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK - min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; -#else - min_fck_per_pck = 0; -#endif - pckd_hw_min = dispc->feat->min_pcd; pckd_hw_max = 255; @@ -3723,7 +3719,7 @@ bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, else fck = lck; - if (fck < pck * min_fck_per_pck) + if (fck < pck * dispc->min_fck_per_pck) continue; if (func(lckd, pckd, lck, pck, data)) @@ -4826,6 +4822,8 @@ static int dispc_bind(struct device *dev, struct device *master, void *data) } } + of_property_read_u32(np, "min-fck-pck-ratio", &dispc->min_fck_per_pck); + r = dispc_init_gamma_tables(dispc); if (r) goto err_free; -- 2.17.1

6 39

[PATCH] drm/i915/dp: Fix DP MST error after unplugging TypeC cable
by srinivasan.s＠intel.com 01 Oct '19

01 Oct '19

From: Srinivasan S <srinivasan.s(a)intel.com> This patch avoids DP MST payload error message in dmesg, as it is trying to update the payload to the disconnected DP MST device. After DP MST device is disconnected we should not be updating the payload and hence remove the error. v2: Removed the connector status check and converted from error to debug. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111632 Signed-off-by: Srinivasan S <srinivasan.s(a)intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index eeeb3f933aa4..497a6ae0d2c0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -215,7 +215,7 @@ static void intel_mst_disable_dp(struct intel_encoder *encoder, ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); if (ret) { - DRM_ERROR("failed to update payload %d\n", ret); + DRM_DEBUG_KMS("failed to update payload %d\n", ret); } if (old_crtc_state->has_audio) intel_audio_codec_disable(encoder, -- 2.7.4

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dri-devel September 2019