dri-devel September 2019

dri-devel@lists.freedesktop.org

315 participants
2278 discussions

[PATCH] drm/komeda: Use IRQ_RETVAL shorthand in d71_irq_handler
by Mihail Atanassov 01 Oct '19

01 Oct '19

No change in behaviour; IRQ_RETVAL is about twice as popular as manually writing out the ternary. Signed-off-by: Mihail Atanassov <mihail.atanassov(a)arm.com> --- drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c index d567ab7ed314..1b42095969e7 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c @@ -195,7 +195,7 @@ d71_irq_handler(struct komeda_dev *mdev, struct komeda_events *evts) if (gcu_status & GLB_IRQ_STATUS_PIPE1) evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status); - return gcu_status ? IRQ_HANDLED : IRQ_NONE; + return IRQ_RETVAL(gcu_status); } #define ENABLED_GCU_IRQS (GCU_IRQ_CVAL0 | GCU_IRQ_CVAL1 | \ -- 2.23.0

3 2

[PATCH] drm/meson: enable runtime PM
by Kevin Hilman 01 Oct '19

01 Oct '19

From: Kevin Hilman <khilman(a)baylibre.com> On some SoCs, the VPU is in a power-domain and needs runtime PM enabled and used in order to keep the power domain on. Signed-off-by: Kevin Hilman <khilman(a)baylibre.com> --- drivers/gpu/drm/meson/meson_drv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index 2310c96fff46..256b6a0e9c6b 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -14,6 +14,7 @@ #include <linux/platform_device.h> #include <linux/component.h> #include <linux/of_graph.h> +#include <linux/pm_runtime.h> #include <drm/drmP.h> #include <drm/drm_atomic.h> @@ -274,6 +275,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) /* Hardware Initialization */ + pm_runtime_get_sync(dev); meson_vpu_init(priv); meson_venc_init(priv); meson_vpp_init(priv); @@ -416,6 +418,7 @@ static int meson_drv_probe(struct platform_device *pdev) struct device_node *ep, *remote; int count = 0; + pm_runtime_enable(&pdev->dev); for_each_endpoint_of_node(np, ep) { remote = of_graph_get_remote_port_parent(ep); if (!remote || !of_device_is_available(remote)) { @@ -440,6 +443,7 @@ static int meson_drv_probe(struct platform_device *pdev) } /* If no output endpoints were available, simply bail out */ + pm_runtime_disable(&pdev->dev); return 0; }; -- 2.22.0

3 3

[PATCH] drm/ttm: move cpu_writers handling into vmwgfx v2
by Christian König 01 Oct '19

01 Oct '19

From: Christian König <ckoenig.leichtzumerken(a)gmail.com> This feature is only used by vmwgfx and superflous for everybody else. v2: use vmw_buffer_object instead of vmw_user_bo. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/gpu/drm/ttm/ttm_bo.c | 27 ---------------------- drivers/gpu/drm/ttm/ttm_bo_util.c | 1 - drivers/gpu/drm/ttm/ttm_execbuf_util.c | 7 +----- drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 36 +++++++++++++++++++++++++----- drivers/gpu/drm/vmwgfx/vmwgfx_drv.h | 2 ++ drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 8 +++++++ drivers/gpu/drm/vmwgfx/vmwgfx_resource.c | 4 ++++ drivers/gpu/drm/vmwgfx/vmwgfx_validation.c | 4 ++++ include/drm/ttm/ttm_bo_api.h | 31 ------------------------- 9 files changed, 49 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 881cf26d698e..a9aaecdd7481 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -153,7 +153,6 @@ static void ttm_bo_release_list(struct kref *list_kref) BUG_ON(kref_read(&bo->list_kref)); BUG_ON(kref_read(&bo->kref)); - BUG_ON(atomic_read(&bo->cpu_writers)); BUG_ON(bo->mem.mm_node != NULL); BUG_ON(!list_empty(&bo->lru)); BUG_ON(!list_empty(&bo->ddestroy)); @@ -1311,7 +1310,6 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev, kref_init(&bo->kref); kref_init(&bo->list_kref); - atomic_set(&bo->cpu_writers, 0); INIT_LIST_HEAD(&bo->lru); INIT_LIST_HEAD(&bo->ddestroy); INIT_LIST_HEAD(&bo->swap); @@ -1823,31 +1821,6 @@ int ttm_bo_wait(struct ttm_buffer_object *bo, } EXPORT_SYMBOL(ttm_bo_wait); -int ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait) -{ - int ret = 0; - - /* - * Using ttm_bo_reserve makes sure the lru lists are updated. - */ - - ret = ttm_bo_reserve(bo, true, no_wait, NULL); - if (unlikely(ret != 0)) - return ret; - ret = ttm_bo_wait(bo, true, no_wait); - if (likely(ret == 0)) - atomic_inc(&bo->cpu_writers); - ttm_bo_unreserve(bo); - return ret; -} -EXPORT_SYMBOL(ttm_bo_synccpu_write_grab); - -void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo) -{ - atomic_dec(&bo->cpu_writers); -} -EXPORT_SYMBOL(ttm_bo_synccpu_write_release); - /** * A buffer object shrink method that tries to swap out the first * buffer object on the bo_global::swap_lru list. diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index fe81c565e7ef..b00039dcb487 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -511,7 +511,6 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, mutex_init(&fbo->base.wu_mutex); fbo->base.moving = NULL; drm_vma_node_reset(&fbo->base.base.vma_node); - atomic_set(&fbo->base.cpu_writers, 0); kref_init(&fbo->base.list_kref); kref_init(&fbo->base.kref); diff --git a/drivers/gpu/drm/ttm/ttm_execbuf_util.c b/drivers/gpu/drm/ttm/ttm_execbuf_util.c index 131dae8f4170..0519e1b5a49c 100644 --- a/drivers/gpu/drm/ttm/ttm_execbuf_util.c +++ b/drivers/gpu/drm/ttm/ttm_execbuf_util.c @@ -113,12 +113,7 @@ int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket, struct ttm_buffer_object *bo = entry->bo; ret = __ttm_bo_reserve(bo, intr, (ticket == NULL), ticket); - if (!ret && unlikely(atomic_read(&bo->cpu_writers) > 0)) { - dma_resv_unlock(bo->base.resv); - - ret = -EBUSY; - - } else if (ret == -EALREADY && dups) { + if (ret == -EALREADY && dups) { struct ttm_validate_buffer *safe = entry; entry = list_prev_entry(entry, head); list_del(&safe->head); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c index a05ef9d0a2e7..5ddd2573b64c 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c @@ -76,6 +76,26 @@ vmw_user_buffer_object(struct ttm_buffer_object *bo) return container_of(vmw_bo, struct vmw_user_buffer_object, vbo); } +/** + * vmw_bo_verify_synccpu - Verify if grab for CPU access exists + * + * @list: list of ttm_validate_buffer objects + * + * Return: + * -EBUSY if a CPU grab is found, 0 otherwise. + */ +int vmw_bo_verify_synccpu(struct list_head *list) +{ + struct ttm_validate_buffer *entry; + + list_for_each_entry(entry, list, head) { + struct vmw_buffer_object *bo = vmw_buffer_object(entry->bo); + + if (unlikely(atomic_read(&bo->cpu_writers) > 0)) + return -EBUSY; + } + return 0; +} /** * vmw_bo_pin_in_placement - Validate a buffer to placement. @@ -565,7 +585,7 @@ static void vmw_user_bo_ref_obj_release(struct ttm_base_object *base, switch (ref_type) { case TTM_REF_SYNCCPU_WRITE: - ttm_bo_synccpu_write_release(&user_bo->vbo.base); + atomic_dec(&user_bo->vbo.cpu_writers); break; default: WARN_ONCE(true, "Undefined buffer object reference release.\n"); @@ -681,12 +701,12 @@ static int vmw_user_bo_synccpu_grab(struct vmw_user_buffer_object *user_bo, struct ttm_object_file *tfile, uint32_t flags) { + bool nonblock = !!(flags & drm_vmw_synccpu_dontblock); struct ttm_buffer_object *bo = &user_bo->vbo.base; bool existed; int ret; if (flags & drm_vmw_synccpu_allow_cs) { - bool nonblock = !!(flags & drm_vmw_synccpu_dontblock); long lret; lret = dma_resv_wait_timeout_rcu @@ -699,15 +719,20 @@ static int vmw_user_bo_synccpu_grab(struct vmw_user_buffer_object *user_bo, return 0; } - ret = ttm_bo_synccpu_write_grab - (bo, !!(flags & drm_vmw_synccpu_dontblock)); + ret = ttm_bo_reserve(bo, true, nonblock, NULL); + if (unlikely(ret != 0)) + return ret; + ret = ttm_bo_wait(bo, true, nonblock); + if (likely(ret == 0)) + atomic_inc(&user_bo->vbo.cpu_writers); + ttm_bo_unreserve(bo); if (unlikely(ret != 0)) return ret; ret = ttm_ref_object_add(tfile, &user_bo->prime.base, TTM_REF_SYNCCPU_WRITE, &existed, false); if (ret != 0 || existed) - ttm_bo_synccpu_write_release(&user_bo->vbo.base); + atomic_dec(&user_bo->vbo.cpu_writers); return ret; } @@ -731,7 +756,6 @@ static int vmw_user_bo_synccpu_release(uint32_t handle, return 0; } - /** * vmw_user_bo_synccpu_ioctl - ioctl function implementing the synccpu * functionality. diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h index adb0436528c7..894ed804186d 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h @@ -90,6 +90,7 @@ struct vmw_buffer_object { struct ttm_buffer_object base; struct list_head res_list; s32 pin_count; + atomic_t cpu_writers; /* Not ref-counted. Protected by binding_mutex */ struct vmw_resource *dx_query_ctx; /* Protected by reservation */ @@ -773,6 +774,7 @@ extern void vmw_bo_move_notify(struct ttm_buffer_object *bo, extern void vmw_bo_swap_notify(struct ttm_buffer_object *bo); extern struct vmw_buffer_object * vmw_user_bo_noref_lookup(struct ttm_object_file *tfile, u32 handle); +extern int vmw_bo_verify_synccpu(struct list_head *list); /** * vmw_user_bo_noref_release - release a buffer object pointer looked up diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c index ff86d49dc5e8..0738436b90ee 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c @@ -3737,6 +3737,10 @@ int vmw_execbuf_process(struct drm_file *file_priv, if (unlikely(ret != 0)) goto out_err_nores; + ret = vmw_bo_verify_synccpu(&val_ctx.bo_list); + if (unlikely(ret != 0)) + goto out_err; + ret = vmw_validation_bo_validate(&val_ctx, true); if (unlikely(ret != 0)) goto out_err; @@ -3936,6 +3940,10 @@ void __vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv, if (ret) goto out_no_reserve; + ret = vmw_bo_verify_synccpu(&val_ctx.bo_list); + if (unlikely(ret != 0)) + goto out_no_emit; + if (dev_priv->query_cid_valid) { BUG_ON(fence != NULL); ret = vmw_fifo_emit_dummy_query(dev_priv, dev_priv->query_cid); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c index 0b5472450633..b496ce5c1735 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c @@ -469,6 +469,10 @@ vmw_resource_check_buffer(struct ww_acquire_ctx *ticket, if (unlikely(ret != 0)) goto out_no_reserve; + ret = vmw_bo_verify_synccpu(&val_list); + if (unlikely(ret != 0)) + goto out_no_validate; + if (res->func->needs_backup && list_empty(&res->mob_head)) return 0; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_validation.c b/drivers/gpu/drm/vmwgfx/vmwgfx_validation.c index f611b2290a1b..a7beaec91f56 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_validation.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_validation.c @@ -725,6 +725,10 @@ int vmw_validation_prepare(struct vmw_validation_context *ctx, if (ret) goto out_no_bo_reserve; + ret = vmw_bo_verify_synccpu(&ctx->bo_list); + if (unlikely(ret != 0)) + goto out_no_validate; + ret = vmw_validation_bo_validate(ctx, intr); if (ret) goto out_no_validate; diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index 43c4929a2171..1d623c140f07 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -147,7 +147,6 @@ struct ttm_tt; * holds a pointer to a persistent shmem object. * @ttm: TTM structure holding system pages. * @evicted: Whether the object was evicted without user-space knowing. - * @cpu_writes: For synchronization. Number of cpu writers. * @lru: List head for the lru list. * @ddestroy: List head for the delayed destroy list. * @swap: List head for swap LRU list. @@ -198,11 +197,6 @@ struct ttm_buffer_object { struct ttm_tt *ttm; bool evicted; - /** - * Members protected by the bo::reserved lock only when written to. - */ - - atomic_t cpu_writers; /** * Members protected by the bdev::lru_lock. @@ -441,31 +435,6 @@ void ttm_bo_unlock_delayed_workqueue(struct ttm_bo_device *bdev, int resched); bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, const struct ttm_place *place); -/** - * ttm_bo_synccpu_write_grab - * - * @bo: The buffer object: - * @no_wait: Return immediately if buffer is busy. - * - * Synchronizes a buffer object for CPU RW access. This means - * command submission that affects the buffer will return -EBUSY - * until ttm_bo_synccpu_write_release is called. - * - * Returns - * -EBUSY if the buffer is busy and no_wait is true. - * -ERESTARTSYS if interrupted by a signal. - */ -int ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait); - -/** - * ttm_bo_synccpu_write_release: - * - * @bo : The buffer object. - * - * Releases a synccpu lock. - */ -void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo); - /** * ttm_bo_acc_size * -- 2.14.1

2 1

[PATCH v3 00/37] Introduce memory region concept (including device local memory)
by Matthew Auld 01 Oct '19

01 Oct '19

In preparation for upcoming devices with device local memory, introduce the concept of different memory regions, and a simple buddy allocator to manage them in i915. One of the concerns raised from v1 was around not using enough of TTM, which is a fair criticism, so trying to get better alignment here is something we are investigating, though currently that is still WIP so in the meantime v3 still continues to push more of the low-level details forward, but not yet the TTM interactions. Sidenote: Daniel raised a fair point with the whole mmap_offset uAPI and whether we can just get away with using gtt_mmap, it looks like it should work and would simplify a few things and possibly allow us to drop a couple patches. Thoughts? Abdiel Janulgue (11): drm/i915: Add memory region information to device_info drm/i915: setup io-mapping for LMEM drm/i915/lmem: support kernel mapping drm/i915: enumerate and init each supported region drm/i915: Allow i915 to manage the vma offset nodes instead of drm core drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET drm/i915/lmem: add helper to get CPU accessible offset drm/i915: Add cpu and lmem fault handlers drm/i915: cpu-map based dumb buffers drm/i915: Introduce GEM_OBJECT_SETPARAM with I915_PARAM_MEMORY_REGION drm/i915/query: Expose memory regions through the query uAPI CQ Tang (1): drm/i915: check for missing aperture in insert_mappable_node Daniele Ceraolo Spurio (4): drm/i915: define HAS_MAPPABLE_APERTURE drm/i915: do not map aperture if it is not available. drm/i915: set num_fence_regs to 0 if there is no aperture drm/i915: error capture with no ggtt slot Matthew Auld (20): drm/i915: buddy allocator drm/i915: introduce intel_memory_region drm/i915/region: support basic eviction drm/i915/region: support continuous allocations drm/i915/region: support volatile objects drm/i915: support creating LMEM objects drm/i915/blt: don't assume pinned intel_context drm/i915/blt: bump size restriction drm/i915/blt: support copying objects drm/i915/selftests: move gpu-write-dw into utils drm/i915/selftests: add write-dword test for LMEM drm/i915/selftest: extend coverage to include LMEM huge-pages drm/i915/lmem: support CPU relocations drm/i915/lmem: support pread drm/i915/lmem: support pwrite drm/i915: treat shmem as a region drm/i915: treat stolen as a region drm/i915/selftests: check for missing aperture drm/i915: support basic object migration HAX drm/i915: add the fake lmem region Michal Wajdeczko (1): drm/i915: Don't try to place HWS in non-existing mappable region arch/x86/kernel/early-quirks.c | 26 + drivers/gpu/drm/i915/Makefile | 5 + .../gpu/drm/i915/gem/i915_gem_client_blt.c | 34 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 + drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 + .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 55 +- drivers/gpu/drm/i915/gem/i915_gem_internal.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | 4 + drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 315 +++++++ drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 37 + drivers/gpu/drm/i915/gem/i915_gem_mman.c | 376 +++++++- drivers/gpu/drm/i915/gem/i915_gem_object.c | 271 ++++++ drivers/gpu/drm/i915/gem/i915_gem_object.h | 29 +- .../gpu/drm/i915/gem/i915_gem_object_blt.c | 349 +++++++- .../gpu/drm/i915/gem/i915_gem_object_blt.h | 18 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 48 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 28 +- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_region.c | 165 ++++ drivers/gpu/drm/i915/gem/i915_gem_region.h | 29 + drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 71 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 71 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 3 +- .../drm/i915/gem/selftests/huge_gem_object.c | 4 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 331 ++++--- .../i915/gem/selftests/i915_gem_client_blt.c | 16 +- .../i915/gem/selftests/i915_gem_coherency.c | 5 +- .../drm/i915/gem/selftests/i915_gem_context.c | 134 +-- .../drm/i915/gem/selftests/i915_gem_mman.c | 15 +- .../i915/gem/selftests/i915_gem_object_blt.c | 128 ++- .../drm/i915/gem/selftests/igt_gem_utils.c | 135 +++ .../drm/i915/gem/selftests/igt_gem_utils.h | 16 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 5 +- drivers/gpu/drm/i915/gt/intel_reset.c | 13 +- drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 +- drivers/gpu/drm/i915/i915_buddy.c | 433 ++++++++++ drivers/gpu/drm/i915/i915_buddy.h | 128 +++ drivers/gpu/drm/i915/i915_drv.c | 28 +- drivers/gpu/drm/i915/i915_drv.h | 20 +- drivers/gpu/drm/i915/i915_gem.c | 41 +- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 121 ++- drivers/gpu/drm/i915/i915_getparam.c | 1 + drivers/gpu/drm/i915/i915_globals.c | 1 + drivers/gpu/drm/i915/i915_globals.h | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 64 +- drivers/gpu/drm/i915/i915_pci.c | 29 +- drivers/gpu/drm/i915/i915_query.c | 57 ++ drivers/gpu/drm/i915/i915_vma.c | 21 +- drivers/gpu/drm/i915/intel_device_info.h | 2 + drivers/gpu/drm/i915/intel_memory_region.c | 240 +++++ drivers/gpu/drm/i915/intel_memory_region.h | 116 +++ drivers/gpu/drm/i915/intel_region_lmem.c | 141 +++ drivers/gpu/drm/i915/intel_region_lmem.h | 16 + drivers/gpu/drm/i915/selftests/i915_buddy.c | 719 +++++++++++++++ drivers/gpu/drm/i915/selftests/i915_gem.c | 3 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 8 +- .../drm/i915/selftests/i915_live_selftests.h | 1 + .../drm/i915/selftests/i915_mock_selftests.h | 2 + .../drm/i915/selftests/intel_memory_region.c | 817 ++++++++++++++++++ .../gpu/drm/i915/selftests/mock_gem_device.c | 9 +- drivers/gpu/drm/i915/selftests/mock_region.c | 64 ++ drivers/gpu/drm/i915/selftests/mock_region.h | 16 + include/drm/i915_drm.h | 3 + include/uapi/drm/i915_drm.h | 93 ++ 67 files changed, 5524 insertions(+), 477 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.h create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.h create mode 100644 drivers/gpu/drm/i915/i915_buddy.c create mode 100644 drivers/gpu/drm/i915/i915_buddy.h create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.c create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.h create mode 100644 drivers/gpu/drm/i915/selftests/i915_buddy.c create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h -- 2.20.1

7 65

[PATCH] drm/i915/dp: Fix DP MST error after unplugging TypeC cable
by srinivasan.s＠intel.com 30 Sep '19

30 Sep '19

From: Srinivasan S <srinivasan.s(a)intel.com> This patch avoids DP MST payload error message in dmesg, as it is trying to read the payload from the disconnected DP MST device. After the unplug the connector status is disconnected and we should not be looking for the payload and hence remove the error and throw the warning. This details can be found in: https://bugs.freedesktop.org/show_bug.cgi?id=111632 Signed-off-by: Srinivasan S <srinivasan.s(a)intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index eeeb3f933aa4..5b2278fdf675 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -215,7 +215,12 @@ static void intel_mst_disable_dp(struct intel_encoder *encoder, ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); if (ret) { - DRM_ERROR("failed to update payload %d\n", ret); + if (!connector || + connector->base.status != connector_status_connected) { + DRM_WARN("DP MST disconnect\n"); + } else { + DRM_ERROR("failed to update payload %d\n", ret); + } } if (old_crtc_state->has_audio) intel_audio_codec_disable(encoder, -- 2.7.4

5 9

[RFC PATCH] pci: prevent putting pcie devices into lower device states on certain intel bridges
by Karol Herbst 30 Sep '19

30 Sep '19

Fixes state transitions of Nvidia Pascal GPUs from D3cold into higher device states. v2: convert to pci_dev quirk put a proper technical explenation of the issue as a in-code comment RFC comment (copied from last sent): We are quite sure that there is a higher amount of bridges affected by this, but I was only testing it on my own machine for now. I've stresstested runpm by doing 5000 runpm cycles with that patch applied and never saw it fail. I mainly wanted to get a discussion going on if that's a feasable workaround indeed or if we need something better. I am also sure, that the nouveau driver itself isn't at fault as I am able to reproduce the same issue by poking into some PCI registers on the PCIe bridge to put the GPU into D3cold as it's done in ACPI code. I've written a little python script to reproduce this issue without the need of loading nouveau: https://raw.githubusercontent.com/karolherbst/pci-stub-runpm/master/nv_runp… Signed-off-by: Karol Herbst <kherbst(a)redhat.com> Cc: Bjorn Helgaas <bhelgaas(a)google.com> Cc: Lyude Paul <lyude(a)redhat.com> Cc: Rafael J. Wysocki <rjw(a)rjwysocki.net> Cc: Mika Westerberg <mika.westerberg(a)intel.com> Cc: linux-pci(a)vger.kernel.org Cc: linux-pm(a)vger.kernel.org Cc: dri-devel(a)lists.freedesktop.org Cc: nouveau(a)lists.freedesktop.org --- drivers/pci/pci.c | 11 ++++++++++ drivers/pci/quirks.c | 50 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 1 + 3 files changed, 62 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 088fcdc8d2b4..65516b024ee5 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -799,6 +799,13 @@ static inline bool platform_pci_bridge_d3(struct pci_dev *dev) return pci_platform_pm ? pci_platform_pm->bridge_d3(dev) : false; } +static inline bool parent_broken_child_pm(struct pci_dev *dev) +{ + if (!dev->bus || !dev->bus->self) + return false; + return dev->bus->self->broken_child_pm; +} + /** * pci_raw_set_power_state - Use PCI PM registers to set the power state of * given PCI device @@ -844,6 +851,10 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) || (state == PCI_D2 && !dev->d2_support)) return -EIO; + /* check if the bus controller causes issues */ + if (state != PCI_D0 && parent_broken_child_pm(dev)) + return 0; + pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); /* diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 0f16acc323c6..2be0deec2c3d 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5198,3 +5198,53 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, PCI_CLASS_DISPLAY_VGA, 8, quirk_reset_lenovo_thinkpad_p50_nvgpu); + +/* + * Some Intel PCIe bridges cause devices to disappear from the PCIe bus after + * those were put into D3cold state if they were put into a non D0 PCI PM + * device state before doing so. + * + * This leads to various issue different issues which all manifest differently, + * but have the same root cause: + * - AIML code execution hits an infinite loop (as the coe waits on device + * memory to change). + * - kernel crashes, as all pci reads return -1, which most code isn't able + * to handle well enough. + * - sudden shutdowns, as the kernel identified an unrecoverable error after + * userspace tries to access the GPU. + * + * In all cases dmesg will contain at least one line like this: + * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3' + * followed by a lot of nouveau timeouts. + * + * ACPI code writes bit 0x80 to the not documented PCI register 0x248 of the + * PCIe bridge controller in order to power down the GPU. + * Nonetheless, there are other code paths inside the ACPI firmware which use + * other registers, which seem to work fine: + * - 0xbc bit 0x20 (publicly available documentation claims 'reserved') + * - 0xb0 bit 0x10 (link disable) + * Changing the conditions inside the firmware by poking into the relevant + * addresses does resolve the issue, but it seemed to be ACPI private memory + * and not any device accessible memory at all, so there is no portable way of + * changing the conditions. + * + * The only systems where this behavior can be seen are hybrid graphics laptops + * with a secondary Nvidia Pascal GPU. It cannot be ruled out that this issue + * only occurs in combination with listed Intel PCIe bridge controllers and + * the mentioned GPUs or if it's only a hw bug in the bridge controller. + * + * But because this issue was NOT seen on laptops with an Nvidia Pascal GPU + * and an Intel Coffee Lake SoC, there is a higher chance of there being a bug + * in the bridge controller rather than in the GPU. + * + * This issue was not able to be reproduced on non laptop systems. + */ + +static void quirk_broken_child_pm(struct pci_dev *dev) +{ + dev->broken_child_pm = 1; + printk("applied broken child pm quirk!\n"); +} +/* kaby lake */ +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1901, + quirk_broken_child_pm); diff --git a/include/linux/pci.h b/include/linux/pci.h index dd436da7eccc..01eb0a9e6c13 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -413,6 +413,7 @@ struct pci_dev { unsigned int __aer_firmware_first_valid:1; unsigned int __aer_firmware_first:1; unsigned int broken_intx_masking:1; /* INTx masking can't be used */ + unsigned int broken_child_pm:1; /* children put into lower PCI PM states won't recover after D3cold transition */ unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ unsigned int irq_managed:1; unsigned int has_secondary_link:1; -- 2.21.0

1 0

[PATCH] ARM: dts: am4372: Set memory bandwidth limit for DISPC
by Tomi Valkeinen 30 Sep '19

30 Sep '19

From: Peter Ujfalusi <peter.ujfalusi(a)ti.com> Set memory bandwidth limit to filter out resolutions above 720p@60Hz to avoid underflow errors due to the bandwidth needs of higher resolutions. am43xx can not provide enough bandwidth to DISPC to correctly handle 'high' resolutions. Signed-off-by: Peter Ujfalusi <peter.ujfalusi(a)ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen(a)ti.com> --- arch/arm/boot/dts/am4372.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 848e2a8884e2..14bbc438055f 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -337,6 +337,8 @@ ti,hwmods = "dss_dispc"; clocks = <&disp_clk>; clock-names = "fck"; + + max-memory-bandwidth = <230000000>; }; rfbi: rfbi@4832a800 { -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

2 1

[PATCH 1/2] drm/qxl: stop abusing TTM to call driver internal functions
by Christian König 30 Sep '19

30 Sep '19

The ttm_mem_io_* functions are actually internal to TTM and shouldn't be used in a driver. Instead call the qxl_ttm_io_mem_reserve() function directly. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/gpu/drm/qxl/qxl_drv.h | 2 ++ drivers/gpu/drm/qxl/qxl_object.c | 11 +---------- drivers/gpu/drm/qxl/qxl_ttm.c | 4 ++-- 3 files changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h index 9e034c5fa87d..8a24f8e101da 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.h +++ b/drivers/gpu/drm/qxl/qxl_drv.h @@ -354,6 +354,8 @@ int qxl_mode_dumb_mmap(struct drm_file *filp, /* qxl ttm */ int qxl_ttm_init(struct qxl_device *qdev); void qxl_ttm_fini(struct qxl_device *qdev); +int qxl_ttm_io_mem_reserve(struct ttm_bo_device *bdev, + struct ttm_mem_reg *mem); int qxl_mmap(struct file *filp, struct vm_area_struct *vma); /* qxl image */ diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c index 548dfe6f3b26..299e63a951c5 100644 --- a/drivers/gpu/drm/qxl/qxl_object.c +++ b/drivers/gpu/drm/qxl/qxl_object.c @@ -148,7 +148,6 @@ int qxl_bo_kmap(struct qxl_bo *bo, void **ptr) void *qxl_bo_kmap_atomic_page(struct qxl_device *qdev, struct qxl_bo *bo, int page_offset) { - struct ttm_mem_type_manager *man = &bo->tbo.bdev->man[bo->tbo.mem.mem_type]; void *rptr; int ret; struct io_mapping *map; @@ -160,9 +159,7 @@ void *qxl_bo_kmap_atomic_page(struct qxl_device *qdev, else goto fallback; - (void) ttm_mem_io_lock(man, false); - ret = ttm_mem_io_reserve(bo->tbo.bdev, &bo->tbo.mem); - ttm_mem_io_unlock(man); + ret = qxl_ttm_io_mem_reserve(bo->tbo.bdev, &bo->tbo.mem); return io_mapping_map_atomic_wc(map, bo->tbo.mem.bus.offset + page_offset); fallback: @@ -193,17 +190,11 @@ void qxl_bo_kunmap(struct qxl_bo *bo) void qxl_bo_kunmap_atomic_page(struct qxl_device *qdev, struct qxl_bo *bo, void *pmap) { - struct ttm_mem_type_manager *man = &bo->tbo.bdev->man[bo->tbo.mem.mem_type]; - if ((bo->tbo.mem.mem_type != TTM_PL_VRAM) && (bo->tbo.mem.mem_type != TTM_PL_PRIV)) goto fallback; io_mapping_unmap_atomic(pmap); - - (void) ttm_mem_io_lock(man, false); - ttm_mem_io_free(bo->tbo.bdev, &bo->tbo.mem); - ttm_mem_io_unlock(man); return; fallback: qxl_bo_kunmap(bo); diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c index 9b24514c75aa..cb80e512dd46 100644 --- a/drivers/gpu/drm/qxl/qxl_ttm.c +++ b/drivers/gpu/drm/qxl/qxl_ttm.c @@ -159,8 +159,8 @@ static int qxl_verify_access(struct ttm_buffer_object *bo, struct file *filp) filp->private_data); } -static int qxl_ttm_io_mem_reserve(struct ttm_bo_device *bdev, - struct ttm_mem_reg *mem) +int qxl_ttm_io_mem_reserve(struct ttm_bo_device *bdev, + struct ttm_mem_reg *mem) { struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; struct qxl_device *qdev = qxl_get_qdev(bdev); -- 2.14.1

4 8

[PATCH] drm/tilcdc: include linux/pinctrl/consumer.h again
by Jyri Sarha 30 Sep '19

30 Sep '19

From: Arnd Bergmann <arnd(a)arndb.de> This was apparently dropped by accident in a recent cleanup, causing a build failure in some configurations now: drivers/gpu/drm/tilcdc/tilcdc_tfp410.c:296:12: error: implicit declaration of function 'devm_pinctrl_get_select_default' [-Werror,-Wimplicit-function-declaration] Fixes: fcb57664172e ("drm/tilcdc: drop use of drmP.h") Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> Reviewed-by: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Signed-off-by: Jyri Sarha <jsarha(a)ti.com> --- Just reordered the includes in aplhapetical order and applied Laurent's Reviewed-by. I'll apply this to drm-misc-next. drivers/gpu/drm/tilcdc/tilcdc_tfp410.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c index 525dc1c0f1c1..530edb3b51cc 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c @@ -7,6 +7,7 @@ #include <linux/gpio.h> #include <linux/mod_devicetable.h> #include <linux/of_gpio.h> +#include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <drm/drm_atomic_helper.h> -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

2 1

[PATCH] drm/fourcc: Add Arm 16x16 block modifier
by Raymond Smith 30 Sep '19

30 Sep '19

Add the DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED modifier to denote the 16x16 block u-interleaved format used in Arm Utgard and Midgard GPUs. Signed-off-by: Raymond Smith <raymond.smith(a)arm.com> --- include/uapi/drm/drm_fourcc.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3..8ed7ecf 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -743,6 +743,16 @@ extern "C" { #define AFBC_FORMAT_MOD_BCH (1ULL << 11) /* + * Arm 16x16 Block U-Interleaved modifier + * + * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image + * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels + * in the block are reordered. + */ +#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ + fourcc_mod_code(ARM, ((1ULL << 55) | 1)) + +/* * Allwinner tiled modifier * * This tiling mode is implemented by the VPU found on all Allwinner platforms, -- 2.7.4

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dri-devel September 2019