dri-devel September 2019

dri-devel@lists.freedesktop.org

315 participants
2278 discussions

[PATCH/RFC 0/5] Decouple EDID retrieval from drm_connector
by Laurent Pinchart 10 Sep '19

10 Sep '19

Hello, This small patch series attemps at decoupling EDID retrieval from drm_connector, following a discussion with Daniel Vetter [1]. While working on this I noticed a few issues with EDID retrieval, which I have attempted to fix in patches 1/5 to 4/5. Patch 5/5 then tries to decouple the EDID retrieval from drm_connector, in what I think is a pretty bad way. I would like to discuss this further to see if a) there's an interest, and b) someone has a better idea :-) Regardless of the outcome of the discussion on patch 5/5, the first four patches are candidates for upstreaming as they try to address existing issues (they may also introduce new bugs, but hopefully they will be pointed out during review). The patches are available at git://linuxtv.org/pinchartl/media.git omapdrm/edid [1] https://lists.freedesktop.org/archives/dri-devel/2019-August/231930.html Laurent Pinchart (5): drm/edid: Reorganise the DisplayID parsing code drm/edid: Move functions to avoid forward declaration drm/edid: Move DisplayID tile parsing to drm_connector.c drm/edid: Honour connector->force in drm_do_get_edid() [HACK] drm/edid: Decouple EDID retrieval from connector drivers/gpu/drm/drm_connector.c | 137 +++- drivers/gpu/drm/drm_dp_mst_topology.c | 3 +- drivers/gpu/drm/drm_edid.c | 857 ++++++++++++-------------- include/drm/drm_connector.h | 3 +- include/drm/drm_displayid.h | 2 + include/drm/drm_edid.h | 2 + 6 files changed, 534 insertions(+), 470 deletions(-) -- Regards, Laurent Pinchart

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[PATCH 0/4] Merge VRAM MM and GEM VRAM source files
by Thomas Zimmermann 10 Sep '19

10 Sep '19

VRAM MM and GEM VRAM are only used with each other. This patch set moves VRAM MM into GEM VRAM source files and cleans up the helper's public interface. Thomas Zimmermann (4): drm/vram: Move VRAM memory manager to GEM VRAM implementation drm/vram: Have VRAM MM call GEM VRAM functions directly drm/vram: Unexport internal functions of VRAM MM drm/vram: Unconditonally set BO call-back functions Documentation/gpu/drm-mm.rst | 12 - drivers/gpu/drm/Makefile | 3 +- drivers/gpu/drm/ast/ast_drv.c | 1 - drivers/gpu/drm/ast/ast_main.c | 1 - drivers/gpu/drm/ast/ast_ttm.c | 3 +- drivers/gpu/drm/bochs/bochs.h | 1 - drivers/gpu/drm/bochs/bochs_mm.c | 3 +- drivers/gpu/drm/drm_gem_vram_helper.c | 361 ++++++++++++++---- drivers/gpu/drm/drm_vram_helper_common.c | 8 +- drivers/gpu/drm/drm_vram_mm_helper.c | 309 --------------- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 - drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c | 3 +- drivers/gpu/drm/mgag200/mgag200_drv.h | 1 - drivers/gpu/drm/mgag200/mgag200_ttm.c | 3 +- drivers/gpu/drm/vboxvideo/vbox_drv.h | 2 - drivers/gpu/drm/vboxvideo/vbox_ttm.c | 3 +- include/drm/drm_gem_vram_helper.h | 90 ++++- include/drm/drm_vram_mm_helper.h | 108 ------ 18 files changed, 375 insertions(+), 538 deletions(-) delete mode 100644 drivers/gpu/drm/drm_vram_mm_helper.c delete mode 100644 include/drm/drm_vram_mm_helper.h -- 2.23.0

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[PATCH 1/2] drm/edid: Don't look for CEA data blocks in CEA ext block rev < 3
by Ville Syrjala 10 Sep '19

10 Sep '19

From: Ville Syrjälä <ville.syrjala(a)linux.intel.com> CEA ext block revisions 1 and 2 do not contain the data block collection. Instead that section of the extension block is marked as reserved for 8 byte timing descriptors. Revision 3 changed it to contain the CEA data block collection instead. Most places that iterate the data blocks already check for revision >= 3, but drm_detect_hdmi_monitor() and drm_detect_monitor_audio() do not. So in theory when encountering rev 1 or 2 CEA extension block they could end up misinterpreting whatever data is in the reserved section as CEA data blocks. Let's have cea_db_offsets() do the revision check so that the callers don't even have worry about it. Cc: Jean Delvare <jdelvare(a)suse.de> Signed-off-by: Ville Syrjälä <ville.syrjala(a)linux.intel.com> --- drivers/gpu/drm/drm_edid.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 82a4ceed3fcf..7b3072fc550b 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3690,6 +3690,9 @@ cea_revision(const u8 *cea) static int cea_db_offsets(const u8 *cea, int *start, int *end) { + if (cea_revision(cea) < 3) + return -ENOTSUPP; + /* DisplayID CTA extension blocks and top-level CEA EDID * block header definitions differ in the following bytes: * 1) Byte 2 of the header specifies length differently, -- 2.21.0

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[PATCH 1/9] drm/ttm: return -EBUSY on pipelining with no_gpu_wait
by Christian König 10 Sep '19

10 Sep '19

Setting the no_gpu_wait flag means that the allocate BO must be available immediately and we can't wait for any GPU operation to finish. Signed-off-by: Christian König <christian.koenig(a)amd.com> Acked-by: Felix Kuehling <Felix.Kuehling(a)amd.com> --- drivers/gpu/drm/ttm/ttm_bo.c | 43 +++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 2070e8a57ed8..2899702139fb 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -924,7 +924,8 @@ EXPORT_SYMBOL(ttm_bo_mem_put); */ static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo, struct ttm_mem_type_manager *man, - struct ttm_mem_reg *mem) + struct ttm_mem_reg *mem, + bool no_wait_gpu) { struct dma_fence *fence; int ret; @@ -933,19 +934,22 @@ static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo, fence = dma_fence_get(man->move); spin_unlock(&man->move_lock); - if (fence) { - reservation_object_add_shared_fence(bo->resv, fence); + if (!fence) + return 0; - ret = reservation_object_reserve_shared(bo->resv, 1); - if (unlikely(ret)) { - dma_fence_put(fence); - return ret; - } + if (no_wait_gpu) + return -EBUSY; + + reservation_object_add_shared_fence(bo->resv, fence); - dma_fence_put(bo->moving); - bo->moving = fence; + ret = reservation_object_reserve_shared(bo->resv, 1); + if (unlikely(ret)) { + dma_fence_put(fence); + return ret; } + dma_fence_put(bo->moving); + bo->moving = fence; return 0; } @@ -974,7 +978,7 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object *bo, return ret; } while (1); - return ttm_bo_add_move_fence(bo, man, mem); + return ttm_bo_add_move_fence(bo, man, mem, ctx->no_wait_gpu); } static uint32_t ttm_bo_select_caching(struct ttm_mem_type_manager *man, @@ -1116,13 +1120,16 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, if (unlikely(ret)) goto error; - if (mem->mm_node) { - ret = ttm_bo_add_move_fence(bo, man, mem); - if (unlikely(ret)) { - (*man->func->put_node)(man, mem); - goto error; - } - return 0; + if (!mem->mm_node) + continue; + + ret = ttm_bo_add_move_fence(bo, man, mem, ctx->no_wait_gpu); + if (unlikely(ret)) { + (*man->func->put_node)(man, mem); + if (ret == -EBUSY) + continue; + + goto error; } } -- 2.17.1

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[v4 1/2] dt/bindings: display: Add optional property node define for Mali DP500
by Wen He 10 Sep '19

10 Sep '19

Add optional property node 'arm,malidp-arqos-value' for the Mali DP500. This property describe the ARQoS levels of DP500's QoS signaling. Signed-off-by: Wen He <wen.he_1(a)nxp.com> --- Documentation/devicetree/bindings/display/arm,malidp.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/arm,malidp.txt b/Documentation/devicetree/bindings/display/arm,malidp.txt index 2f7870983ef1..7a97a2b48c2a 100644 --- a/Documentation/devicetree/bindings/display/arm,malidp.txt +++ b/Documentation/devicetree/bindings/display/arm,malidp.txt @@ -37,6 +37,8 @@ Optional properties: Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be used for the framebuffer; if not present, the framebuffer may be located anywhere in memory. + - arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS + levels of DP500's QoS signaling. Example: @@ -54,6 +56,7 @@ Example: clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; + arm,malidp-arqos-high-level = <0xd000d000>; port { dp0_output: endpoint { remote-endpoint = <&tda998x_2_input>; -- 2.17.1

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[PATCH] FBTFT: fb_agm1264k: usleep_range is preferred over udelay
by Sreeram Veluthakkal 10 Sep '19

10 Sep '19

This patch fixes the issue: FILE: drivers/staging/fbtft/fb_agm1264k-fl.c:88: CHECK: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst + udelay(20); Signed-off-by: Sreeram Veluthakkal <srrmvlt(a)gmail.com> --- drivers/staging/fbtft/fb_agm1264k-fl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/fbtft/fb_agm1264k-fl.c b/drivers/staging/fbtft/fb_agm1264k-fl.c index eeeeec97ad27..2dece71fd3b5 100644 --- a/drivers/staging/fbtft/fb_agm1264k-fl.c +++ b/drivers/staging/fbtft/fb_agm1264k-fl.c @@ -85,7 +85,7 @@ static void reset(struct fbtft_par *par) dev_dbg(par->info->device, "%s()\n", __func__); gpiod_set_value(par->gpio.reset, 0); - udelay(20); + usleep_range(20, 40); gpiod_set_value(par->gpio.reset, 1); mdelay(120); } -- 2.17.1

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[PATCH] drm/lima: fix lima_gem_wait() return value
by Vasily Khoruzhick 10 Sep '19

10 Sep '19

drm_gem_reservation_object_wait() returns 0 if it succeeds and -ETIME if it timeouts, but lima driver assumed that 0 is error. Cc: stable(a)vger.kernel.org Signed-off-by: Vasily Khoruzhick <anarsoul(a)gmail.com> --- drivers/gpu/drm/lima/lima_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/lima/lima_gem.c b/drivers/gpu/drm/lima/lima_gem.c index 477c0f766663..b609dc030d6c 100644 --- a/drivers/gpu/drm/lima/lima_gem.c +++ b/drivers/gpu/drm/lima/lima_gem.c @@ -342,7 +342,7 @@ int lima_gem_wait(struct drm_file *file, u32 handle, u32 op, s64 timeout_ns) timeout = drm_timeout_abs_to_jiffies(timeout_ns); ret = drm_gem_reservation_object_wait(file, handle, write, timeout); - if (ret == 0) + if (ret == -ETIME) ret = timeout ? -ETIMEDOUT : -EBUSY; return ret; -- 2.23.0

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[PATCH V5] drm: Add definitions for link training repeaters
by Siqueira, Rodrigo 10 Sep '19

10 Sep '19

This change adds definitions required for Link Training-tunable PHY Repeater, which was introduced in the DP 1.3 specification, and incremented with new features in the DP 1.4*. Changes since V4: - Update commit message - Fix misleading comments related to the spec version Changes since V3: - Replace spaces by tabs Changes since V2: - Drop the kernel-doc comment - Reorder LTTPR according to register offset Changes since V1: - Adjusts registers names to be aligned with spec and the rest of the file - Update spec comment from 1.4 to 1.4a Cc: Abdoulaye Berthe <Abdoulaye.Berthe(a)amd.com> Cc: Harry Wentland <harry.wentland(a)amd.com> Cc: Leo Li <sunpeng.li(a)amd.com> Cc: Jani Nikula <jani.nikula(a)linux.intel.com> Cc: Manasi Navare <manasi.d.navare(a)intel.com> Cc: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira(a)amd.com> Signed-off-by: Abdoulaye Berthe <Abdoulaye.Berthe(a)amd.com> Reviewed-by: Harry Wentland <Harry.Wentland(a)amd.com> --- include/drm/drm_dp_helper.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 7972b925a952..b1a9a0dcc177 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -966,6 +966,31 @@ #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 +/* Link Training (LT)-tunable PHY Repeaters */ +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ +#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ +#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ +#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */ +#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */ +#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */ +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ +#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */ +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ +#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */ +#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */ +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ +#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */ +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ + /* DP HDCP message start offsets in DPCD address space */ #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET -- 2.23.0

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[PATCH V5] drm: Add link training repeaters addresses
by Siqueira, Rodrigo 10 Sep '19

10 Sep '19

DP 1.3 specification introduces the Link Training-tunable PHY Repeater, and DP 1.4* supplemented it with new features. In the 1.4a spec, it was introduced some innovations to make handy to add support for systems with Thunderbolt or other repeater devices. It is important to highlight that DP specification had some updates from 1.3 through 1.4a. In particular, DP 1.4 defines Repeater_FEC_CAPABILITY at the address 0xf0004, and DP 1.4a redefined the address 0xf0004 to DP_MAX_LANE_COUNT_PHY_REPEATER. Changes since V4: - Update commit message - Fix misleading comments related to the spec version Changes since V3: - Replace spaces by tabs Changes since V2: - Drop the kernel-doc comment - Reorder LTTPR according to register offset Changes since V1: - Adjusts registers names to be aligned with spec and the rest of the file - Update spec comment from 1.4 to 1.4a Cc: Abdoulaye Berthe <Abdoulaye.Berthe(a)amd.com> Cc: Harry Wentland <harry.wentland(a)amd.com> Cc: Leo Li <sunpeng.li(a)amd.com> Cc: Jani Nikula <jani.nikula(a)linux.intel.com> Cc: Manasi Navare <manasi.d.navare(a)intel.com> Cc: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira(a)amd.com> Signed-off-by: Abdoulaye Berthe <Abdoulaye.Berthe(a)amd.com> Reviewed-by: Harry Wentland <Harry.Wentland(a)amd.com> --- include/drm/drm_dp_helper.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 7972b925a952..fddcd84601f8 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -966,6 +966,32 @@ #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 +/* Link Training (LT)-tunable PHY Repeaters */ +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ +#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ +#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ +#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ +#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */ +#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */ +#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */ +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ +#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */ +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ +#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */ +#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */ +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ +#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */ +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ + /* DP HDCP message start offsets in DPCD address space */ #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET -- 2.23.0

1 1

[PATCH] drm/tilcdc: include linux/pinctrl/consumer.h again
by Arnd Bergmann 09 Sep '19

09 Sep '19

This was apparently dropped by accident in a recent cleanup, causing a build failure in some configurations now: drivers/gpu/drm/tilcdc/tilcdc_tfp410.c:296:12: error: implicit declaration of function 'devm_pinctrl_get_select_default' [-Werror,-Wimplicit-function-declaration] Fixes: fcb57664172e ("drm/tilcdc: drop use of drmP.h") Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> --- drivers/gpu/drm/tilcdc/tilcdc_tfp410.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c index 525dc1c0f1c1..9edcdd7f2b96 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c @@ -8,6 +8,7 @@ #include <linux/mod_devicetable.h> #include <linux/of_gpio.h> #include <linux/platform_device.h> +#include <linux/pinctrl/consumer.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_encoder.h> -- 2.20.0

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dri-devel September 2019