dri-devel November 2020

dri-devel@lists.freedesktop.org

316 participants
811 discussions

[PATCH 1/2] drm/ttm: use pin_count more extensively
by Christian König 14 Dec '20

14 Dec '20

Check the pin_count instead of the lru list is empty here. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/gpu/drm/ttm/ttm_bo.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 9a03c7834b1e..a0bddcc64504 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -937,9 +937,8 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, } error: - if (bo->mem.mem_type == TTM_PL_SYSTEM && !list_empty(&bo->lru)) { + if (bo->mem.mem_type == TTM_PL_SYSTEM && !bo->pin_count) ttm_bo_move_to_lru_tail_unlocked(bo); - } return ret; } -- 2.25.1

2 2

Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
by Imre Deak 14 Dec '20

14 Dec '20

Hi Daniel, Jani, is it ok to merge this patch along with 2/2 via the i915 tree? --Imre On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote: > From: Radhakrishna Sripada <radhakrishna.sripada(a)intel.com> > > Gen12 display can decompress surfaces compressed by render engine with > Clear Color, add a new modifier as the driver needs to know the surface > was compressed by render engine. > > V2: Description changes as suggested by Rafael. > V3: Mention the Clear Color size of 64 bits in the comments(DK) > v4: Fix trailing whitespaces > v5: Explain Clear Color in the documentation. > v6: Documentation Nitpicks(Nanley) > > Cc: Ville Syrjala <ville.syrjala(a)linux.intel.com> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan(a)intel.com> > Cc: Kalyan Kondapally <kalyan.kondapally(a)intel.com> > Cc: Rafael Antognolli <rafael.antognolli(a)intel.com> > Cc: Nanley Chery <nanley.g.chery(a)intel.com> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada(a)intel.com> > Signed-off-by: Imre Deak <imre.deak(a)intel.com> > --- > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index ca48ed0e6bc1..0a1b2c4c4bee 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -527,6 +527,25 @@ extern "C" { > */ > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) > > +/* > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render > + * compression. > + * > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear > + * and at index 1. The clear color is stored at index 2, and the pitch should > + * be ignored. The clear color structure is 256 bits. The first 128 bits > + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented > + * by 32 bits. The raw clear color is consumed by the 3d engine and generates > + * the converted clear color of size 64 bits. The first 32 bits store the Lower > + * Converted Clear Color value and the next 32 bits store the Higher Converted > + * Clear Color value when applicable. The Converted Clear Color values are > + * consumed by the DE. The last 64 bits are used to store Color Discard Enable > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line > + * corresponds to an area of 4x1 tiles in the main surface. The main surface > + * pitch is required to be a multiple of 4 tile widths. > + */ > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) > + > /* > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > * > -- > 2.25.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

4 7

[PATCH] drm/amdgpu: fix check oder in amdgpu_bo_move
by Christian König 14 Dec '20

14 Dec '20

Reorder the code to fix checking if blitting is available. Signed-off-by: Christian König <christian.koenig(a)amd.com> Fixes: f5a89a5cae81 drm/amdgpu/ttm: use multihop --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 53 +++++++++++-------------- 1 file changed, 23 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 676fb520e044..c438d290a6db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -551,25 +551,12 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, struct ttm_resource *old_mem = &bo->mem; int r; - if ((old_mem->mem_type == TTM_PL_SYSTEM && - new_mem->mem_type == TTM_PL_VRAM) || - (old_mem->mem_type == TTM_PL_VRAM && - new_mem->mem_type == TTM_PL_SYSTEM)) { - hop->fpfn = 0; - hop->lpfn = 0; - hop->mem_type = TTM_PL_TT; - hop->flags = 0; - return -EMULTIHOP; - } - if (new_mem->mem_type == TTM_PL_TT) { r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); if (r) return r; } - amdgpu_bo_move_notify(bo, evict, new_mem); - /* Can't move a pinned BO */ abo = ttm_to_amdgpu_bo(bo); if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) @@ -579,24 +566,23 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { ttm_bo_move_null(bo, new_mem); - return 0; + goto out; } if (old_mem->mem_type == TTM_PL_SYSTEM && new_mem->mem_type == TTM_PL_TT) { ttm_bo_move_null(bo, new_mem); - return 0; + goto out; } - if (old_mem->mem_type == TTM_PL_TT && new_mem->mem_type == TTM_PL_SYSTEM) { r = ttm_bo_wait_ctx(bo, ctx); if (r) - goto fail; + return r; amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); ttm_resource_free(bo, &bo->mem); ttm_bo_assign_mem(bo, new_mem); - return 0; + goto out; } if (old_mem->mem_type == AMDGPU_PL_GDS || @@ -607,27 +593,37 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, new_mem->mem_type == AMDGPU_PL_OA) { /* Nothing to save here */ ttm_bo_move_null(bo, new_mem); - return 0; + goto out; } - if (!adev->mman.buffer_funcs_enabled) { + if (adev->mman.buffer_funcs_enabled) { + if (((old_mem->mem_type == TTM_PL_SYSTEM && + new_mem->mem_type == TTM_PL_VRAM) || + (old_mem->mem_type == TTM_PL_VRAM && + new_mem->mem_type == TTM_PL_SYSTEM))) { + hop->fpfn = 0; + hop->lpfn = 0; + hop->mem_type = TTM_PL_TT; + hop->flags = 0; + return -EMULTIHOP; + } + + r = amdgpu_move_blit(bo, evict, new_mem, old_mem); + } else { r = -ENODEV; - goto memcpy; } - r = amdgpu_move_blit(bo, evict, new_mem, old_mem); if (r) { -memcpy: /* Check that all memory is CPU accessible */ if (!amdgpu_mem_visible(adev, old_mem) || !amdgpu_mem_visible(adev, new_mem)) { pr_err("Move buffer fallback to memcpy unavailable\n"); - goto fail; + return r; } r = ttm_bo_move_memcpy(bo, ctx, new_mem); if (r) - goto fail; + return r; } if (bo->type == ttm_bo_type_device && @@ -639,14 +635,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; } +out: /* update statistics */ atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); + amdgpu_bo_move_notify(bo, evict, new_mem); return 0; -fail: - swap(*new_mem, bo->mem); - amdgpu_bo_move_notify(bo, false, new_mem); - swap(*new_mem, bo->mem); - return r; } /** -- 2.25.1

5 4

[PATCH 0/9] Xilinx AI engine kernel driver
by Wendy Liang 14 Dec '20

14 Dec '20

AI engine is the acceleration engine provided by Xilinx. These engines provide high compute density for vector-based algorithms, and flexible custom compute and data movement. It has core tiles for compute and shim tiles to interface the FPGA fabric. You can check the AI engine architecture document for more hardware details: https://www.xilinx.com/support/documentation/architecture-manuals/am009-ver… This patch series adds a Linux kernel driver to manage the Xilinx AI engine array device and AI engine partitions (groups of AI engine tiles dedicated to an application). Izhar Ameer Shaikh (1): firmware: xilinx: Add IOCTL support for AIE ISR Clear Nishad Saraf (2): misc: xilinx-ai-engine: Add support to request device management services misc: xilinx-ai-engine: Add support for servicing error interrupts Wendy Liang (6): dt-binding: soc: xilinx: ai-engine: Add AI engine binding misc: Add Xilinx AI engine device driver misc: xilinx-ai-engine: Implement AI engine cleanup sequence misc: xilinx-ai-engine: expose AI engine tile memories to userspace misc: xilinx-ai-engine: add setting shim dma bd operation misc: xilinx-ai-engine: add request and release tiles .../bindings/soc/xilinx/xlnx,ai-engine.yaml | 119 ++++ MAINTAINERS | 8 + drivers/firmware/xilinx/zynqmp.c | 14 + drivers/misc/Kconfig | 12 + drivers/misc/Makefile | 1 + drivers/misc/xilinx-ai-engine/Makefile | 16 + drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 608 +++++++++++++++++++ drivers/misc/xilinx-ai-engine/ai-engine-clock.c | 244 ++++++++ drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 492 +++++++++++++++ drivers/misc/xilinx-ai-engine/ai-engine-dma.c | 481 +++++++++++++++ drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 519 ++++++++++++++++ .../misc/xilinx-ai-engine/ai-engine-interrupt.c | 661 +++++++++++++++++++++ drivers/misc/xilinx-ai-engine/ai-engine-mem.c | 274 +++++++++ drivers/misc/xilinx-ai-engine/ai-engine-part.c | 635 ++++++++++++++++++++ drivers/misc/xilinx-ai-engine/ai-engine-res.c | 219 +++++++ drivers/misc/xilinx-ai-engine/ai-engine-reset.c | 159 +++++ include/linux/firmware/xlnx-zynqmp.h | 8 + include/uapi/linux/xlnx-ai-engine.h | 236 ++++++++ 18 files changed, 4706 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml create mode 100644 drivers/misc/xilinx-ai-engine/Makefile create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c create mode 100644 include/uapi/linux/xlnx-ai-engine.h -- 2.7.4

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[Bug 201139] New: amdgpu: [drm] enabling link 1 failed: 15 (vega)
by bugzilla-daemon＠bugzilla.kernel.org 12 Dec '20

12 Dec '20

https://bugzilla.kernel.org/show_bug.cgi?id=201139 Bug ID: 201139 Summary: amdgpu: [drm] enabling link 1 failed: 15 (vega) Product: Drivers Version: 2.5 Kernel Version: 4.19-rc3 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: mezin.alexander(a)gmail.com Regression: No My setup: - RX Vega 64 - Arch Linux - GNOME 3.28.3 on Xorg 1.20.1 - modesetting Xorg driver - LG 27UD69P and Dell P2415Q I have "screen blanking" enabled in Gnome. Sometimes (very rarely) one display (Dell, connected to 2nd DisplayPort) doesn't wake up correctly. It turns on, shows only black screen, then quickly shows "no signal" message. In kernel log I see: [39215.008773] [drm] enabling link 1 failed: 15 If I manually turn the display off and on, it starts to work. Can't tell if it is a regression (hardly it is) because on 4.18 and earlier screen blanking just makes the driver hang: https://bugzilla.kernel.org/show_bug.cgi?id=200531 I've never seen a similar issue on Windows on the same machine. If I'm not mistaken, I've seen the same issue with Gnome on Wayland too (but I'm not sure). -- You are receiving this mail because: You are watching the assignee of the bug.

1 14

[PATCH v7 0/3] drm: LogiCVC display controller support
by Paul Kocialkowski 11 Dec '20

11 Dec '20

This series introduces support for the LogiCVC display controller. The controller is a bit unusual since it is usually loaded as programmable logic on Xilinx FPGAs or Zynq-7000 SoCs. More details are presented on the main commit for the driver. More information about the controller is available on the dedicated web page: https://www.logicbricks.com/Products/logiCVC-ML.aspx Note that this driver has rather simple connector management, which was not converted to drm_panel_bridge to keep the ability to enable the panel at first vblank but also to support DVI. Changes since v6: - Updated to the latest DRM internal API changes; - Used an enum to index dt properties instead of the name string. Changes since v5: - Subclass DRM device and use devm_drm_dev_alloc for allocation; - Removed call to drm_mode_config_cleanup (done automatically with devm); - Some related code cleanups; - Bring back not-for-merge patch adding colorkey support. Changes since v4: - Updated to internal DRM API changes (rebased on drm-misc-next); - Added Kconfig dependency on OF; - Added MAINTAINERS entry; - Used drm_err and dev_err instead of DRM_ERROR where possible; - Various cosmetic changes. Changes since v3: - Rebased on latest drm-misc; - Improved event lock wrapping; - Added collect tag; - Added color-key support patch (not for merge, for reference only). Changes since v2: - Fixed and slightly improved dt schema. Changes since v1: - Switched dt bindings documentation to dt schema; - Described more possible dt parameters; - Added support for the lvds-3bit interface; - Added support for grabbing syscon regmap from parent node; - Removed layers count property and count layers child nodes instead. Cheers! Paul Kocialkowski (3): dt-bindings: display: Document the Xylon LogiCVC display controller drm: Add support for the LogiCVC display controller NOTFORMERGE: drm/logicvc: Add plane colorkey support .../display/xylon,logicvc-display.yaml | 313 ++++++++ MAINTAINERS | 6 + drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/logicvc/Kconfig | 9 + drivers/gpu/drm/logicvc/Makefile | 4 + drivers/gpu/drm/logicvc/logicvc_crtc.c | 277 +++++++ drivers/gpu/drm/logicvc/logicvc_crtc.h | 21 + drivers/gpu/drm/logicvc/logicvc_drm.c | 472 +++++++++++ drivers/gpu/drm/logicvc/logicvc_drm.h | 67 ++ drivers/gpu/drm/logicvc/logicvc_interface.c | 224 ++++++ drivers/gpu/drm/logicvc/logicvc_interface.h | 30 + drivers/gpu/drm/logicvc/logicvc_layer.c | 750 ++++++++++++++++++ drivers/gpu/drm/logicvc/logicvc_layer.h | 71 ++ drivers/gpu/drm/logicvc/logicvc_mode.c | 101 +++ drivers/gpu/drm/logicvc/logicvc_mode.h | 15 + drivers/gpu/drm/logicvc/logicvc_of.c | 197 +++++ drivers/gpu/drm/logicvc/logicvc_of.h | 46 ++ drivers/gpu/drm/logicvc/logicvc_regs.h | 88 ++ 19 files changed, 2694 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml create mode 100644 drivers/gpu/drm/logicvc/Kconfig create mode 100644 drivers/gpu/drm/logicvc/Makefile create mode 100644 drivers/gpu/drm/logicvc/logicvc_crtc.c create mode 100644 drivers/gpu/drm/logicvc/logicvc_crtc.h create mode 100644 drivers/gpu/drm/logicvc/logicvc_drm.c create mode 100644 drivers/gpu/drm/logicvc/logicvc_drm.h create mode 100644 drivers/gpu/drm/logicvc/logicvc_interface.c create mode 100644 drivers/gpu/drm/logicvc/logicvc_interface.h create mode 100644 drivers/gpu/drm/logicvc/logicvc_layer.c create mode 100644 drivers/gpu/drm/logicvc/logicvc_layer.h create mode 100644 drivers/gpu/drm/logicvc/logicvc_mode.c create mode 100644 drivers/gpu/drm/logicvc/logicvc_mode.h create mode 100644 drivers/gpu/drm/logicvc/logicvc_of.c create mode 100644 drivers/gpu/drm/logicvc/logicvc_of.h create mode 100644 drivers/gpu/drm/logicvc/logicvc_regs.h -- 2.28.0

4 10

[PATCH v5 1/1] lib/vsprintf: Add support for printing V4L2 and DRM fourccs
by Sakari Ailus 11 Dec '20

11 Dec '20

Add a printk modifier %p4cc (for pixel format) for printing V4L2 and DRM pixel formats denoted by fourccs. The fourcc encoding is the same for both so the same implementation can be used. Suggested-by: Mauro Carvalho Chehab <mchehab(a)kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus(a)linux.intel.com> --- since v4: - Use correct destination for error string (was broken in v4) - Remove unneeded comment "/* subtract parenthesis and the space from the size */". Documentation/core-api/printk-formats.rst | 16 +++++++ lib/test_printf.c | 17 ++++++++ lib/vsprintf.c | 51 +++++++++++++++++++++++ 3 files changed, 84 insertions(+) diff --git a/Documentation/core-api/printk-formats.rst b/Documentation/core-api/printk-formats.rst index 6d26c5c6ac48..080262d2e030 100644 --- a/Documentation/core-api/printk-formats.rst +++ b/Documentation/core-api/printk-formats.rst @@ -565,6 +565,22 @@ For printing netdev_features_t. Passed by reference. +V4L2 and DRM FourCC code (pixel format) +--------------------------------------- + +:: + + %p4cc + +Print a FourCC code used by V4L2 or DRM, including format endianness and +its numerical value as hexadecimal. + +Passed by reference. + +Examples:: + + %p4cc BG12 little-endian (0x32314742) + Thanks ====== diff --git a/lib/test_printf.c b/lib/test_printf.c index 7ac87f18a10f..7fb042542660 100644 --- a/lib/test_printf.c +++ b/lib/test_printf.c @@ -649,6 +649,22 @@ static void __init fwnode_pointer(void) software_node_unregister(&softnodes[0]); } +static void __init fourcc_pointer(void) +{ + struct { + u32 code; + char *str; + } const try[] = { + { 0x20104646, "FF(10) little-endian (0x20104646)", }, + { 0xa0104646, "FF(10) big-endian (0xa0104646)", }, + { 0x10111213, "(13)(12)(11)(10) little-endian (0x10111213)", }, + }; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(try); i++) + test(try[i].str, "%p4cc", &try[i].code); +} + static void __init errptr(void) { @@ -694,6 +710,7 @@ test_pointer(void) flags(); errptr(); fwnode_pointer(); + fourcc_pointer(); } static void __init selftest(void) diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 14c9a6af1b23..b07ee5b7de06 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -1733,6 +1733,54 @@ char *netdev_bits(char *buf, char *end, const void *addr, return special_hex_number(buf, end, num, size); } +static noinline_for_stack +char *fourcc_string(char *buf, char *end, const u32 *fourcc, + struct printf_spec spec, const char *fmt) +{ + char output[sizeof("(xx)(xx)(xx)(xx) little-endian (0x01234567)")]; + char *p = output; + unsigned int i; + u32 val; + + if (fmt[1] != 'c' || fmt[2] != 'c') + return error_string(buf, end, "(%p4?)", spec); + + if (check_pointer(&buf, end, fourcc, spec)) + return buf; + + val = *fourcc & ~BIT(31); + + for (i = 0; i < sizeof(*fourcc); i++) { + unsigned char c = val >> (i * 8); + + /* Weed out spaces */ + if (c == ' ') + continue; + + /* Print non-control ASCII characters as-is */ + if (isascii(c) && isprint(c)) { + *p++ = c; + continue; + } + + *p++ = '('; + p = hex_byte_pack(p, c); + *p++ = ')'; + } + + strcpy(p, *fourcc & BIT(31) ? " big-endian" : " little-endian"); + p += strlen(p); + + *p++ = ' '; + *p++ = '('; + p = special_hex_number(p, output + sizeof(output) - 2, *fourcc, + sizeof(u32)); + *p++ = ')'; + *p = '\0'; + + return string(buf, end, output, spec); +} + static noinline_for_stack char *address_val(char *buf, char *end, const void *addr, struct printf_spec spec, const char *fmt) @@ -2162,6 +2210,7 @@ char *fwnode_string(char *buf, char *end, struct fwnode_handle *fwnode, * correctness of the format string and va_list arguments. * - 'K' For a kernel pointer that should be hidden from unprivileged users * - 'NF' For a netdev_features_t + * - '4cc' V4L2 or DRM FourCC code, with endianness and raw numerical value. * - 'h[CDN]' For a variable-length buffer, it prints it as a hex string with * a certain separator (' ' by default): * C colon @@ -2259,6 +2308,8 @@ char *pointer(const char *fmt, char *buf, char *end, void *ptr, return restricted_pointer(buf, end, ptr, spec); case 'N': return netdev_bits(buf, end, ptr, spec, fmt); + case '4': + return fourcc_string(buf, end, ptr, spec, fmt); case 'a': return address_val(buf, end, ptr, spec, fmt); case 'd': -- 2.27.0

4 7

[PATCH v1] drm/bridge: lt9611: Fix handling of 4k panels
by Robert Foss 11 Dec '20

11 Dec '20

4k requires two dsi pipes, so don't report MODE_OK when only a single pipe is configured. But rather report MODE_PANEL to signal that requirements of the panel are not being met. Reported-by: Peter Collingbourne <pcc(a)google.com> Suggested-by: Peter Collingbourne <pcc(a)google.com> Signed-off-by: Robert Foss <robert.foss(a)linaro.org> Tested-by: John Stultz <john.stultz(a)linaro.org> --- drivers/gpu/drm/bridge/lontium-lt9611.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/lontium-lt9611.c b/drivers/gpu/drm/bridge/lontium-lt9611.c index d734d9402c35..e8eb8deb444b 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611.c @@ -867,8 +867,14 @@ static enum drm_mode_status lt9611_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_mode *mode) { struct lt9611_mode *lt9611_mode = lt9611_find_mode(mode); + struct lt9611 *lt9611 = bridge_to_lt9611(bridge); - return lt9611_mode ? MODE_OK : MODE_BAD; + if (!lt9611_mode) + return MODE_BAD; + else if (lt9611_mode->intfs > 1 && !lt9611->dsi1) + return MODE_PANEL; + else + return MODE_OK; } static void lt9611_bridge_pre_enable(struct drm_bridge *bridge) -- 2.27.0

5 4

[PATCH 0/7] Adding a proper workaround for fixing RTD3 issues with Nouveau
by Karol Herbst 10 Dec '20

10 Dec '20

First three patches are removing ACPI workarounds which should have never landed. The last four are adding a workaround to nouveau which seem to help quite a lot with the RTD3 issues with Nouveau, so let's discuss and get wider testing of those and see if there is any fallout or laptops where the issues don't get fixed. Karol Herbst (7): Revert "ACPI / OSI: Add OEM _OSI string to enable dGPU direct output" Revert "ACPI / OSI: Add OEM _OSI string to enable NVidia HDMI audio" Revert "ACPI / OSI: Add OEM _OSI strings to disable NVidia RTD3" drm/nouveau/pci: enable pcie link changes for pascal drm/nouveau/pci: add nvkm_pcie_get_speed drm/nouveau/pci: save the boot pcie link speed and restore it on fini drm/nouveau: abort runtime suspend if we hit an error drivers/acpi/osi.c | 24 ---------- .../drm/nouveau/include/nvkm/core/device.h | 2 + .../gpu/drm/nouveau/include/nvkm/subdev/pci.h | 9 ++-- drivers/gpu/drm/nouveau/nouveau_drm.c | 6 +++ .../gpu/drm/nouveau/nvkm/subdev/clk/base.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/pci/base.c | 9 +++- .../gpu/drm/nouveau/nvkm/subdev/pci/gk104.c | 8 ++-- .../gpu/drm/nouveau/nvkm/subdev/pci/gp100.c | 10 ++++ .../gpu/drm/nouveau/nvkm/subdev/pci/pcie.c | 46 +++++++++++++++++-- .../gpu/drm/nouveau/nvkm/subdev/pci/priv.h | 7 +++ 10 files changed, 84 insertions(+), 39 deletions(-) -- 2.21.0

10 40

[PATCH] drm: drivers may provide multiple primary planes per CRTC
by Simon Ser 09 Dec '20

09 Dec '20

Some drivers may expose primary planes compatible with multiple CRTCs. Make this clear in the docs: the current wording may be misunderstood as "exactly one primary plane per CRTC". Signed-off-by: Simon Ser <contact(a)emersion.fr> Cc: Daniel Vetter <daniel(a)ffwll.ch> --- drivers/gpu/drm/drm_plane.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index b7b90b3a2e38..108a922e8c23 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -49,8 +49,8 @@ * &struct drm_plane (possibly as part of a larger structure) and registers it * with a call to drm_universal_plane_init(). * - * Cursor and overlay planes are optional. All drivers should provide one - * primary plane per CRTC to avoid surprising userspace too much. See enum + * Cursor and overlay planes are optional. All drivers should provide at least + * one primary plane per CRTC to avoid surprising userspace too much. See enum * drm_plane_type for a more in-depth discussion of these special uapi-relevant * plane types. Special planes are associated with their CRTC by calling * drm_crtc_init_with_planes(). -- 2.28.0

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dri-devel November 2020