dri-devel February 2020

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679 discussions

[PATCH v5] drm/dp_mst: Fix W=1 warnings
by Benjamin Gaignard 04 Feb '20

04 Feb '20

Fix the warnings that show up with W=1. They are all about unused but set variables. If functions returns are not used anymore make them void. Signed-off-by: Benjamin Gaignard <benjamin.gaignard(a)st.com> --- version 5: - fix indentation version 4: - do not touch crc4 unused variable in this patch CC: lyude(a)redhat.com CC: airlied(a)linux.ie CC: jani.nikula(a)linux.intel.com drivers/gpu/drm/drm_dp_mst_topology.c | 92 +++++++++++++++-------------------- 1 file changed, 40 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 4104f15f4594..822d2f177f90 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -1034,7 +1034,8 @@ static bool drm_dp_sideband_parse_req(struct drm_dp_sideband_msg_rx *raw, } } -static int build_dpcd_write(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 offset, u8 num_bytes, u8 *bytes) +static void build_dpcd_write(struct drm_dp_sideband_msg_tx *msg, + u8 port_num, u32 offset, u8 num_bytes, u8 *bytes) { struct drm_dp_sideband_msg_req_body req; @@ -1044,17 +1045,14 @@ static int build_dpcd_write(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 req.u.dpcd_write.num_bytes = num_bytes; req.u.dpcd_write.bytes = bytes; drm_dp_encode_sideband_req(&req, msg); - - return 0; } -static int build_link_address(struct drm_dp_sideband_msg_tx *msg) +static void build_link_address(struct drm_dp_sideband_msg_tx *msg) { struct drm_dp_sideband_msg_req_body req; req.req_type = DP_LINK_ADDRESS; drm_dp_encode_sideband_req(&req, msg); - return 0; } static int build_clear_payload_id_table(struct drm_dp_sideband_msg_tx *msg) @@ -1066,7 +1064,8 @@ static int build_clear_payload_id_table(struct drm_dp_sideband_msg_tx *msg) return 0; } -static int build_enum_path_resources(struct drm_dp_sideband_msg_tx *msg, int port_num) +static int build_enum_path_resources(struct drm_dp_sideband_msg_tx *msg, + int port_num) { struct drm_dp_sideband_msg_req_body req; @@ -1077,10 +1076,11 @@ static int build_enum_path_resources(struct drm_dp_sideband_msg_tx *msg, int por return 0; } -static int build_allocate_payload(struct drm_dp_sideband_msg_tx *msg, int port_num, - u8 vcpi, uint16_t pbn, - u8 number_sdp_streams, - u8 *sdp_stream_sink) +static void build_allocate_payload(struct drm_dp_sideband_msg_tx *msg, + int port_num, + u8 vcpi, uint16_t pbn, + u8 number_sdp_streams, + u8 *sdp_stream_sink) { struct drm_dp_sideband_msg_req_body req; memset(&req, 0, sizeof(req)); @@ -1093,11 +1093,10 @@ static int build_allocate_payload(struct drm_dp_sideband_msg_tx *msg, int port_n number_sdp_streams); drm_dp_encode_sideband_req(&req, msg); msg->path_msg = true; - return 0; } -static int build_power_updown_phy(struct drm_dp_sideband_msg_tx *msg, - int port_num, bool power_up) +static void build_power_updown_phy(struct drm_dp_sideband_msg_tx *msg, + int port_num, bool power_up) { struct drm_dp_sideband_msg_req_body req; @@ -1109,7 +1108,6 @@ static int build_power_updown_phy(struct drm_dp_sideband_msg_tx *msg, req.u.port_num.port_number = port_num; drm_dp_encode_sideband_req(&req, msg); msg->path_msg = true; - return 0; } static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr *mgr, @@ -2054,25 +2052,20 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux, static void drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, u8 *guid) { - int ret; - memcpy(mstb->guid, guid, 16); if (!drm_dp_validate_guid(mstb->mgr, mstb->guid)) { if (mstb->port_parent) { - ret = drm_dp_send_dpcd_write( - mstb->mgr, - mstb->port_parent, - DP_GUID, - 16, - mstb->guid); + drm_dp_send_dpcd_write(mstb->mgr, + mstb->port_parent, + DP_GUID, + 16, + mstb->guid); } else { - - ret = drm_dp_dpcd_write( - mstb->mgr->aux, - DP_GUID, - mstb->guid, - 16); + drm_dp_dpcd_write(mstb->mgr->aux, + DP_GUID, + mstb->guid, + 16); } } } @@ -2595,7 +2588,8 @@ static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, return false; } -static int build_dpcd_read(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 offset, u8 num_bytes) +static void build_dpcd_read(struct drm_dp_sideband_msg_tx *msg, + u8 port_num, u32 offset, u8 num_bytes) { struct drm_dp_sideband_msg_req_body req; @@ -2604,8 +2598,6 @@ static int build_dpcd_read(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 req.u.dpcd_read.dpcd_address = offset; req.u.dpcd_read.num_bytes = num_bytes; drm_dp_encode_sideband_req(&req, msg); - - return 0; } static int drm_dp_send_sideband_msg(struct drm_dp_mst_topology_mgr *mgr, @@ -2828,7 +2820,7 @@ static int drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_sideband_msg_tx *txmsg; struct drm_dp_link_address_ack_reply *reply; struct drm_dp_mst_port *port, *tmp; - int i, len, ret, port_mask = 0; + int i, ret, port_mask = 0; bool changed = false; txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); @@ -2836,7 +2828,7 @@ static int drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr, return -ENOMEM; txmsg->dst = mstb; - len = build_link_address(txmsg); + build_link_address(txmsg); mstb->link_address_sent = true; drm_dp_queue_down_tx(mgr, txmsg); @@ -2898,14 +2890,14 @@ void drm_dp_send_clear_payload_id_table(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_branch *mstb) { struct drm_dp_sideband_msg_tx *txmsg; - int len, ret; + int ret; txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); if (!txmsg) return; txmsg->dst = mstb; - len = build_clear_payload_id_table(txmsg); + build_clear_payload_id_table(txmsg); drm_dp_queue_down_tx(mgr, txmsg); @@ -2923,7 +2915,6 @@ drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, { struct drm_dp_enum_path_resources_ack_reply *path_res; struct drm_dp_sideband_msg_tx *txmsg; - int len; int ret; txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); @@ -2931,7 +2922,7 @@ drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, return -ENOMEM; txmsg->dst = mstb; - len = build_enum_path_resources(txmsg, port->port_num); + build_enum_path_resources(txmsg, port->port_num); drm_dp_queue_down_tx(mgr, txmsg); @@ -3014,7 +3005,7 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr, { struct drm_dp_sideband_msg_tx *txmsg; struct drm_dp_mst_branch *mstb; - int len, ret, port_num; + int ret, port_num; u8 sinks[DRM_DP_MAX_SDP_STREAMS]; int i; @@ -3039,9 +3030,9 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr, sinks[i] = i; txmsg->dst = mstb; - len = build_allocate_payload(txmsg, port_num, - id, - pbn, port->num_sdp_streams, sinks); + build_allocate_payload(txmsg, port_num, + id, + pbn, port->num_sdp_streams, sinks); drm_dp_queue_down_tx(mgr, txmsg); @@ -3070,7 +3061,7 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, bool power_up) { struct drm_dp_sideband_msg_tx *txmsg; - int len, ret; + int ret; port = drm_dp_mst_topology_get_port_validated(mgr, port); if (!port) @@ -3083,7 +3074,7 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, } txmsg->dst = port->parent; - len = build_power_updown_phy(txmsg, port->port_num, power_up); + build_power_updown_phy(txmsg, port->port_num, power_up); drm_dp_queue_down_tx(mgr, txmsg); ret = drm_dp_mst_wait_tx_reply(port->parent, txmsg); @@ -3305,7 +3296,6 @@ static int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int offset, int size, u8 *bytes) { - int len; int ret = 0; struct drm_dp_sideband_msg_tx *txmsg; struct drm_dp_mst_branch *mstb; @@ -3320,7 +3310,7 @@ static int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr, goto fail_put; } - len = build_dpcd_read(txmsg, port->port_num, offset, size); + build_dpcd_read(txmsg, port->port_num, offset, size); txmsg->dst = port->parent; drm_dp_queue_down_tx(mgr, txmsg); @@ -3358,7 +3348,6 @@ static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int offset, int size, u8 *bytes) { - int len; int ret; struct drm_dp_sideband_msg_tx *txmsg; struct drm_dp_mst_branch *mstb; @@ -3373,7 +3362,7 @@ static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, goto fail_put; } - len = build_dpcd_write(txmsg, port->port_num, offset, size, bytes); + build_dpcd_write(txmsg, port->port_num, offset, size, bytes); txmsg->dst = mstb; drm_dp_queue_down_tx(mgr, txmsg); @@ -4529,17 +4518,16 @@ void drm_dp_mst_dump_topology(struct seq_file *m, mutex_lock(&mgr->lock); if (mgr->mst_primary) { u8 buf[DP_PAYLOAD_TABLE_SIZE]; - int ret; - ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, buf, DP_RECEIVER_CAP_SIZE); + drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, buf, DP_RECEIVER_CAP_SIZE); seq_printf(m, "dpcd: %*ph\n", DP_RECEIVER_CAP_SIZE, buf); - ret = drm_dp_dpcd_read(mgr->aux, DP_FAUX_CAP, buf, 2); + drm_dp_dpcd_read(mgr->aux, DP_FAUX_CAP, buf, 2); seq_printf(m, "faux/mst: %*ph\n", 2, buf); - ret = drm_dp_dpcd_read(mgr->aux, DP_MSTM_CTRL, buf, 1); + drm_dp_dpcd_read(mgr->aux, DP_MSTM_CTRL, buf, 1); seq_printf(m, "mst ctrl: %*ph\n", 1, buf); /* dump the standard OUI branch header */ - ret = drm_dp_dpcd_read(mgr->aux, DP_BRANCH_OUI, buf, DP_BRANCH_OUI_HEADER_SIZE); + drm_dp_dpcd_read(mgr->aux, DP_BRANCH_OUI, buf, DP_BRANCH_OUI_HEADER_SIZE); seq_printf(m, "branch oui: %*phN devid: ", 3, buf); for (i = 0x3; i < 0x8 && buf[i]; i++) seq_printf(m, "%c", buf[i]); -- 2.15.0

2 1

[PATCH v2 1/3] drm: msm: Add 618 gpu to the adreno gpu list
by Sharat Masetty 04 Feb '20

04 Feb '20

This patch adds Adreno 618 entry and its associated properties to the gpulist entries. Signed-off-by: Sharat Masetty <smasetty(a)codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index fbbdf86..cb3a6e5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -167,6 +167,17 @@ .init = a5xx_gpu_init, .zapfw = "a540_zap.mdt", }, { + .rev = ADRENO_REV(6, 1, 8, ANY_ID), + .revn = 618, + .name = "A618", + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a630_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), .revn = 630, .name = "A630", -- 1.9.1

4 6

[PATCH 1/8] drm/edid: Check the number of detailed timing descriptors in the CEA ext block
by Ville Syrjala 04 Feb '20

04 Feb '20

From: Ville Syrjälä <ville.syrjala(a)linux.intel.com> CEA-861 says : "d = offset for the byte following the reserved data block. If no data is provided in the reserved data block, then d=4. If no DTDs are provided, then d=0." So let's not look for DTDs when d==0. In fact let's just make that <4 since those values would just mean that he DTDs overlap the block header. And let's also check that d isn't so big as to declare the descriptors to live past the block end, although the code does already survive that case as we'd just end up with a negative number of descriptors and the loop would not do anything. Cc: Allen Chen <allen.chen(a)ite.com.tw> Signed-off-by: Ville Syrjälä <ville.syrjala(a)linux.intel.com> --- drivers/gpu/drm/drm_edid.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 99769d6c9f84..1b6e544cf5c7 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2201,10 +2201,13 @@ typedef void detailed_cb(struct detailed_timing *timing, void *closure); static void cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) { - int i, n = 0; + int i, n; u8 d = ext[0x02]; u8 *det_base = ext + d; + if (d < 4 || d > 127) + return; + n = (127 - d) / 18; for (i = 0; i < n; i++) cb((struct detailed_timing *)(det_base + 18 * i), closure); -- 2.24.1

5 31

[bug report] drm/ttm: fix re-init of global structures
by Dan Carpenter 04 Feb '20

04 Feb '20

Hello Christian König, The patch bd4264112f93: "drm/ttm: fix re-init of global structures" from Apr 16, 2019, leads to the following static checker warning: drivers/gpu/drm/ttm/ttm_bo.c:1610 ttm_bo_global_release() warn: passing freed memory 'glob' drivers/gpu/drm/ttm/ttm_bo.c 1591 static void ttm_bo_global_kobj_release(struct kobject *kobj) 1592 { 1593 struct ttm_bo_global *glob = 1594 container_of(kobj, struct ttm_bo_global, kobj); 1595 1596 __free_page(glob->dummy_read_page); 1597 } 1598 1599 static void ttm_bo_global_release(void) 1600 { 1601 struct ttm_bo_global *glob = &ttm_bo_glob; 1602 1603 mutex_lock(&ttm_global_mutex); 1604 if (--ttm_bo_glob_use_count > 0) 1605 goto out; 1606 1607 kobject_del(&glob->kobj); 1608 kobject_put(&glob->kobj); 1609 ttm_mem_global_release(&ttm_mem_glob); 1610 memset(glob, 0, sizeof(*glob)); ^^^^^^^^^^^^^^^^^^^^^^ Depending on the config kobject_release() might call ttm_bo_global_kobj_release() a few seconds after this memset. Maybe put the memset into ttm_bo_global_kobj_release()? 1611 out: 1612 mutex_unlock(&ttm_global_mutex); 1613 } regards, dan carpenter

2 3

[v4] arm64: dts: sc7180: add display dt nodes
by Harigovindan P 04 Feb '20

04 Feb '20

Add display, DSI hardware DT nodes for sc7180. Signed-off-by: Harigovindan P <harigovi(a)codeaurora.org> --- Changes in v1: -Added display DT nodes for sc7180 Changes in v2: -Renamed node names -Corrected code alignments -Removed extra new line -Added DISP AHB clock for register access under display_subsystem node for global settings Changes in v3: -Modified node names -Modified hard coded values -Removed mdss reg entry Changes in v4: -Reverting mdp node name -Setting status to disabled in main SOC dtsi file -Replacing _ to - for node names -Adding clock dependency patch link -Splitting idp dt file to a separate patch This patch has dependency on the below series https://lkml.org/lkml/2019/12/27/73 arch/arm64/boot/dts/qcom/sc7180.dtsi | 128 +++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3bc3f64..c3883af 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1184,6 +1184,134 @@ #power-domain-cells = <1>; }; + mdss: mdss@ae00000 { + compatible = "qcom,sc7180-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "gcc_bus", "ahb", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x800 0x2>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sc7180-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>, + <0 0x0af03000 0 0x16>; + reg-names = "mdp", "vbif", "disp_cc"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "rot", "lut", "core", + "vsync"; + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <300000000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi_controller: dsi-controller@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface"; + + status = "disabled"; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7180-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; -- 2.7.4

4 4

[PATCH] drm/stm: ltdc: check number of endpoints
by Yannick Fertre 04 Feb '20

04 Feb '20

Number of endpoints could exceed the fix value MAX_ENDPOINTS(2). Instead of increase simply this value, the number of endpoint could be read from device tree. Load sequence has been a little rework to take care of several panel or bridge which can be connected/disconnected or enable/disable. Signed-off-by: Yannick Fertré <yannick.fertre(a)st.com> --- drivers/gpu/drm/stm/ltdc.c | 104 ++++++++++++++++++++++----------------------- 1 file changed, 52 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index c2815e8..dba8e7f 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -42,8 +42,6 @@ #define MAX_IRQ 4 -#define MAX_ENDPOINTS 2 - #define HWVER_10200 0x010200 #define HWVER_10300 0x010300 #define HWVER_20101 0x020101 @@ -1190,36 +1188,20 @@ int ltdc_load(struct drm_device *ddev) struct ltdc_device *ldev = ddev->dev_private; struct device *dev = ddev->dev; struct device_node *np = dev->of_node; - struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL}; - struct drm_panel *panel[MAX_ENDPOINTS] = {NULL}; + struct drm_bridge *bridge; + struct drm_panel *panel; struct drm_crtc *crtc; struct reset_control *rstc; struct resource *res; - int irq, ret, i, endpoint_not_ready = -ENODEV; + int irq, i, nb_endpoints; + int ret = -ENODEV; DRM_DEBUG_DRIVER("\n"); - /* Get endpoints if any */ - for (i = 0; i < MAX_ENDPOINTS; i++) { - ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i], - &bridge[i]); - - /* - * If at least one endpoint is -EPROBE_DEFER, defer probing, - * else if at least one endpoint is ready, continue probing. - */ - if (ret == -EPROBE_DEFER) - return ret; - else if (!ret) - endpoint_not_ready = 0; - } - - if (endpoint_not_ready) - return endpoint_not_ready; - - rstc = devm_reset_control_get_exclusive(dev, NULL); - - mutex_init(&ldev->err_lock); + /* Get number of endpoints */ + nb_endpoints = of_graph_get_endpoint_count(np); + if (!nb_endpoints) + return -ENODEV; ldev->pixel_clk = devm_clk_get(dev, "lcd"); if (IS_ERR(ldev->pixel_clk)) { @@ -1233,6 +1215,43 @@ int ltdc_load(struct drm_device *ddev) return -ENODEV; } + /* Get endpoints if any */ + for (i = 0; i < nb_endpoints; i++) { + ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); + + /* + * If at least one endpoint is -ENODEV, continue probing, + * else if at least one endpoint returned an error + * (ie -EPROBE_DEFER) then stop probing. + */ + if (ret == -ENODEV) + continue; + else if (ret) + goto err; + + if (panel) { + bridge = drm_panel_bridge_add_typed(panel, + DRM_MODE_CONNECTOR_DPI); + if (IS_ERR(bridge)) { + DRM_ERROR("panel-bridge endpoint %d\n", i); + ret = PTR_ERR(bridge); + goto err; + } + } + + if (bridge) { + ret = ltdc_encoder_init(ddev, bridge); + if (ret) { + DRM_ERROR("init encoder endpoint %d\n", i); + goto err; + } + } + } + + rstc = devm_reset_control_get_exclusive(dev, NULL); + + mutex_init(&ldev->err_lock); + if (!IS_ERR(rstc)) { reset_control_assert(rstc); usleep_range(10, 20); @@ -1268,7 +1287,6 @@ int ltdc_load(struct drm_device *ddev) } } - ret = ltdc_get_caps(ddev); if (ret) { DRM_ERROR("hardware identifier (0x%08x) not supported!\n", @@ -1278,27 +1296,6 @@ int ltdc_load(struct drm_device *ddev) DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); - /* Add endpoints panels or bridges if any */ - for (i = 0; i < MAX_ENDPOINTS; i++) { - if (panel[i]) { - bridge[i] = drm_panel_bridge_add_typed(panel[i], - DRM_MODE_CONNECTOR_DPI); - if (IS_ERR(bridge[i])) { - DRM_ERROR("panel-bridge endpoint %d\n", i); - ret = PTR_ERR(bridge[i]); - goto err; - } - } - - if (bridge[i]) { - ret = ltdc_encoder_init(ddev, bridge[i]); - if (ret) { - DRM_ERROR("init encoder endpoint %d\n", i); - goto err; - } - } - } - crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); if (!crtc) { DRM_ERROR("Failed to allocate crtc\n"); @@ -1331,8 +1328,8 @@ int ltdc_load(struct drm_device *ddev) return 0; err: - for (i = 0; i < MAX_ENDPOINTS; i++) - drm_panel_bridge_remove(bridge[i]); + for (i = 0; i < nb_endpoints; i++) + drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); clk_disable_unprepare(ldev->pixel_clk); @@ -1341,11 +1338,14 @@ int ltdc_load(struct drm_device *ddev) void ltdc_unload(struct drm_device *ddev) { - int i; + struct device *dev = ddev->dev; + int nb_endpoints, i; DRM_DEBUG_DRIVER("\n"); - for (i = 0; i < MAX_ENDPOINTS; i++) + nb_endpoints = of_graph_get_endpoint_count(dev->of_node); + + for (i = 0; i < nb_endpoints; i++) drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); pm_runtime_disable(ddev->dev); -- 2.7.4

3 2

[PATCH] drm/stm: dsi: stm mipi dsi doesn't print error on probe deferral
by Yannick Fertre 04 Feb '20

04 Feb '20

From: Etienne Carriere <etienne.carriere(a)st.com> Change DSI driver to not print an error trace when probe is deferred for a clock resource. Signed-off-by: Etienne Carriere <etienne.carriere(a)st.com> --- drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c index 4b16563..2e1f266 100644 --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c @@ -377,7 +377,9 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev) dsi->pllref_clk = devm_clk_get(dev, "ref"); if (IS_ERR(dsi->pllref_clk)) { ret = PTR_ERR(dsi->pllref_clk); - DRM_ERROR("Unable to get pll reference clock: %d\n", ret); + if (ret != -EPROBE_DEFER) + DRM_ERROR("Unable to get pll reference clock: %d\n", + ret); goto err_clk_get; } -- 2.7.4

3 2

[PATCH] drm/stm: ltdc: check crtc state before enabling LIE
by Yannick Fertre 04 Feb '20

04 Feb '20

Following investigations of a hardware bug, the LIE interrupt can occur while the display controller is not activated. LIE interrupt (vblank) don't have to be set if the CRTC is not enabled. Signed-off-by: Yannick Fertre <yannick.fertre(a)st.com> --- drivers/gpu/drm/stm/ltdc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index c2815e8..ea654c7 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -648,9 +648,14 @@ static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) { struct ltdc_device *ldev = crtc_to_ltdc(crtc); + struct drm_crtc_state *state = crtc->state; DRM_DEBUG_DRIVER("\n"); - reg_set(ldev->regs, LTDC_IER, IER_LIE); + + if (state->enable) + reg_set(ldev->regs, LTDC_IER, IER_LIE); + else + return -EPERM; return 0; } -- 2.7.4

3 2

[PATCH] drm/stm: ltdc: add number of interrupts
by Yannick Fertre 04 Feb '20

04 Feb '20

The number of interrupts depends on the ltdc version. Don't try to get interrupt which not exist, avoiding kernel warning messages. Signed-off-by: Yannick Fertre <yannick.fertre(a)st.com> --- drivers/gpu/drm/stm/ltdc.c | 30 +++++++++++++++--------------- drivers/gpu/drm/stm/ltdc.h | 1 + 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index c2815e8..58092b0 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -1146,12 +1146,14 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.pad_max_freq_hz = 90000000; if (ldev->caps.hw_version == HWVER_10200) ldev->caps.pad_max_freq_hz = 65000000; + ldev->caps.nb_irq = 2; break; case HWVER_20101: ldev->caps.reg_ofs = REG_OFS_4; ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; ldev->caps.non_alpha_only_l1 = false; ldev->caps.pad_max_freq_hz = 150000000; + ldev->caps.nb_irq = 4; break; default: return -ENODEV; @@ -1251,13 +1253,21 @@ int ltdc_load(struct drm_device *ddev) reg_clear(ldev->regs, LTDC_IER, IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); - for (i = 0; i < MAX_IRQ; i++) { + ret = ltdc_get_caps(ddev); + if (ret) { + DRM_ERROR("hardware identifier (0x%08x) not supported!\n", + ldev->caps.hw_version); + goto err; + } + + DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); + + for (i = 0; i < ldev->caps.nb_irq; i++) { irq = platform_get_irq(pdev, i); - if (irq == -EPROBE_DEFER) + if (irq < 0) { + ret = irq; goto err; - - if (irq < 0) - continue; + } ret = devm_request_threaded_irq(dev, irq, ltdc_irq, ltdc_irq_thread, IRQF_ONESHOT, @@ -1268,16 +1278,6 @@ int ltdc_load(struct drm_device *ddev) } } - - ret = ltdc_get_caps(ddev); - if (ret) { - DRM_ERROR("hardware identifier (0x%08x) not supported!\n", - ldev->caps.hw_version); - goto err; - } - - DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); - /* Add endpoints panels or bridges if any */ for (i = 0; i < MAX_ENDPOINTS; i++) { if (panel[i]) { diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index a1ad0ae..310e87f 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -19,6 +19,7 @@ struct ltdc_caps { const u32 *pix_fmt_hw; /* supported pixel formats */ bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */ int pad_max_freq_hz; /* max frequency supported by pad */ + int nb_irq; /* number of hardware interrupts */ }; #define LTDC_MAX_LAYER 4 -- 2.7.4

3 2

[PATCH] drm/stm: ltdc: enable/disable depends on encoder
by Yannick Fertre 04 Feb '20

04 Feb '20

From: Yannick Fertré <yannick.fertre(a)st.com> When connected to a dsi host, the ltdc display controller must send frames only after the end of the dsi panel initialization to avoid errors when the dsi host sends commands to the dsi panel (dsi px fifo full). To avoid this issue, the display controller must be enabled/disabled when the encoder is enabled/disabled. Signed-off-by: Yannick Fertré <yannick.fertre(a)st.com> --- drivers/gpu/drm/stm/ltdc.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 719dfc5..9ef125d 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -437,9 +437,6 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, /* Commit shadow registers = update planes at next vblank */ reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); - /* Enable LTDC */ - reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); - drm_crtc_vblank_on(crtc); } @@ -453,9 +450,6 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, drm_crtc_vblank_off(crtc); - /* disable LTDC */ - reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); - /* disable IRQ */ reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); @@ -1058,9 +1052,13 @@ static const struct drm_encoder_funcs ltdc_encoder_funcs = { static void ltdc_encoder_disable(struct drm_encoder *encoder) { struct drm_device *ddev = encoder->dev; + struct ltdc_device *ldev = ddev->dev_private; DRM_DEBUG_DRIVER("\n"); + /* Disable LTDC */ + reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); + /* Set to sleep state the pinctrl whatever type of encoder */ pinctrl_pm_select_sleep_state(ddev->dev); } @@ -1068,6 +1066,7 @@ static void ltdc_encoder_disable(struct drm_encoder *encoder) static void ltdc_encoder_enable(struct drm_encoder *encoder) { struct drm_device *ddev = encoder->dev; + struct ltdc_device *ldev = ddev->dev_private; DRM_DEBUG_DRIVER("\n"); @@ -1078,6 +1077,9 @@ static void ltdc_encoder_enable(struct drm_encoder *encoder) */ if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) pinctrl_pm_select_default_state(ddev->dev); + + /* Enable LTDC */ + reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); } static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = { -- 2.7.4

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dri-devel February 2020