dri-devel July 2020

dri-devel@lists.freedesktop.org

336 participants
772 discussions

[PATCH] drm/v3d: Use platform_get_irq_optional() to get optional IRQs
by Nicolas Saenz Julienne 17 Jul '20

17 Jul '20

Aside from being more correct, the non optional version of the function prints an error when failing to find the IRQ. Fixes: eea9b97b4504 ("drm/v3d: Add support for V3D v4.2") Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne(a)suse.de> --- drivers/gpu/drm/v3d/v3d_irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/v3d/v3d_irq.c b/drivers/gpu/drm/v3d/v3d_irq.c index c88686489b88..0be2eb7876be 100644 --- a/drivers/gpu/drm/v3d/v3d_irq.c +++ b/drivers/gpu/drm/v3d/v3d_irq.c @@ -217,7 +217,7 @@ v3d_irq_init(struct v3d_dev *v3d) V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS); V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); - irq1 = platform_get_irq(v3d_to_pdev(v3d), 1); + irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1); if (irq1 == -EPROBE_DEFER) return irq1; if (irq1 > 0) { -- 2.27.0

2 1

[GIT PULL] drm/tegra: Changes for v5.9-rc1
by Thierry Reding 17 Jul '20

17 Jul '20

Hi Dave, The following changes since commit fce3a51d9b31312aa12ecb72ffabfc4c7b40bdc6: drm/tegra: Add zpos property for cursor planes (2020-06-16 19:03:25 +0200) are available in the Git repository at: ssh://git.freedesktop.org/git/tegra/linux.git tags/drm/tegra/for-5.9-rc1 for you to fetch changes up to 4fba6d22ca9ad28b8871d763b35a4da2e1ca272e: drm/tegra: plane: Support 180° rotation (2020-07-17 16:06:17 +0200) Note that I've supplied the ssh:// URL above as opposed to the git:// URL that I usually use. The latter has been somewhat spotty for me. Let me know if this is causing any issues. Thanks, Thierry ---------------------------------------------------------------- drm/tegra: Changes for v5.9-rc1 This set of patches contains a few preparatory patches to enable video capture support from external camera modules. This is a dependency for the V4L2 driver patches that will likely be merged in v5.9 or v5.10. On top of that there are a couple of fixes across the board as well as some improvements. >From a feature point of view this also adds support for horizontal reflection and 180° rotation of planes. ---------------------------------------------------------------- Dmitry Osipenko (9): gpu: host1x: Optimize BOs usage when firewall is enabled gpu: host1x: Put gather's BO on pinning error gpu: host1x: debug: Fix multiple channels emitting messages simultaneously gpu: host1x: debug: Dump push buffer state drm/tegra: gr3d: Assert reset before power-gating drm/tegra: gr2d: Add tiled PATBASE address register drm/tegra: plane: Rename bottom_up to reflect_y drm/tegra: plane: Support horizontal reflection drm/tegra: plane: Support 180° rotation Sowjanya Komatineni (3): gpu: host1x: mipi: Update tegra_mipi_request() to be node based gpu: host1x: mipi: Use readl_relaxed_poll_timeout() in tegra_mipi_wait() gpu: host1x: mipi: Split tegra_mipi_calibrate() and tegra_mipi_wait() Tang Bin (1): drm/tegra: dc: Omit superfluous error message in tegra_dc_probe() Thierry Reding (1): drm/tegra: sor: Use correct power supply names for HDMI drivers/gpu/drm/tegra/dc.c | 50 ++++++++++++++++++++++++++++++---------- drivers/gpu/drm/tegra/dc.h | 3 ++- drivers/gpu/drm/tegra/dsi.c | 9 ++++++-- drivers/gpu/drm/tegra/gr2d.c | 1 + drivers/gpu/drm/tegra/gr2d.h | 1 + drivers/gpu/drm/tegra/gr3d.c | 2 ++ drivers/gpu/drm/tegra/plane.c | 3 ++- drivers/gpu/drm/tegra/plane.h | 3 ++- drivers/gpu/drm/tegra/sor.c | 4 ++-- drivers/gpu/host1x/debug.c | 4 ++++ drivers/gpu/host1x/hw/debug_hw.c | 6 +++++ drivers/gpu/host1x/job.c | 27 ++++++++++++++++------ drivers/gpu/host1x/mipi.c | 37 ++++++++++++++++------------- include/linux/host1x.h | 4 +++- 14 files changed, 111 insertions(+), 43 deletions(-)

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[PATCH v11 0/4] Panel rotation patches
by Dmitry Osipenko 17 Jul '20

17 Jul '20

Hello! This series adds support for display panel's DT rotation property. It's a continuation of the work that was initially started by Derek Basehore for the panel driver that is used by some Mediatek device [1]. I picked up the Derek's patches and added my t-b and r-b tags to them, I also added rotation support to the panel-lvds and panel-simple drivers. We need the rotation support for the Nexus 7 tablet device which is pending to become supported by upstream kernel, the device has display panel mounted upside-down and it uses panel-lvds [2]. [1] https://lkml.org/lkml/2020/3/5/1119 [2] https://patchwork.ozlabs.org/project/linux-tegra/patch/20200607154327.18589… Changelog: v11: - This series is factored out from this patchset [3] because these patches do not have hard dependency on the Tegra DRM patches and it should be nicer to review and apply the properly grouped patches. - Initially [3] only touched the panel-lvds driver and Emil Velikov suggested that it will be better to support more panels in the review comments to [3]. So I included the Derek's patch for the BOE panel and added rotation support to the panel-simple driver. I tested that panel-lvds and panel-simple work properly with the rotated panel using the Opentegra Xorg driver [4] and Wayland Weston [5]. - The panel-lvds driver now prints a error message if rotation property fails to be parsed. [3] https://lore.kernel.org/lkml/20200614200121.14147-1-digetx@gmail.com/ [4] https://github.com/grate-driver/xf86-video-opentegra/commit/28eb20a3959bbe5… [5] https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/315 Derek Basehore (2): drm/panel: Add helper for reading DT rotation drm/panel: Read panel orientation for BOE TV101WUM-NL6 Dmitry Osipenko (2): drm/panel: lvds: Read panel orientation drm/panel-simple: Read panel orientation drivers/gpu/drm/drm_panel.c | 43 +++++++++++++++++++ .../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 6 +++ drivers/gpu/drm/panel/panel-lvds.c | 10 +++++ drivers/gpu/drm/panel/panel-simple.c | 11 +++++ include/drm/drm_panel.h | 9 ++++ 5 files changed, 79 insertions(+) -- 2.26.0

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[PATCH] drm: msm: a6xx: fix gpu failure after system resume
by Akhil P Oommen 17 Jul '20

17 Jul '20

On targets where GMU is available, GMU takes over the ownership of GX GDSC during its initialization. So, take a refcount on the GX PD on behalf of GMU before we initialize it. This makes sure that nobody can collapse the GX GDSC once GMU owns the GX GDSC. This patch fixes some weird failures during GPU wake up during system resume. Signed-off-by: Akhil P Oommen <akhilpo(a)codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index a6f43ff..5b2df7d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -873,10 +873,19 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) /* Turn on the resources */ pm_runtime_get_sync(gmu->dev); + /* + * "enable" the GX power domain which won't actually do anything but it + * will make sure that the refcounting is correct in case we need to + * bring down the GX after a GMU failure + */ + if (!IS_ERR_OR_NULL(gmu->gxpd)) + pm_runtime_get_sync(gmu->gxpd); + /* Use a known rate to bring up the GMU */ clk_set_rate(gmu->core_clk, 200000000); ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); if (ret) { + pm_runtime_put(gmu->gxpd); pm_runtime_put(gmu->dev); return ret; } @@ -919,19 +928,12 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) /* Set the GPU to the current freq */ a6xx_gmu_set_initial_freq(gpu, gmu); - /* - * "enable" the GX power domain which won't actually do anything but it - * will make sure that the refcounting is correct in case we need to - * bring down the GX after a GMU failure - */ - if (!IS_ERR_OR_NULL(gmu->gxpd)) - pm_runtime_get(gmu->gxpd); - out: /* On failure, shut down the GMU to leave it in a good state */ if (ret) { disable_irq(gmu->gmu_irq); a6xx_rpmh_stop(gmu); + pm_runtime_put(gmu->gxpd); pm_runtime_put(gmu->dev); } -- 2.7.4

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[PATCH] drm/todo: Plumb drm_atomic_state all over
by Ville Syrjala 17 Jul '20

17 Jul '20

From: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Add a TODO for plumbing drm_atomic_state all over to ease the hurdles of accessing additional object states. Reviewed-by: Daniel Vetter <daniel.vetter(a)ffwll.ch> #irc Signed-off-by: Ville Syrjälä <ville.syrjala(a)linux.intel.com> --- Documentation/gpu/todo.rst | 46 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index 7969f106877d..b0ea17da8ff6 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -403,6 +403,52 @@ Contact: Emil Velikov, respective driver maintainers Level: Intermediate +Plumb drm_atomic_state all over +------------------------------- + +Currently various atomic functions take just a single or a handful of +object states (eg. plane state). While that single object state can +suffice for some simple cases, we often have to dig out additional +object states for dealing with various dependencies between the individual +objects or the hardware they represent. The process of digging out the +additional states is rather non-intuitive and error prone. + +To fix that most functions should rather take the overall +drm_atomic_state as one of their parameters. The other parameters +would generally be the object(s) we mainly want to interact with. + +For example, instead of + +.. code-block:: c + + int (*atomic_check)(struct drm_plane *plane, struct drm_plane_state *state); + +we would have something like + +.. code-block:: c + + int (*atomic_check)(struct drm_plane *plane, struct drm_atomic_state *state); + +The implementation can then trivially gain access to any required object +state(s) via drm_atomic_get_plane_state(), drm_atomic_get_new_plane_state(), +drm_atomic_get_old_plane_state(), and their equivalents for +other object types. + +Additionally many drivers currently access the object->state pointer +directly in their commit functions. That is not going to work if we +eg. want to allow deeper commit pipelines as those pointers could +then point to the states corresponding to a future commit instead of +the current commit we're trying to process. Also non-blocking commits +execute locklessly so there are serious concerns with dereferencing +the object->state pointers without holding the locks that protect them. +Use of drm_atomic_get_new_plane_state(), drm_atomic_get_old_plane_state(), +etc. avoids these problems as well since they relate to a specific +commit via the passed in drm_atomic_state. + +Contact: Ville Syrjälä, Daniel Vetter + +Level: Intermediate + Core refactorings ================= -- 2.26.2

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[PATCH] drm: sun4i: hdmi: Fix inverted HPD result
by Chen-Yu Tsai 17 Jul '20

17 Jul '20

From: Chen-Yu Tsai <wens(a)csie.org> When the extra HPD polling in sun4i_hdmi was removed, the result of HPD was accidentally inverted. Fix this by inverting the check. Fixes: bda8eaa6dee7 ("drm: sun4i: hdmi: Remove extra HPD polling") Signed-off-by: Chen-Yu Tsai <wens(a)csie.org> --- Sorry for the screw-up. --- drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c index 557cbe5ab35f..2f2c9f0a1071 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c @@ -260,7 +260,7 @@ sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) unsigned long reg; reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG); - if (reg & SUN4I_HDMI_HPD_HIGH) { + if (!(reg & SUN4I_HDMI_HPD_HIGH)) { cec_phys_addr_invalidate(hdmi->cec_adap); return connector_status_disconnected; } -- 2.27.0

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[PATCH v6 0/6] Add support for GPU DDR BW scaling
by Akhil P Oommen 17 Jul '20

17 Jul '20

This series add support for GPU DDR bandwidth scaling and is based on the bindings from Georgi [1]. This is mostly a rebase of Sharat's patches [2] on the tip of msm-next branch. [1] https://kernel.googlesource.com/pub/scm/linux/kernel/git/vireshk/pm/+log/op… [2] https://patchwork.freedesktop.org/series/75291/ Changes from v5: - Added "interconnect-names" property Changes from v4: - Squashed a patch to another one to fix Jonathan's comment - Add back the pm_runtime_get_if_in_use() check Changes from v3: - Rebased on top of Jonathan's patch which adds support for changing gpu freq through hfi on newer targets - As suggested by Rob, left the icc_path intact for pre-a6xx GPUs Sharat Masetty (6): dt-bindings: drm/msm/gpu: Document gpu opp table drm: msm: a6xx: send opp instead of a frequency drm: msm: a6xx: use dev_pm_opp_set_bw to scale DDR arm64: dts: qcom: SDM845: Enable GPU DDR bw scaling arm64: dts: qcom: sc7180: Add interconnects property for GPU arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp .../devicetree/bindings/display/msm/gpu.txt | 28 ++++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 108 ++++++++++++--------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/msm_gpu.c | 3 +- drivers/gpu/drm/msm/msm_gpu.h | 3 +- 7 files changed, 114 insertions(+), 50 deletions(-) -- 2.7.4

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[pull] amdgpu, amdkfd drm-next-5.9
by Alex Deucher 17 Jul '20

17 Jul '20

Hi Dave, Daniel, More stuff for 5.9. The following changes since commit 9555152beb1143c85c03f9b9de59863cbbe89f4b: Merge tag 'amd-drm-next-5.9-2020-07-01' of git://people.freedesktop.org/~agd5f/linux into drm-next (2020-07-02 15:17:31 +1000) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux tags/amd-drm-next-5.9-2020-07-17 for you to fetch changes up to 6e14adea0ac3037d923a9591d1a094c115d7947c: drm/amd/amdkfd: Fix large framesize for kfd_smi_ev_read() (2020-07-15 13:27:34 -0400) ---------------------------------------------------------------- amd-drm-next-5.9-2020-07-17: amdgpu: - SI UVD/VCE clock support - Updates for Sienna Cichlid - Expose drm rotation property - Atomfirmware updates for renoir - updates to GPUVM hub handling for different register layouts - swSMU restructuring and cleanups - RAS fixes - DC fixes - mode1 reset support for Sienna Cichlid - Add support for Navy Flounder GPUs amdkfd: - Add SMI events watch interface UAPI: - Add amdkfd SMI events watch interface Userspace which uses this interface: https://github.com/RadeonOpenCompute/rocm_smi_lib/commit/2235ede34c456f1c7d… ---------------------------------------------------------------- Alex Deucher (5): drm/amdgpu/atomfirmware: fix vram_info fetching for renoir drm/amdgpu/atomfirmware: update to latest integratedinfotable drm/amdgpu/atomfirmware: update vram info handling for renoir drm/amdgpu: use %u rather than %d for sclk/mclk drm/amdgpu/display: create fake mst encoders ahead of time (v4) Alex Jivin (4): drm/amdgpu: SI support for UVD clock control drm/amdgpu: SI support for VCE clock control drm/amdgpu: SI support for UVD and VCE power managment drm/amdgpu: Move the mutex lock/unlock out Amber Lin (2): drm/amdkfd: Provide SMI events watch include/uapi/linux: Update KFD ioctl version Anthony Koo (6): drm/amd/display: [FW Promotion] Release 1.0.20 drm/amd/display: [FW Promotion] Release 1.0.21 drm/amd/display: [FW Promotion] Release 1.0.22 drm/amd/display: [FW Promotion] Release 0.0.23 drm/amd/display: 3.2.93 drm/amd/display: [FW Promotion] Release 0.0.24 Aric Cyr (2): drm/amd/display: 3.2.92 drm/amd/display: 3.2.94 Aurabindo Pillai (1): drm/amd/amdkfd: Fix large framesize for kfd_smi_ev_read() Bhawanpreet Lakha (2): drm/amd/display: Add missing reg mask for dcn3 drm/amd/display: add DC support for navy flounder Boyuan Zhang (5): drm/amdgpu: add navy_flounder vcn firmware support drm/amdgpu: add vcn ip block for navy_flounder drm/amdgpu: enable VCN3.0 PG and CG for navy_flounder drm/amdgpu: enable VCN3.0 DPG for navy_flounder drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounder Changfeng (1): Revert "drm/amd/display: add mechanism to skip DCN init" Chengming Gui (2): drm/amdkfd: Support navy_flounder KFD drm/amdkfd: Add kfd2kgd_funcs for navy_flounder kfd support Chiawen Huang (1): drm/amd/display: reduce sr_xxx_time by 3 us when ppt disable Colin Ian King (2): drm/amd/display: remove redundant initialization of variable result drm/amdgpu: fix spelling mistake "Falied" -> "Failed" Dan Carpenter (1): drm/amd/display: remove an unnecessary NULL check Dmytro Laktyushkin (4): drm/amd/display: Enable 4 to 1 mpc combine for max detile use drm/amd/display: Add diags scaling log by default drm/amd/display: update dml var drm/amd/display: fix dcn3 p_state_change_support validation (v2) Evan Quan (35): drm/amd/powerplay: drop unnecessary "@" on OD sysfs output drm/amd/powerplay: fix compile error with ARCH=arc drm/amd/powerplay: correct the .get_workload_type() pointer drm/amd/powerplay: drop unnecessary wrappers around clock retrieving drm/amd/powerplay: bypass wrapper on retrieving current clock frequency drm/amd/powerplay: unshare the code for retrieving current clock frequency drm/amd/powerplay: drop unused code and wrapper around clock retrieving drm/amd/powerplay: put setting hard limit common code in smu_v11_0.c drm/amd/powerplay: revise calling chain on setting soft limit drm/amd/powerplay: revise calling chain on retrieving frequency range drm/amd/powerplay: put dpm frequency setting common code in smu_v11_0.c drm/amd/powerplay: add more members for dpm table drm/amd/powerplay: implement a common set dpm table API for smu V11 drm/amd/powerplay: update Arcturus default dpm table setting drm/amd/powerplay: update Navi10 default dpm table setup drm/amd/powerplay: update Sienna Cichlid default dpm table setup drm/amd/powerplay: add new UMD pstate data structure drm/amd/powerplay: update UMD pstate clock settings drm/amd/powerplay: update the common API for performance level setting drm/amd/powerplay: drop unnecessary Arcturus specific APIs drm/amd/powerplay: drop unnecessary Navi1x specific APIs drm/amd/powerplay: drop unnecessary Sienna Cichlid specific APIs drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs drm/amd/powerplay: drop unnecessary wrappers drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper V2 drm/amd/powerplay: drop unused APIs and parameters drm/amd/powerplay: drop unnecessary wrapper around pcie parameters setting drm/amd/powerplay: correct the supported pcie GenSpeed and LaneCount drm/amd/powerplay: correct Navi1X temperature limit settings drm/amd/powerplay: correct Sienna Cichlid temperature limit settings drm/amd/powerplay: cache the software_shutdown_temp drm/amd/powerplay: sort the call flow on temperature ranges retrieving drm/amd/powerplay: maximum the code sharing on thermal irq setting drm/amd/powerplay: drop unused code around thermal range setting Felix Kuehling (3): drm/amdgpu: Clean up KFD VMID assignment drm/amdgpu: Let KFD use more VMIDs on Arcturus drm/amdkfd: Remove redundant kfd2kgd interface lookup Hawking Zhang (1): Revert "drm/amdgpu: support access regs outside of mmio bar" Huang Rui (15): drm/amdgpu: asd function needs to be unloaded in suspend phase drm/amdgpu: add TMR destory function for psp drm/amdgpu: add register distance members into vmhub structure drm/amdgpu: use register distance member instead of hardcode in GMC9 drm/amdgpu: use register distance member instead of hardcode in GMC10 drm/amdgpu: use register distance member instead of hardcode in VCN1/JEPG1 drm/amdgpu: use register distance member instead of hardcode in UVD7/VCE4 drm/amdgpu: use register distance member instead of hardcode in VCN2/JEPG2 drm/amdgpu: use register distance member instead of hardcode in gfxhub v1 drm/amdgpu: use register distance member instead of hardcode in gfxhub v2 drm/amdgpu: use register distance member instead of hardcode in gfxhub v2.1 drm/amdgpu: use register distance member instead of hardcode in mmhub v1 drm/amdgpu: use register distance member instead of hardcode in mmhub v2 drm/amdgpu: use register distance member instead of hardcode in mmhub v9.4 drm/amdgpu: expand to add multiple trap event irq id Igor Kravchenko (1): drm/amd/display: Register init Jack Xiao (2): drm/amdgpu/gfx10: fix race condition for kiq drm/amdgpu: fix preemption unit test Jack Zhang (5): drm/amd/sriov skip jped ip block and close pgcg flags drm/amdgpu: optimize rlcg write for gfx_v10 drm/amd/sriov add mmsch_v3 interface drm/amd/sriov porting sriov cap to vcn3.0 drm/amd/sriov skip vcn powergating and dec_ring_test Jaehyun Chung (2): drm/amd/display: Fix incorrect rounding for 10Hz refresh range drm/amd/display: Send VSIF on unsupported modes on DAL Jiansong Chen (32): drm/amdgpu: add navy_flounder asic type drm/amdgpu: add navy_flounder gpu info firmware drm/amdgpu: set fw load type for navy_flounder drm/amdgpu: set asic family and ip blocks for navy_flounder drm/amdgpu/gfx10: add support for navy_flounder firmware drm/amdgpu/gmc10: add navy_flounder support drm/amdgpu/gfx10: add clockgating support for navy_flounder drm/amdgpu/soc15: add support for navy_flounder drm/amdgpu: initialize IP offset for navy_flounder drm/amdgpu: add support on mmhub for navy_flounder drm/amdgpu: add common ip block for navy_flounder drm/amdgpu: add gmc ip block for navy_flounder drm/amdgpu: add ih ip block for navy_flounder drm/amdgpu: add gfx ip block for navy_flounder drm/amdgpu: add sdma ip block for navy_flounder drm/amdgpu: add virtual display support for navy_flounder. drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounder drm/amdgpu: add gmc cg support for navy_flounder drm/amdgpu/powerplay: add smu support for navy_flounder drm/amdgpu: add smu block for navy_flounder drm/amdgpu: add psp support for navy_flounder drm/amdgpu: add psp block for navy_flounder drm/amdgpu: use front door firmware loading for navy_flounder drm/amdgpu/gfx10: add gc golden setting for navy_flounder drm/amdgpu: enable cp_fw_write_wait for navy_flounder drm/amdgpu: enable GFX clock gating for navy_flounder drm/amdgpu: support athub cg setting for navy_flounder drm/amd/powerplay: set VCN1 pg only for sienna_cichlid drm/amdgpu: enable athub/mmhub PG for navy_flounder drm/amdgpu: enable mc CG and LS for navy_flounder drm/amdgpu: enable hdp CG and LS for navy_flounder drm/amdgpu: enable ih CG for navy_flounder Jing Zhou (1): drm/amd/display: Add register key and status for edid John Clements (3): drm/amdgpu: updated ta ucode header drm/amdgpu: updated ta ucode loading drm/amdgpu: correct ta header v2 ucode init start address Joseph Greathouse (2): drm/amdkfd: Update hardware scheduling time quanta drm/amdkfd: Add Arcturus GWS support and fix VG10 Joshua Aberback (2): drm/amd/display: Preserve gpu memory allocation for life of dc drm/amd/display: Request PHYCLK adjustment on PHY enable/disable Josip Pavic (1): drm/amd/display: handle failed allocation during stream construction Likun Gao (7): drm/amd/powerplay: change method to set board parameters drm/amd/powerplay: update driver if file for sienna_cichlid drm/amdgpu: use RREG32_KIQ to read register when get cg state drm/amdgpu: fix coding error of mmhub pg enablement drm/amdgpu: remove unnecessary logic of ASIC check drm/amdgpu: enable gpu recovery for sienna cichlid drm/amd/powerplay: update driver if file for sienna_cichlid Marek Olšák (1): drm/amdgpu: don't do soft recovery if gpu_recovery=0 Mikita Lipski (1): drm/amd/display: Reuse parsing code of debugfs write buffer Monk Liu (1): drm/amdgpu: make IB test synchronize with init for SRIOV(v2) Nicholas Kazlauskas (6): drm/amd/display: Only revalidate bandwidth on medium and fast updates drm/amd/display: Add missing CW4 programming for DCN30 drm/amd/display: Use VUPDATE_NO_LOCK instead of VUPDATE for dcn30 drm/amd/display: Fix CSC remap matrix not being applied on dcn30 drm/amd/display: Add missing DCN30 registers and fields for OTG_CRC_CNTL2 drm/amd/display: Allow for vblank enabled with no active planes Nirmoy Das (1): drm/amdgpu: minor cleanup of phase1 suspend code Pierre-Loup A. Griffais (1): drm/amd/display: Create plane rotation property Rajneesh Bhardwaj (1): drm/amdkfd: fix kernel-doc and cleanup Roman Li (1): drm/amd/display: Remove VSC infoframe dep on DMCU Sung Lee (1): drm/amd/display: Power down hardware if set mode is not called before timeout Tao Zhou (1): drm/amdgpu: configure navy_flounder gfx according to gfx 10.3 Tiezhu Yang (1): gpu/drm: Remove debug info about CPU address Tom Rix (1): drm/radeon: fix double free Wenhui Sheng (10): drm/amdgpu: request init data in virt detection drm/amdgpu: move reg base init forward for soc15 drm/amdgpu: invoke req full access early enough drm/amdgpu: merge atombios init block drm/amdgpu: reduce ip discovery data reading size drm/amdgpu: correct discovery_tmr_size init val drm/amd/powerplay: add SMU mode1 reset drm/amdgpu: RAS emergency restart logic refine drm/amdgpu: enable mode1 reset drm/amdgpu: add module parameter choose reset mode Wesley Chalmers (1): drm/amd/display: Add logger for SMU msg Wyatt Wood (1): drm/amd/display: Initialize psr debug flags to 0 Xiaojie Yuan (2): drm/amdgpu: use ARRAY_SIZE() to add amdgpu debugfs files drm/amdgpu/sdma5: fix wptr overwritten in ->get_wptr() Yongqiang Sun (1): drm/amd/display: Handle SMU msg response chen gong (2): drm/amdgpu/powerplay: Target power profile mode should be the second parameter of renoir_set_power_profile_mode drm/amdgpu/powerplay: Modify SMC message name for setting power profile mode hersen wu (2): drm/amd/display: OLED panel backlight adjust not work with external display connected drm/amd/display: p-state warning occurs while changing resolution from 120hz to 60hz jinlong zhang (1): drm/amd/display: check dpcd read status of DP_DOWNSTREAM_PORT_0 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 28 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 12 +- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 10 + drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 26 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 143 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 26 +- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 + drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 11 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 9 + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 79 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 172 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 11 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 26 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 12 + drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 28 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 + drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 1 + drivers/gpu/drm/amd/amdgpu/cik.c | 8 + drivers/gpu/drm/amd/amdgpu/cikd.h | 2 - drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 132 +++- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 48 +- drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 47 +- drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 47 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 75 +- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 55 +- drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 45 +- drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 52 +- drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 46 +- drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h | 130 +++ drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 + drivers/gpu/drm/amd/amdgpu/nv.c | 97 ++- drivers/gpu/drm/amd/amdgpu/nv.h | 1 + drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 12 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 34 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 119 +-- drivers/gpu/drm/amd/amdgpu/si.c | 365 ++++++++- drivers/gpu/drm/amd/amdgpu/si_dpm.c | 19 + drivers/gpu/drm/amd/amdgpu/si_enums.h | 1 - drivers/gpu/drm/amd/amdgpu/sid.h | 35 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 36 +- drivers/gpu/drm/amd/amdgpu/soc15.h | 1 + drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 5 +- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 5 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 5 +- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 371 ++++++++- drivers/gpu/drm/amd/amdgpu/vi.c | 16 +- drivers/gpu/drm/amd/amdgpu/vi.h | 1 + drivers/gpu/drm/amd/amdgpu/vid.h | 2 - drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c | 2 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 18 + drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_device.c | 35 +- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 2 + drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_pasid.c | 31 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 65 +- drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 227 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h | 29 + drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 229 +++--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 259 +++--- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 53 +- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 3 + drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 3 - .../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c | 39 +- .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 35 +- .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 70 +- .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 51 +- .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h | 1 + .../amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 53 +- .../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 65 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 21 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 105 +-- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 16 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 39 +- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 19 +- drivers/gpu/drm/amd/display/dc/dc.h | 6 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 28 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 2 - drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 156 ++-- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 1 + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 1 + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 27 +- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 + .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 24 +- drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 + .../display/dc/dcn30/dcn30_dio_stream_encoder.h | 1 + drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h | 9 + .../gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 46 +- .../amd/display/dc/dml/dcn30/display_mode_vba_30.c | 8 +- .../drm/amd/display/dc/dml/display_mode_structs.h | 2 + .../gpu/drm/amd/display/dc/dml/display_mode_vba.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 3 + .../drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 5 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 + .../amd/display/dc/irq/dcn30/irq_service_dcn30.c | 28 +- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 5 +- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 23 +- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 15 - drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 4 - drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 10 + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h | 6 + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c | 21 +- drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 40 +- drivers/gpu/drm/amd/display/include/logger_types.h | 4 +- .../drm/amd/display/modules/freesync/freesync.c | 37 +- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 7 +- drivers/gpu/drm/amd/include/atomfirmware.h | 78 ++ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 281 +++---- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 878 ++++++++------------- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 51 +- .../powerplay/inc/smu11_driver_if_sienna_cichlid.h | 27 +- drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 + drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 55 +- drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 11 - drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 656 +++++++-------- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 277 +++++-- drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 20 - drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 714 ++++++++--------- drivers/gpu/drm/amd/powerplay/smu_internal.h | 14 +- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 461 +++++++---- drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 121 --- drivers/gpu/drm/radeon/ci_dpm.c | 7 +- drivers/gpu/drm/radeon/radeon_fence.c | 4 +- include/drm/amd_asic_type.h | 1 + include/uapi/linux/kfd_ioctl.h | 22 +- 158 files changed, 5162 insertions(+), 3019 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h

1 0

[PATCH v5 0/4] Add support for iMX8MQ Display Controller Subsystem
by Laurentiu Palcu 17 Jul '20

17 Jul '20

From: Laurentiu Palcu <laurentiu.palcu(a)nxp.com> Hi, This patchset adds initial DCSS support for iMX8MQ chip. Initial support includes only graphics plane support (no video planes), no HDR10 capabilities, no graphics decompression (only linear, tiled and super-tiled buffers allowed). Support for the rest of the features will be added incrementally, in subsequent patches. The patchset was tested with both HDP driver (in the downstream tree) and the upstream MIPI-DSI driver (with a couple of patches on top, to make it work correctly with DCSS). Thanks, Laurentiu Changes in v5: * Rebased to latest; * Took out component framework support and made it a separate patch so that people can still test with HDP driver, which makes use of it. But the idea is to get rid of it once HDP driver's next versions will remove component framework as well; * Slight improvement to modesetting: avoid cutting off the pixel clock if the new mode and the old one are equal. Also, in this case, is not necessary to wait for DTG to shut off. This would allow to switch from 8b RGB to 12b YUV422, for example, with no interruptions (at least from DCSS point of view); * Do not fire off CTXLD when going to suspend, unless it still has entries that need to be committed to DCSS; * Addressed Rob's comments on bindings; Changes in v4: * Addressed Lucas and Philipp's comments: * Added DRM_KMS_CMA_HELPER dependency in Kconfig; * Removed usage of devm_ functions since I'm already doing all the clean-up in the submodules_deinit(); * Moved the drm_crtc_arm_vblank_event() in dcss_crtc_atomic_flush(); * Removed en_completion variable from dcss_crtc since this was introduced mainly to avoid vblank timeout warnings which were fixed by arming the vblank event in flush() instead of begin(); * Removed clks_on and irq_enabled flags since all the calls to enabling/disabling clocks and interrupts were balanced; * Removed the custom atomic_commit callback and used the DRM core helper and, in the process, got rid of a workqueue that wasn't necessary anymore; * Fixed some minor DT binding issues flagged by Philipp; * Some other minor changes suggested by Lucas; * Removed YUV formats from the supported formats as these cannot work without the HDR10 module CSCs and LUTs. Will add them back when I will add support for video planes; Changes in v3: * rebased to latest linux-next and made it compile as drmP.h was removed; * removed the patch adding the VIDEO2_PLL clock. It's already applied; * removed an unnecessary 50ms sleep in the dcss_dtg_sync_set(); * fixed a a spurious hang reported by Lukas Hartmann and encountered by me several times; * mask DPR and DTG interrupts by default, as they may come enabled from U-boot; Changes in v2: * Removed '0x' in node's unit-address both in DT and yaml; * Made the address region size lowercase, to be consistent; * Removed some left-over references to P010; * Added a Kconfig dependency of DRM && ARCH_MXC. This will also silence compilation issues reported by kbuild for other architectures; Laurentiu Palcu (5): drm/imx: compile imx directory by default drm/imx: Add initial support for DCSS on iMX8MQ drm/imx/dcss: add component framework functionality dt-bindings: display: imx: add bindings for DCSS arm64: dts: imx8mq: add DCSS node .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 84 ++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 + drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/imx/Kconfig | 2 + drivers/gpu/drm/imx/Makefile | 1 + drivers/gpu/drm/imx/dcss/Kconfig | 9 + drivers/gpu/drm/imx/dcss/Makefile | 6 + drivers/gpu/drm/imx/dcss/dcss-blkctl.c | 70 ++ drivers/gpu/drm/imx/dcss/dcss-crtc.c | 219 +++++ drivers/gpu/drm/imx/dcss/dcss-ctxld.c | 424 +++++++++ drivers/gpu/drm/imx/dcss/dcss-dev.c | 314 +++++++ drivers/gpu/drm/imx/dcss/dcss-dev.h | 177 ++++ drivers/gpu/drm/imx/dcss/dcss-dpr.c | 562 ++++++++++++ drivers/gpu/drm/imx/dcss/dcss-drv.c | 183 ++++ drivers/gpu/drm/imx/dcss/dcss-dtg.c | 409 +++++++++ drivers/gpu/drm/imx/dcss/dcss-kms.c | 185 ++++ drivers/gpu/drm/imx/dcss/dcss-kms.h | 43 + drivers/gpu/drm/imx/dcss/dcss-plane.c | 405 +++++++++ drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 ++++++++++++++++++ drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++++ 20 files changed, 4123 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig create mode 100644 drivers/gpu/drm/imx/dcss/Makefile create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c -- 2.23.0

4 13

[PATCH 0/3] drm/vram-helper: Update GEM VRAM object creation
by Thomas Zimmermann 17 Jul '20

17 Jul '20

This patchset updates drm_gem_vram_create() and related code. The first patch fixes a double-free bug in the error path. Patch #2 simplifies the object creation. Patch #3 allow drivers to override GEM functions. Jia Yang (1): drm: fix double free for gbo in drm_gem_vram_init and drm_gem_vram_create Thomas Zimmermann (2): drm/vram-helper: Integrate drm_gem_vram_init() into drm_gem_vram_create() drm/vram-helper: Set object function iff they are not provided by driver drivers/gpu/drm/drm_gem_vram_helper.c | 79 +++++++++++---------------- 1 file changed, 33 insertions(+), 46 deletions(-) -- 2.27.0

2 6

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dri-devel July 2020