dri-devel July 2020

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[PATCH] drm/msm/adreno: fix gpu probe if no interconnect-names
by Rob Clark 15 Jul '20

15 Jul '20

From: Rob Clark <robdclark(a)chromium.org> If there is no interconnect-names, but there is an interconnects property, then of_icc_get(dev, "gfx-mem"); would return an error rather than NULL. Also, if there is no interconnect-names property, there will never be a ocmem path. But of_icc_get(dev, "ocmem") would return -EINVAL instead of -ENODATA. Just don't bother trying in this case. v2: explicity check for interconnect-names property Fixes: 8e29fb37b301 ("drm/msm: handle for EPROBE_DEFER for of_icc_get") Fixes: 00bb9243d346 ("drm/msm/gpu: add support for ocmem interconnect path") Signed-off-by: Rob Clark <robdclark(a)chromium.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 0527e85184e1..e23641a5ec84 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1003,22 +1003,23 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, if (ret) return ret; - /* Check for an interconnect path for the bus */ - gpu->icc_path = of_icc_get(dev, "gfx-mem"); - if (!gpu->icc_path) { - /* - * Keep compatbility with device trees that don't have an - * interconnect-names property. - */ + /* + * The legacy case, before "interconnect-names", only has a + * single interconnect path which is equivalent to "gfx-mem" + */ + if (!of_find_property(dev->of_node, "interconnect-names", NULL)) { gpu->icc_path = of_icc_get(dev, NULL); + } else { + gpu->icc_path = of_icc_get(dev, "gfx-mem"); + gpu->ocmem_icc_path = of_icc_get(dev, "ocmem"); } + if (IS_ERR(gpu->icc_path)) { ret = PTR_ERR(gpu->icc_path); gpu->icc_path = NULL; return ret; } - gpu->ocmem_icc_path = of_icc_get(dev, "ocmem"); if (IS_ERR(gpu->ocmem_icc_path)) { ret = PTR_ERR(gpu->ocmem_icc_path); gpu->ocmem_icc_path = NULL; @@ -1026,6 +1027,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, if (ret != -ENODATA) return ret; } + return 0; } -- 2.26.2

2 1

[radeon-alex:drm-next 140/193] drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:1233:3: warning: variable 'direct_poll' set but not used
by kernel test robot 15 Jul '20

15 Jul '20

tree: git://people.freedesktop.org/~agd5f/linux.git drm-next head: d7373aaf738393f38f40b0570bfa1403584eb982 commit: 1f61a43fcec1dceac2ec537a63aba6846dd0e80a [140/193] drm/amd/sriov porting sriov cap to vcn3.0 config: parisc-allyesconfig (attached as .config) compiler: hppa-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 1f61a43fcec1dceac2ec537a63aba6846dd0e80a # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=parisc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com> All warnings (new ones prefixed by >>): drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c: In function 'vcn_v3_0_start_sriov': >> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:1233:3: warning: variable 'direct_poll' set but not used [-Wunused-but-set-variable] 1233 | direct_poll = { {0} }; | ^~~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:25: At top level: drivers/gpu/drm/amd/amdgpu/amdgpu.h:192:19: warning: 'debug_evictions' defined but not used [-Wunused-const-variable=] 192 | static const bool debug_evictions; /* = false */ | ^~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/amdgpu.h:191:18: warning: 'sched_policy' defined but not used [-Wunused-const-variable=] 191 | static const int sched_policy = KFD_SCHED_POLICY_HWS; | ^~~~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:33, from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30, from drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26, from drivers/gpu/drm/amd/amdgpu/amdgpu.h:65, from drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:25: drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning: 'dc_fixpt_ln2_div_2' defined but not used [-Wunused-const-variable=] 76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL }; | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:75:32: warning: 'dc_fixpt_ln2' defined but not used [-Wunused-const-variable=] 75 | static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL }; | ^~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:74:32: warning: 'dc_fixpt_e' defined but not used [-Wunused-const-variable=] 74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL }; | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning: 'dc_fixpt_two_pi' defined but not used [-Wunused-const-variable=] 73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL }; | ^~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning: 'dc_fixpt_pi' defined but not used [-Wunused-const-variable=] 72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL }; | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:67:32: warning: 'dc_fixpt_zero' defined but not used [-Wunused-const-variable=] 67 | static const struct fixed31_32 dc_fixpt_zero = { 0 }; | ^~~~~~~~~~~~~ vim +/direct_poll +1233 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 1210 1211 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1212 { 1213 int i, j; 1214 struct amdgpu_ring *ring; 1215 uint64_t cache_addr; 1216 uint64_t rb_addr; 1217 uint64_t ctx_addr; 1218 uint32_t param, resp, expected; 1219 uint32_t offset, cache_size; 1220 uint32_t tmp, timeout; 1221 uint32_t id; 1222 1223 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1224 uint32_t *table_loc; 1225 uint32_t table_size; 1226 uint32_t size, size_dw; 1227 1228 struct mmsch_v3_0_cmd_direct_write 1229 direct_wt = { {0} }; 1230 struct mmsch_v3_0_cmd_direct_read_modify_write 1231 direct_rd_mod_wt = { {0} }; 1232 struct mmsch_v3_0_cmd_direct_polling > 1233 direct_poll = { {0} }; 1234 struct mmsch_v3_0_cmd_end end = { {0} }; 1235 struct mmsch_v3_0_init_header header; 1236 1237 direct_wt.cmd_header.command_type = 1238 MMSCH_COMMAND__DIRECT_REG_WRITE; 1239 direct_rd_mod_wt.cmd_header.command_type = 1240 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1241 direct_poll.cmd_header.command_type = 1242 MMSCH_COMMAND__DIRECT_REG_POLLING; 1243 end.cmd_header.command_type = 1244 MMSCH_COMMAND__END; 1245 1246 header.version = MMSCH_VERSION; 1247 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1248 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1249 header.inst[i].init_status = 0; 1250 header.inst[i].table_offset = 0; 1251 header.inst[i].table_size = 0; 1252 } 1253 1254 table_loc = (uint32_t *)table->cpu_addr; 1255 table_loc += header.total_size; 1256 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1257 if (adev->vcn.harvest_config & (1 << i)) 1258 continue; 1259 1260 table_size = 0; 1261 1262 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1263 mmUVD_STATUS), 1264 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1265 1266 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1267 1268 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1269 id = amdgpu_ucode_id_vcns[i]; 1270 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1271 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1272 adev->firmware.ucode[id].tmr_mc_addr_lo); 1273 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1274 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1275 adev->firmware.ucode[id].tmr_mc_addr_hi); 1276 offset = 0; 1277 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1278 mmUVD_VCPU_CACHE_OFFSET0), 1279 0); 1280 } else { 1281 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1282 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1283 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1284 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1285 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1286 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1287 offset = cache_size; 1288 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1289 mmUVD_VCPU_CACHE_OFFSET0), 1290 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1291 } 1292 1293 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1294 mmUVD_VCPU_CACHE_SIZE0), 1295 cache_size); 1296 1297 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1298 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1299 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1300 lower_32_bits(cache_addr)); 1301 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1302 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1303 upper_32_bits(cache_addr)); 1304 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1305 mmUVD_VCPU_CACHE_OFFSET1), 1306 0); 1307 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1308 mmUVD_VCPU_CACHE_SIZE1), 1309 AMDGPU_VCN_STACK_SIZE); 1310 1311 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1312 AMDGPU_VCN_STACK_SIZE; 1313 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1314 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1315 lower_32_bits(cache_addr)); 1316 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1317 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1318 upper_32_bits(cache_addr)); 1319 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1320 mmUVD_VCPU_CACHE_OFFSET2), 1321 0); 1322 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1323 mmUVD_VCPU_CACHE_SIZE2), 1324 AMDGPU_VCN_CONTEXT_SIZE); 1325 1326 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1327 ring = &adev->vcn.inst[i].ring_enc[j]; 1328 ring->wptr = 0; 1329 rb_addr = ring->gpu_addr; 1330 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1331 mmUVD_RB_BASE_LO), 1332 lower_32_bits(rb_addr)); 1333 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1334 mmUVD_RB_BASE_HI), 1335 upper_32_bits(rb_addr)); 1336 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1337 mmUVD_RB_SIZE), 1338 ring->ring_size / 4); 1339 } 1340 1341 ring = &adev->vcn.inst[i].ring_dec; 1342 ring->wptr = 0; 1343 rb_addr = ring->gpu_addr; 1344 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1345 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1346 lower_32_bits(rb_addr)); 1347 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1348 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1349 upper_32_bits(rb_addr)); 1350 /* force RBC into idle state */ 1351 tmp = order_base_2(ring->ring_size); 1352 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1353 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1354 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1355 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1356 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1357 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1358 mmUVD_RBC_RB_CNTL), 1359 tmp); 1360 1361 /* add end packet */ 1362 MMSCH_V3_0_INSERT_END(); 1363 1364 /* refine header */ 1365 header.inst[i].init_status = 1; 1366 header.inst[i].table_offset = header.total_size; 1367 header.inst[i].table_size = table_size; 1368 header.total_size += table_size; 1369 } 1370 1371 /* Update init table header in memory */ 1372 size = sizeof(struct mmsch_v3_0_init_header); 1373 table_loc = (uint32_t *)table->cpu_addr; 1374 memcpy((void *)table_loc, &header, size); 1375 1376 /* message MMSCH (in VCN[0]) to initialize this client 1377 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1378 * of memory descriptor location 1379 */ 1380 ctx_addr = table->gpu_addr; 1381 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1382 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1383 1384 /* 2, update vmid of descriptor */ 1385 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1386 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1387 /* use domain0 for MM scheduler */ 1388 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1389 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1390 1391 /* 3, notify mmsch about the size of this descriptor */ 1392 size = header.total_size; 1393 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1394 1395 /* 4, set resp to zero */ 1396 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1397 1398 /* 5, kick off the initialization and wait until 1399 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1400 */ 1401 param = 0x10000001; 1402 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1403 tmp = 0; 1404 timeout = 1000; 1405 resp = 0; 1406 expected = param + 1; 1407 while (resp != expected) { 1408 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1409 if (resp == expected) 1410 break; 1411 1412 udelay(10); 1413 tmp = tmp + 10; 1414 if (tmp >= timeout) { 1415 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1416 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1417 "(expected=0x%08x, readback=0x%08x)\n", 1418 tmp, expected, resp); 1419 return -EBUSY; 1420 } 1421 } 1422 1423 return 0; 1424 } 1425 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

1 0

[Bug 208413] New: amdgpu driver crash
by bugzilla-daemon＠bugzilla.kernel.org 15 Jul '20

15 Jul '20

https://bugzilla.kernel.org/show_bug.cgi?id=208413 Bug ID: 208413 Summary: amdgpu driver crash Product: Drivers Version: 2.5 Kernel Version: 5.8 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: ghutzriop(a)gmail.com Regression: No Created attachment 290063 --> https://bugzilla.kernel.org/attachment.cgi?id=290063&action=edit dmesg from hang Linux freezes after a while of desktop usage with Gnome 3 on wayland. The CPU is a Ryzen 4700u without a dedicated GPU. The freezes occurred on kernel 5.7 as well. -- You are receiving this mail because: You are watching the assignee of the bug.

1 4

[PATCH] drm/msm/adreno: fix gpu probe if no interconnect-names
by Rob Clark 15 Jul '20

15 Jul '20

From: Rob Clark <robdclark(a)chromium.org> If there is no interconnect-names, but there is an interconnects property, then of_icc_get(dev, "gfx-mem"); would return an error rather than NULL. Also, if there is no interconnect-names property, there will never be a ocmem path. But of_icc_get(dev, "ocmem") would return -EINVAL instead of -ENODATA. Just don't bother trying in this case. Fixes: 8e29fb37b301 ("drm/msm: handle for EPROBE_DEFER for of_icc_get") Signed-off-by: Rob Clark <robdclark(a)chromium.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 0527e85184e1..c4ac998b90c8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -979,6 +979,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_platform_config *config = dev->platform_data; struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; + bool has_interconnect_names = true; int ret; adreno_gpu->funcs = funcs; @@ -1005,12 +1006,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, /* Check for an interconnect path for the bus */ gpu->icc_path = of_icc_get(dev, "gfx-mem"); - if (!gpu->icc_path) { + if (IS_ERR_OR_NULL(gpu->icc_path)) { /* * Keep compatbility with device trees that don't have an * interconnect-names property. */ gpu->icc_path = of_icc_get(dev, NULL); + has_interconnect_names = false; } if (IS_ERR(gpu->icc_path)) { ret = PTR_ERR(gpu->icc_path); @@ -1018,7 +1020,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, return ret; } - gpu->ocmem_icc_path = of_icc_get(dev, "ocmem"); + if (has_interconnect_names) + gpu->ocmem_icc_path = of_icc_get(dev, "ocmem"); + if (IS_ERR(gpu->ocmem_icc_path)) { ret = PTR_ERR(gpu->ocmem_icc_path); gpu->ocmem_icc_path = NULL; -- 2.26.2

2 2

[PATCH v2 00/59] Add support for KeemBay DRM driver
by Anitha Chrisanthus 15 Jul '20

15 Jul '20

This is a new DRM driver for Intel's KeemBay SOC. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU. This driver is tested with the KMB EVM board which is the refernce baord for Keem Bay SOC. The SOC's display pipeline is as follows +--------------+ +---------+ +-----------------------+ |LCD controller| -> |Mipi DSI | -> |Mipi to HDMI Converter | +--------------+ +---------+ +-----------------------+ LCD controller and Mipi DSI transmitter are part of the SOC and mipi to HDMI converter is ADV7535 for KMB EVM board. The DRM driver is a basic KMS atomic modesetting display driver and has no 2D or 3D graphics.It calls into the ADV bridge driver at the connector level. Only 1080p resolution and single plane is supported at this time. The usecase is for debugging video and camera outputs. Device tree patches are under review here https://lore.kernel.org/linux-arm-kernel/20200708175020.194436-1-daniele.al… Changes since v1: - Removed redundant license text, updated license - Rearranged include blocks - renamed global vars and removed extern in c - Used upclassing for dev_private - Used drm_dev_init in drm device create (will be updated to use devm_drm_dev_alloc() in a separate patch later as kmb driver is currently developed on 5.4 kernel) - minor cleanups Anitha Chrisanthus (52): drm/kmb: Add support for KeemBay Display drm/kmb: Added id to kmb_plane drm/kmb: Set correct values in the LAYERn_CFG register drm/kmb: Use biwise operators for register definitions drm/kmb: Updated kmb_plane_atomic_check drm/kmb: Initial check-in for Mipi DSI drm/kmb: Set OUT_FORMAT_CFG register drm/kmb: Added mipi_dsi_host initialization drm/kmb: Part 1 of Mipi Tx Initialization drm/kmb: Part 2 of Mipi Tx Initialization drm/kmb: Use correct mmio offset from data book drm/kmb: Part3 of Mipi Tx initialization drm/kmb: Part4 of Mipi Tx Initialization drm/kmb: Correct address offsets for mipi registers drm/kmb: Part5 of Mipi Tx Intitialization drm/kmb: Part6 of Mipi Tx Initialization drm/kmb: Part7 of Mipi Tx Initialization drm/kmb: Part8 of Mipi Tx Initialization drm/kmb: Added ioremap/iounmap for register access drm/kmb: Register IRQ for LCD drm/kmb: IRQ handlers for LCD and mipi dsi drm/kmb: Set hardcoded values to LCD_VSYNC_START drm/kmb: Additional register programming to update_plane drm/kmb: Add ADV7535 bridge drm/kmb: Display clock enable/disable drm/kmb: rebase to newer kernel version drm/kmb: minor name change to match device tree drm/kmb: Changed MMIO size drm/kmb: Defer Probe drm/kmb: call bridge init in the very beginning drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable drm/kmb: Mipi DPHY initialization changes drm/kmb: Fixed driver unload drm/kmb: Added LCD_TEST config drm/kmb: Changes for LCD to Mipi drm/kmb: Update LCD programming to match MIPI drm/kmb: Changed name of driver to kmb-drm drm/kmb: Mipi settings from input timings drm/kmb: Enable LCD interrupts drm/kmb: Enable LCD interrupts during modeset drm/kmb: Don’t inadvertantly disable LCD controller drm/kmb: SWAP R and B LCD Layer order drm/kmb: Disable ping pong mode drm/kmb: Do the layer initializations only once drm/kmb: disable the LCD layer in EOF irq handler drm/kmb: Initialize uninitialized variables drm/kmb: Added useful messages in LCD ISR kmb/drm: Prune unsupported modes drm/kmb: workaround for dma undeflow issue drm/kmb: Get System Clock from SCMI drm/kmb: work around for planar formats Edmund Dea (7): drm/kmb: Cleanup probe functions drm/kmb: Revert dsi_host back to a static variable drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg. drm/kmb: Remove declaration of irq_lcd/irq_mipi drm/kmb: Enable MIPI TX HS Test Pattern Generation drm/kmb: Write to LCD_LAYERn_CFG only once drm/kmb: Cleaned up code drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/kmb/Kconfig | 12 + drivers/gpu/drm/kmb/Makefile | 2 + drivers/gpu/drm/kmb/kmb_crtc.c | 226 +++++ drivers/gpu/drm/kmb/kmb_crtc.h | 41 + drivers/gpu/drm/kmb/kmb_drv.c | 809 ++++++++++++++++ drivers/gpu/drm/kmb/kmb_drv.h | 176 ++++ drivers/gpu/drm/kmb/kmb_dsi.c | 1927 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 370 ++++++++ drivers/gpu/drm/kmb/kmb_plane.c | 518 +++++++++++ drivers/gpu/drm/kmb/kmb_plane.h | 124 +++ drivers/gpu/drm/kmb/kmb_regs.h | 738 +++++++++++++++ 13 files changed, 4946 insertions(+) create mode 100644 drivers/gpu/drm/kmb/Kconfig create mode 100644 drivers/gpu/drm/kmb/Makefile create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.c create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.h create mode 100644 drivers/gpu/drm/kmb/kmb_drv.c create mode 100644 drivers/gpu/drm/kmb/kmb_drv.h create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.c create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.h create mode 100644 drivers/gpu/drm/kmb/kmb_plane.c create mode 100644 drivers/gpu/drm/kmb/kmb_plane.h create mode 100644 drivers/gpu/drm/kmb/kmb_regs.h -- 2.7.4

4 64

[PATCH 0/3] Support for tft displays based on ilitek,ili9488
by Kamlesh Gurudasani 15 Jul '20

15 Jul '20

The goal of this series is to get the displays based on ilitek,ili9488 working. Eastrising,er-tft035-6 is a display based on ilitek,ili9488 Kamlesh Gurudasani (3): dt-bindings: add vendor prefix for EastRising Technology Co.,Ltd dt-bindings: add binding for Ilitek ili9488 based display panels drm/tiny: add support for tft displays based on ilitek,ili9488 .../bindings/display/ilitek,ili9488.yaml | 71 ++++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + MAINTAINERS | 7 + drivers/gpu/drm/tiny/Kconfig | 13 + drivers/gpu/drm/tiny/Makefile | 1 + drivers/gpu/drm/tiny/ili9488.c | 446 +++++++++++++++++++++ 6 files changed, 540 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9488.yaml create mode 100644 drivers/gpu/drm/tiny/ili9488.c -- 2.7.4

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Re: [PATCH] drm/nouveau: add the missed kfree() for nouveau_bo_alloc()
by Markus Elfring 15 Jul '20

15 Jul '20

> … to fix it. I suggest to replace this wording by the tag “Fixes”. … > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c > @@ -276,8 +276,10 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 flags, > break; > } > > - if (WARN_ON(pi < 0)) > + if (WARN_ON(pi < 0)) { > + kfree(nvbo); > return ERR_PTR(-EINVAL); > + } I propose to move such common exception handling to the end of this function implementation so that a bit of duplicate code will be avoided. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Doc… Regards, Markus

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[PATCH 0/9] drm/msm: Avoid possible infinite probe deferral and speed booting
by Douglas Anderson 15 Jul '20

15 Jul '20

I found that if I ever had a little mistake in my kernel config, or device tree, or graphics driver that my system would sit in a loop at bootup trying again and again and again. An example log was: msm ae00000.mdss: bound ae01000.mdp (ops 0xffffffe596e951f8) msm_dsi ae94000.dsi: ae94000.dsi supply gdsc not found, using dummy regulator msm_dsi_manager_register: failed to register mipi dsi host for DSI 0 [drm:ti_sn_bridge_probe] *ERROR* could not find any panel node ... I finally tracked it down where this was happening: - msm_pdev_probe() is called. - msm_pdev_probe() registers drivers. Registering drivers kicks off processing of probe deferrals. - component_master_add_with_match() could return -EPROBE_DEFER. making msm_pdev_probe() return -EPROBE_DEFER. - When msm_pdev_probe() returned the processing of probe deferrals happens. - Loop back to the start. It looks like we can fix this by marking "mdss" as a "simple-bus". I have no idea if people consider this the right thing to do or a hack. Hopefully it's the right thing to do. :-) Once I do this I notice that my boot gets marginally faster (you don't need to probe the sub devices over and over) and also if I have a problem it doesn't loop forever (on my system it still gets upset about some stuck clocks in that case, but at least I can boot up). Unless someone hates this, I'd expect: - Get Rob H to say that the bindings are OK (if they are) and yell that these really need to be converted to yaml (they do). - Get Sean or Rob C to land the bindings and driver patch. - Get Andy or Bjorn to land the dts bits. NOTES: - The first patch could land either way. It's just a cleanup. - I tried to split the dts files into separate patches to ease backporting if desired. Also because I can't actually test most of this hardware myself. Douglas Anderson (9): drm/msm: Use the devm variant of of_platform_populate() dt-bindings: msm/dpu: Add simple-bus to dpu bindings dt-bindings: msm/mdp5: Add simple-bus to dpu bindings drm/msm: Avoid manually populating our children if "simple-bus" is there arm64: dts: qcom: sc7180: Add "simple-bus" to our mdss node arm64: dts: qcom: sdm845: Add "simple-bus" to our mdss node arm64: dts: qcom: msm8916: Add "simple-bus" to our mdss node arm64: dts: qcom: msm8996: Add "simple-bus" to our mdss node ARM: dts: qcom: msm8974: Add "simple-bus" to our mdss node .../devicetree/bindings/display/msm/dpu.txt | 4 ++- .../devicetree/bindings/display/msm/mdp5.txt | 2 +- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- drivers/gpu/drm/msm/msm_drv.c | 34 ++++++++----------- 8 files changed, 24 insertions(+), 26 deletions(-) -- 2.27.0.383.g050319c2ae-goog

6 19

[PULL] drm-misc-fixes
by Thomas Zimmermann 15 Jul '20

15 Jul '20

Hi Dave and Daniel, here is the PR for the current drm-misc-fixes. The aspeed fix is only about dmesg noise. The dmabuf locking appears to be a real bug. Best regards Thomas drm-misc-fixes-2020-07-15: * aspeed: setup fbdev console after registering device; avoids warning and stacktrace in dmesg log * dmabuf: protect dmabuf->name with a spinlock; avoids sleeping in atomic context The following changes since commit 00debf8109e5fad3db31375be2a3c515e1461b4a: drm/hisilicon/hibmc: Move drm_fbdev_generic_setup() down to avoid the splat (2020-07-08 09:08:22 +0000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2020-07-15 for you to fetch changes up to 6348dd291e3653534a9e28e6917569bc9967b35b: dmabuf: use spinlock to access dmabuf->name (2020-07-10 15:39:29 +0530) ---------------------------------------------------------------- * aspeed: setup fbdev console after registering device; avoids warning and stacktrace in dmesg log * dmabuf: protect dmabuf->name with a spinlock; avoids sleeping in atomic context ---------------------------------------------------------------- Charan Teja Kalla (1): dmabuf: use spinlock to access dmabuf->name Guenter Roeck (1): drm/aspeed: Call drm_fbdev_generic_setup after drm_dev_register drivers/dma-buf/dma-buf.c | 11 +++++++---- drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 3 +-- include/linux/dma-buf.h | 1 + 3 files changed, 9 insertions(+), 6 deletions(-)

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[git pull] vmwgfx-fixes-5.8
by Roland Scheidegger (VMware) 15 Jul '20

15 Jul '20

Dave, Daniel, vmwgfx-fixes pull for 5.8. Just one fix for now, but it's a really important one, causing black screens in VMs (sometimes on boot), hence marking it for stable. The following changes since commit 1f054fd26e29784d373c3d29c348ee48f1c41fb2: drm/vmwgfx: fix update of display surface when resolution changes (2020-07-14 04:05:52 +0200) are available in the Git repository at: git://people.freedesktop.org/~sroland/linux vmwgfx-fixes-5.8 for you to fetch changes up to 1f054fd26e29784d373c3d29c348ee48f1c41fb2: drm/vmwgfx: fix update of display surface when resolution changes (2020-07-14 04:05:52 +0200) ----------------------------------------------------------------

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dri-devel July 2020