dri-devel July 2020

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[PATCH v2 0/8] Initial SM8150 and SM8250 DPU bringup
by Jonathan Marek 11 Jul '20

11 Jul '20

These patches bring up SM8150 and SM8250 with basic functionality. Tested with displayport output (single mixer, video mode case). v2: rebased Jonathan Marek (8): drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250 drm/msm/dpu: update UBWC config for sm8150 and sm8250 drm/msm/dpu: move some sspp caps to dpu_caps drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845 drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3 drm/msm/dpu: intf timing path for displayport drm/msm/dpu: add SM8150 to hw catalog drm/msm/dpu: add SM8250 to hw catalog drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 - .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 288 +++++++++++++++++- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 48 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 20 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 29 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 16 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 18 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 7 - drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 75 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 +- 12 files changed, 364 insertions(+), 158 deletions(-) -- 2.26.1

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[PATCH v3] drm/msm: handle for EPROBE_DEFER for of_icc_get
by Jonathan Marek 10 Jul '20

10 Jul '20

Check for errors instead of silently not using icc if the msm driver probes before the interconnect driver. Allow ENODATA for ocmem path, as it is optional and this error is returned when "gfx-mem" path is provided but not "ocmem". Because msm_gpu_cleanup assumes msm_gpu_init has been called, the icc path init needs to be after msm_gpu_init for the error path to work. v2: changed to not only check for EPROBE_DEFER v3: move icc path init after msm_gpu_init to avoid deleting a WARN_ON Signed-off-by: Jonathan Marek <jonathan(a)marek.ca> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 65 +++++++++++++++---------- 1 file changed, 38 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 89673c7ed473..8ab75d7691bd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -895,7 +895,7 @@ static int adreno_get_legacy_pwrlevels(struct device *dev) return 0; } -static int adreno_get_pwrlevels(struct device *dev, +static void adreno_get_pwrlevels(struct device *dev, struct msm_gpu *gpu) { unsigned long freq = ULONG_MAX; @@ -930,24 +930,6 @@ static int adreno_get_pwrlevels(struct device *dev, } DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); - - /* Check for an interconnect path for the bus */ - gpu->icc_path = of_icc_get(dev, "gfx-mem"); - if (!gpu->icc_path) { - /* - * Keep compatbility with device trees that don't have an - * interconnect-names property. - */ - gpu->icc_path = of_icc_get(dev, NULL); - } - if (IS_ERR(gpu->icc_path)) - gpu->icc_path = NULL; - - gpu->ocmem_icc_path = of_icc_get(dev, "ocmem"); - if (IS_ERR(gpu->ocmem_icc_path)) - gpu->ocmem_icc_path = NULL; - - return 0; } int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, @@ -993,9 +975,11 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs, int nr_rings) { - struct adreno_platform_config *config = pdev->dev.platform_data; + struct device *dev = &pdev->dev; + struct adreno_platform_config *config = dev->platform_data; struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; + int ret; adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); @@ -1007,15 +991,42 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu_config.nr_rings = nr_rings; - adreno_get_pwrlevels(&pdev->dev, gpu); + adreno_get_pwrlevels(dev, gpu); - pm_runtime_set_autosuspend_delay(&pdev->dev, + pm_runtime_set_autosuspend_delay(dev, adreno_gpu->info->inactive_period); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(&pdev->dev); + pm_runtime_use_autosuspend(dev); + pm_runtime_enable(dev); - return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, + ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, adreno_gpu->info->name, &adreno_gpu_config); + if (ret) + return ret; + + /* Check for an interconnect path for the bus */ + gpu->icc_path = of_icc_get(dev, "gfx-mem"); + if (!gpu->icc_path) { + /* + * Keep compatbility with device trees that don't have an + * interconnect-names property. + */ + gpu->icc_path = of_icc_get(dev, NULL); + } + if (IS_ERR(gpu->icc_path)) { + ret = PTR_ERR(gpu->icc_path); + gpu->icc_path = NULL; + return ret; + } + + gpu->ocmem_icc_path = of_icc_get(dev, "ocmem"); + if (IS_ERR(gpu->ocmem_icc_path)) { + ret = PTR_ERR(gpu->ocmem_icc_path); + gpu->ocmem_icc_path = NULL; + /* allow -ENODATA, ocmem icc is optional */ + if (ret != -ENODATA) + return ret; + } + return 0; } void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) @@ -1026,8 +1037,8 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) release_firmware(adreno_gpu->fw[i]); + msm_gpu_cleanup(&adreno_gpu->base); + icc_put(gpu->icc_path); icc_put(gpu->ocmem_icc_path); - - msm_gpu_cleanup(&adreno_gpu->base); } -- 2.26.1

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[PATCH v2] drm/msm: handle for EPROBE_DEFER for of_icc_get
by Jonathan Marek 10 Jul '20

10 Jul '20

Check for errors instead of silently not using icc if the msm driver probes before the interconnect driver. Allow ENODATA for ocmem path, as it is optional and this error is returned when "gfx-mem" path is provided but not "ocmem". Remove the WARN_ON in msm_gpu_cleanup because INIT_LIST_HEAD won't have been called on the list yet when going through the defer error path. Changes in v2: * Changed to not only check for EPROBE_DEFER Signed-off-by: Jonathan Marek <jonathan(a)marek.ca> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 ++++++++++++++--- drivers/gpu/drm/msm/msm_gpu.c | 2 -- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 89673c7ed473..0f5217202eb5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -940,12 +940,20 @@ static int adreno_get_pwrlevels(struct device *dev, */ gpu->icc_path = of_icc_get(dev, NULL); } - if (IS_ERR(gpu->icc_path)) + if (IS_ERR(gpu->icc_path)) { + ret = PTR_ERR(gpu->icc_path); gpu->icc_path = NULL; + return ret; + } gpu->ocmem_icc_path = of_icc_get(dev, "ocmem"); - if (IS_ERR(gpu->ocmem_icc_path)) + if (IS_ERR(gpu->ocmem_icc_path)) { + ret = PTR_ERR(gpu->ocmem_icc_path); gpu->ocmem_icc_path = NULL; + /* allow -ENODATA, ocmem icc is optional */ + if (ret != -ENODATA) + return ret; + } return 0; } @@ -996,6 +1004,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_platform_config *config = pdev->dev.platform_data; struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; + int ret; adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); @@ -1007,7 +1016,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu_config.nr_rings = nr_rings; - adreno_get_pwrlevels(&pdev->dev, gpu); + ret = adreno_get_pwrlevels(&pdev->dev, gpu); + if (ret) + return ret; pm_runtime_set_autosuspend_delay(&pdev->dev, adreno_gpu->info->inactive_period); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index a22d30622306..ccf9a0dd9706 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -959,8 +959,6 @@ void msm_gpu_cleanup(struct msm_gpu *gpu) DBG("%s", gpu->name); - WARN_ON(!list_empty(&gpu->active_list)); - for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { msm_ringbuffer_destroy(gpu->rb[i]); gpu->rb[i] = NULL; -- 2.26.1

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[PATCH v2 1/2] drm/msm/a6xx: hwcg tables in gpulist
by Jonathan Marek 10 Jul '20

10 Jul '20

This will allow supporting different hwcg tables for a6xx. Signed-off-by: Jonathan Marek <jonathan(a)marek.ca> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 25 ++++++++++------------ drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 +++++++ 3 files changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 3397e5e00d1c..ddcbc57ac25d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -151,10 +151,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, a6xx_flush(gpu, ring); } -static const struct { - u32 offset; - u32 value; -} a6xx_hwcg[] = { +const struct adreno_reglist a630_hwcg[] = { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, @@ -259,7 +256,8 @@ static const struct { {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555} + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, }; static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) @@ -267,9 +265,13 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + const struct adreno_reglist *reg; unsigned int i; u32 val; + if (!adreno_gpu->info->hwcg) + return; + val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); /* Don't re-program the registers if they are already correct */ @@ -279,9 +281,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) /* Disable SP clock before programming HWCG registers */ gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); - for (i = 0; i < ARRAY_SIZE(a6xx_hwcg); i++) - gpu_write(gpu, a6xx_hwcg[i].offset, - state ? a6xx_hwcg[i].value : 0); + for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) + gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); @@ -437,12 +438,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); - /* - * enable hardware clockgating - * For now enable clock gating only for a630 - */ - if (adreno_is_a630(adreno_gpu)) - a6xx_set_hwcg(gpu, true); + /* enable hardware clockgating */ + a6xx_set_hwcg(gpu, true); /* VBIF/GBIF start*/ if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 7732f03d9e3a..97996e7fc668 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -200,6 +200,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", + .hwcg = a630_hwcg, }, { .rev = ADRENO_REV(6, 4, 0, ANY_ID), .revn = 640, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 2f5d2c3acc3a..426cabd374bb 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -68,6 +68,13 @@ struct adreno_gpu_funcs { int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); }; +struct adreno_reglist { + u32 offset; + u32 value; +}; + +extern const struct adreno_reglist a630_hwcg[]; + struct adreno_info { struct adreno_rev rev; uint32_t revn; @@ -78,6 +85,7 @@ struct adreno_info { struct msm_gpu *(*init)(struct drm_device *dev); const char *zapfw; u32 inactive_period; + const struct adreno_reglist *hwcg; }; const struct adreno_info *adreno_info(struct adreno_rev rev); -- 2.26.1

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[PATCH v4 0/7] Add support for GPU DDR BW scaling
by Akhil P Oommen 10 Jul '20

10 Jul '20

This is mostly a rebase of Sharat's patches [1] on the tip of msm-next branch. Changes compared to v3: 1. Rebased on top of Jonathan's patch which adds support for changing gpu freq through hfi on newer targets. Created patch 1 to make this the generic approach of setting gpu freq on newer targets. 2. As suggested by Rob, left the icc_path intact for pre-a6xx GPUs. As mentioned in [1], these patches have dependency on Georgi's series from opp/linux-next [2] and also Sibi's patch which adds a helper function to set and clear ddr bandwidth vote [2]. [1] https://patchwork.freedesktop.org/series/75291/ [2] https://kernel.googlesource.com/pub/scm/linux/kernel/git/vireshk/pm/+log/op… Akhil P Oommen (1): drm: msm: a6xx: set gpu freq through hfi Sharat Masetty (6): dt-bindings: drm/msm/gpu: Document gpu opp table drm: msm: a6xx: send opp instead of a frequency drm: msm: a6xx: use dev_pm_opp_set_bw to scale DDR arm64: dts: qcom: SDM845: Enable GPU DDR bw scaling arm64: dts: qcom: sc7180: Add interconnects property for GPU arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp .../devicetree/bindings/display/msm/gpu.txt | 28 ++++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 105 +++++++++++---------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/msm_gpu.c | 3 +- drivers/gpu/drm/msm/msm_gpu.h | 3 +- 7 files changed, 106 insertions(+), 53 deletions(-) -- 2.7.4

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[PATCH v3 0/2] drm/probe_helper, i915: Validate MST modes against PBN limits
by Lyude Paul 10 Jul '20

10 Jul '20

Something we've been missing for a while with drivers that support MST is being able to prune modes that can't be set due to bandwidth limitations. So, let's go ahead and add that. This also adds a new hook that was needed, mode_valid_ctx, so that we can grab additional locks as needed when validating modes. Lee Shawn C (1): drm/i915/mst: filter out the display mode exceed sink's capability Lyude Paul (1): drm/probe_helper: Add drm_connector_helper_funcs.mode_valid_ctx drivers/gpu/drm/drm_crtc_helper_internal.h | 7 +- drivers/gpu/drm/drm_probe_helper.c | 94 ++++++++++++++------- drivers/gpu/drm/i915/display/intel_dp_mst.c | 55 ++++++++---- include/drm/drm_modeset_helper_vtables.h | 42 +++++++++ 4 files changed, 147 insertions(+), 51 deletions(-) -- 2.26.2

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[PATCH][next] drm/amdgpu: fix spelling mistake "Falied" -> "Failed"
by Colin King 10 Jul '20

10 Jul '20

From: Colin Ian King <colin.king(a)canonical.com> There is a spelling mistake in a DRM_ERROR error message. Fix it. Signed-off-by: Colin Ian King <colin.king(a)canonical.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index e20695b44dbe..40706334f7a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1984,7 +1984,7 @@ static int psp_suspend(void *handle) ret = psp_tmr_terminate(psp); if (ret) { - DRM_ERROR("Falied to terminate tmr\n"); + DRM_ERROR("Failed to terminate tmr\n"); return ret; } -- 2.27.0

2 1

[v2 PATCH] drm/panel: auo, b116xw03: fix flash backlight when power on
by Jitao Shi 10 Jul '20

10 Jul '20

Delay the backlight on to make sure the video stable. Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- drivers/gpu/drm/panel/panel-simple.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 3ad828eaefe1..61781ffa7840 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -724,6 +724,7 @@ static const struct drm_display_mode auo_b116xw03_mode = { .vsync_end = 768 + 10 + 12, .vtotal = 768 + 10 + 12 + 6, .vrefresh = 60, + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, }; static const struct panel_desc auo_b116xw03 = { @@ -734,6 +735,12 @@ static const struct panel_desc auo_b116xw03 = { .width = 256, .height = 144, }, + .delay = { + .enable = 400, + }, + .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + .connector_type = DRM_MODE_CONNECTOR_eDP, }; static const struct drm_display_mode auo_b133xtn01_mode = { -- 2.25.1

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[PATCH v1 0/1] dt-bindings: fix simple-framebuffer warning
by Sam Ravnborg 10 Jul '20

10 Jul '20

Trivial fix for a long standing warning. At least not fixed in drm-msc-next for now. Just in case it was not fixed by someone else (Rob?) already. Sam Sam Ravnborg (1): dt-bindings: fix simple-framebuffer example .../bindings/display/simple-framebuffer.yaml | 45 +++++++++++----------- 1 file changed, 23 insertions(+), 22 deletions(-)

3 5

[PATCH v3 0/3] dt-bindings: display: convert panel bindings to DT Schema
by Sam Ravnborg 10 Jul '20

10 Jul '20

This patch-set convert 3 of the remaining panel bindings to yaml. This is a follow-up on v2 that converted a lot of panel bindings: https://lore.kernel.org/dri-devel/20200408195109.32692-1-sam@ravnborg.org/ All was applied except for the reaming three patches included here. One binding is a DSI binding so just added to panel-simple-dsi. The other two bindings addressed review feedback from Rob. Sebastian Reichel has a pending patch to address the remaining panel binding in display/panel/ All bindings pass dt-binding-check. Based on top of drm-misc-next. Sam Sam Ravnborg (3): dt-bindings: display: convert innolux,p079zca to DT Schema dt-bindings: display: convert samsung,s6e8aa0 to DT Schema dt-bindings: display: convert sharp,lq101r1sx01 to DT Schema .../bindings/display/panel/innolux,p079zca.txt | 22 ----- .../bindings/display/panel/panel-simple-dsi.yaml | 2 + .../bindings/display/panel/samsung,s6e8aa0.txt | 56 ------------ .../bindings/display/panel/samsung,s6e8aa0.yaml | 100 +++++++++++++++++++++ .../bindings/display/panel/sharp,lq101r1sx01.txt | 49 ---------- .../bindings/display/panel/sharp,lq101r1sx01.yaml | 87 ++++++++++++++++++ 6 files changed, 189 insertions(+), 127 deletions(-)

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dri-devel July 2020