dri-devel July 2020

dri-devel@lists.freedesktop.org

336 participants
772 discussions

[PATCH] Replace HTTP links with HTTPS ones: BACKLIGHT CLASS/SUBSYSTEM
by Alexander A. Klimov 10 Jul '20

10 Jul '20

Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster(a)al2klimov.de> --- Continuing my work started at 93431e0607e5. See also: git log --oneline '--author=Alexander A. Klimov <grandmaster(a)al2klimov.de>' v5.7..master (Actually letting a shell for loop submit all this stuff for me.) If there are any URLs to be removed completely or at least not HTTPSified: Just clearly say so and I'll *undo my change*. See also: https://lkml.org/lkml/2020/6/27/64 If there are any valid, but yet not changed URLs: See: https://lkml.org/lkml/2020/6/26/837 If you apply the patch, please let me know. drivers/video/backlight/led_bl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/backlight/led_bl.c b/drivers/video/backlight/led_bl.c index 3f66549997c8..2c48957e9b60 100644 --- a/drivers/video/backlight/led_bl.c +++ b/drivers/video/backlight/led_bl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2015-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2019 Texas Instruments Incorporated - https://www.ti.com/ * Author: Tomi Valkeinen <tomi.valkeinen(a)ti.com> * * Based on pwm_bl.c -- 2.27.0

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[PATCH] Replace HTTP links with HTTPS ones: DRM DRIVERS FOR BRIDGE CHIPS
by Alexander A. Klimov 10 Jul '20

10 Jul '20

Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster(a)al2klimov.de> --- Continuing my work started at 93431e0607e5. See also: git log --oneline '--author=Alexander A. Klimov <grandmaster(a)al2klimov.de>' v5.7..master (Actually letting a shell for loop submit all this stuff for me.) If there are any URLs to be removed completely or at least not HTTPSified: Just clearly say so and I'll *undo my change*. See also: https://lkml.org/lkml/2020/6/27/64 If there are any valid, but yet not changed URLs: See: https://lkml.org/lkml/2020/6/26/837 If you apply the patch, please let me know. drivers/gpu/drm/bridge/tc358768.c | 2 +- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index 6650fe4cfc20..ac3757ecade6 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com * Author: Peter Ujfalusi <peter.ujfalusi(a)ti.com> */ diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 6ad688b320ae..a17f3e3a4157 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * datasheet: http://www.ti.com/lit/ds/symlink/sn65dsi86.pdf + * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf */ #include <linux/clk.h> -- 2.27.0

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[PATCH] drm/msm/a6xx: add build_bw_table for A640/A650
by Jonathan Marek 10 Jul '20

10 Jul '20

This sets up bw tables for A640/A650 similar to A618/A630, 0 DDR bandwidth vote, and the CNOC vote. A640 has the same CNOC addresses as A630 and was working, but this is required for A650 to work. Eventually the bw table should be filled by querying the interconnect driver for each BW in the dts, but use these dummy tables for now. Signed-off-by: Jonathan Marek <jonathan(a)marek.ca> --- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 74 +++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index 9921e632f1ca..ccd44d0418f8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -281,6 +281,76 @@ static void a618_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) msg->cnoc_cmds_data[1][0] = 0x60000001; } +static void a640_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) +{ + /* + * Send a single "off" entry just to get things running + * TODO: bus scaling + */ + msg->bw_level_num = 1; + + msg->ddr_cmds_num = 3; + msg->ddr_wait_bitmask = 0x01; + + msg->ddr_cmds_addrs[0] = 0x50000; + msg->ddr_cmds_addrs[1] = 0x5003c; + msg->ddr_cmds_addrs[2] = 0x5000c; + + msg->ddr_cmds_data[0][0] = 0x40000000; + msg->ddr_cmds_data[0][1] = 0x40000000; + msg->ddr_cmds_data[0][2] = 0x40000000; + + /* + * These are the CX (CNOC) votes - these are used by the GMU but the + * votes are known and fixed for the target + */ + msg->cnoc_cmds_num = 3; + msg->cnoc_wait_bitmask = 0x01; + + msg->cnoc_cmds_addrs[0] = 0x50034; + msg->cnoc_cmds_addrs[1] = 0x5007c; + msg->cnoc_cmds_addrs[2] = 0x5004c; + + msg->cnoc_cmds_data[0][0] = 0x40000000; + msg->cnoc_cmds_data[0][1] = 0x00000000; + msg->cnoc_cmds_data[0][2] = 0x40000000; + + msg->cnoc_cmds_data[1][0] = 0x60000001; + msg->cnoc_cmds_data[1][1] = 0x20000001; + msg->cnoc_cmds_data[1][2] = 0x60000001; +} + +static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) +{ + /* + * Send a single "off" entry just to get things running + * TODO: bus scaling + */ + msg->bw_level_num = 1; + + msg->ddr_cmds_num = 3; + msg->ddr_wait_bitmask = 0x01; + + msg->ddr_cmds_addrs[0] = 0x50000; + msg->ddr_cmds_addrs[1] = 0x50004; + msg->ddr_cmds_addrs[2] = 0x5007c; + + msg->ddr_cmds_data[0][0] = 0x40000000; + msg->ddr_cmds_data[0][1] = 0x40000000; + msg->ddr_cmds_data[0][2] = 0x40000000; + + /* + * These are the CX (CNOC) votes - these are used by the GMU but the + * votes are known and fixed for the target + */ + msg->cnoc_cmds_num = 1; + msg->cnoc_wait_bitmask = 0x01; + + msg->cnoc_cmds_addrs[0] = 0x500a4; + msg->cnoc_cmds_data[0][0] = 0x40000000; + msg->cnoc_cmds_data[1][0] = 0x60000001; +} + static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) { /* Send a single "off" entry since the 630 GMU doesn't do bus scaling */ @@ -327,6 +397,10 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) if (adreno_is_a618(adreno_gpu)) a618_build_bw_table(&msg); + else if (adreno_is_a640(adreno_gpu)) + a640_build_bw_table(&msg); + else if (adreno_is_a650(adreno_gpu)) + a650_build_bw_table(&msg); else a6xx_build_bw_table(&msg); -- 2.26.1

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[PATCH] drm/msm/a6xx: fix crashstate capture for A650
by Jonathan Marek 10 Jul '20

10 Jul '20

A650 has a separate RSCC region, so dump RSCC registers separately, reading them from the RSCC base. Without this change a GPU hang will cause a system reset if CONFIG_DEV_COREDUMP is enabled. Signed-off-by: Jonathan Marek <jonathan(a)marek.ca> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 5 +++++ drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 25 +++++++++++++++------ drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 12 ++++++---- 3 files changed, 31 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 47df4745db50..c6d2bced8e5d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -127,6 +127,11 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ interval, timeout) +static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset) +{ + return msm_readl(gmu->rscc + (offset << 2)); +} + static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value) { return msm_writel(value, gmu->rscc + (offset << 2)); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index d6023ba8033c..959656ad6987 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -736,7 +736,8 @@ static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu, static void _a6xx_get_gmu_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_registers *regs, - struct a6xx_gpu_state_obj *obj) + struct a6xx_gpu_state_obj *obj, + bool rscc) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); @@ -755,9 +756,17 @@ static void _a6xx_get_gmu_registers(struct msm_gpu *gpu, u32 count = RANGE(regs->registers, i); int j; - for (j = 0; j < count; j++) - obj->data[index++] = gmu_read(gmu, - regs->registers[i] + j); + for (j = 0; j < count; j++) { + u32 offset = regs->registers[i] + j; + u32 val; + + if (rscc) + val = gmu_read_rscc(gmu, offset); + else + val = gmu_read(gmu, offset); + + obj->data[index++] = val; + } } } @@ -777,7 +786,9 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, /* Get the CX GMU registers from AHB */ _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0], - &a6xx_state->gmu_registers[0]); + &a6xx_state->gmu_registers[0], false); + _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1], + &a6xx_state->gmu_registers[1], true); if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) return; @@ -785,8 +796,8 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, /* Set the fence to ALLOW mode so we can access the registers */ gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); - _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1], - &a6xx_state->gmu_registers[1]); + _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2], + &a6xx_state->gmu_registers[2], false); } #define A6XX_GBIF_REGLIST_SIZE 1 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h index 24c974c293e5..846fd5b54c23 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -341,10 +341,6 @@ static const u32 a6xx_gmu_cx_registers[] = { 0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165, 0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc, 0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201, - /* GPU RSCC */ - 0x8c8c, 0x8c8c, 0x8d01, 0x8d02, 0x8f40, 0x8f42, 0x8f44, 0x8f47, - 0x8f4c, 0x8f87, 0x8fec, 0x8fef, 0x8ff4, 0x902f, 0x9094, 0x9097, - 0x909c, 0x90d7, 0x913c, 0x913f, 0x9144, 0x917f, /* GMU AO */ 0x9300, 0x9316, 0x9400, 0x9400, /* GPU CC */ @@ -357,8 +353,16 @@ static const u32 a6xx_gmu_cx_registers[] = { 0xbc00, 0xbc16, 0xbc20, 0xbc27, }; +static const u32 a6xx_gmu_cx_rscc_registers[] = { + /* GPU RSCC */ + 0x008c, 0x008c, 0x0101, 0x0102, 0x0340, 0x0342, 0x0344, 0x0347, + 0x034c, 0x0387, 0x03ec, 0x03ef, 0x03f4, 0x042f, 0x0494, 0x0497, + 0x049c, 0x04d7, 0x053c, 0x053f, 0x0544, 0x057f, +}; + static const struct a6xx_registers a6xx_gmu_reglist[] = { REGS(a6xx_gmu_cx_registers, 0, 0), + REGS(a6xx_gmu_cx_rscc_registers, 0, 0), REGS(a6xx_gmu_gx_registers, 0, 0), }; -- 2.26.1

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[PATCH v8 0/5] driver core: add probe error check helper
by Andrzej Hajda 10 Jul '20

10 Jul '20

Hi All, Thanks for comments. Changes since v7: - improved commit message - added R-Bs Changes since v6: - removed leftovers from old naming scheme in commit descritions, - added R-Bs. Changes since v5: - removed patch adding macro, dev_err_probe(dev, PTR_ERR(ptr), ...) should be used instead, - added dev_dbg logging in case of -EPROBE_DEFER, - renamed functions and vars according to comments, - extended docs, - cosmetics. Original message (with small adjustments): Recently I took some time to re-check error handling in drivers probe code, and I have noticed that number of incorrect resource acquisition error handling increased and there are no other propositions which can cure the situation. So I have decided to resend my old proposition of probe_err helper which should simplify resource acquisition error handling, it also extend it with adding defer probe reason to devices_deferred debugfs property, which should improve debugging experience for developers/testers. I have also added two patches showing usage and benefits of the helper. My dirty/ad-hoc cocci scripts shows that this helper can be used in at least 2700 places saving about 3500 lines of code. Regards Andrzej Andrzej Hajda (5): driver core: add device probe log helper driver core: add deferring probe reason to devices_deferred property drm/bridge/sii8620: fix resource acquisition error handling drm/bridge: lvds-codec: simplify error handling coccinelle: add script looking for cases where probe__err can be used drivers/base/base.h | 3 + drivers/base/core.c | 46 +++++ drivers/base/dd.c | 23 ++- drivers/gpu/drm/bridge/lvds-codec.c | 10 +- drivers/gpu/drm/bridge/sil-sii8620.c | 21 +-- include/linux/device.h | 3 + probe_err.cocci | 247 +++++++++++++++++++++++++++ 7 files changed, 333 insertions(+), 20 deletions(-) create mode 100644 probe_err.cocci -- 2.17.1

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[PATCH] DRM PANEL DRIVERS: Replace HTTP links with HTTPS ones
by Alexander A. Klimov 10 Jul '20

10 Jul '20

Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster(a)al2klimov.de> --- Continuing my work started at 93431e0607e5. See also: git log --oneline '--author=Alexander A. Klimov <grandmaster(a)al2klimov.de>' v5.7..master (Actually letting a shell for loop submit all this stuff for me.) If there are any URLs to be removed completely or at least not HTTPSified: Just clearly say so and I'll *undo my change*. See also: https://lkml.org/lkml/2020/6/27/64 If there are any valid, but yet not changed URLs: See: https://lkml.org/lkml/2020/6/26/837 If you apply the patch, please let me know. drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c b/drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c index 3a0229d60095..09f6b0cac854 100644 --- a/drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c +++ b/drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com * Author: Peter Ujfalusi <peter.ujfalusi(a)ti.com> */ -- 2.27.0

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[PATCH v8 0/6] Add support for DisplayPort driver on SnapDragon
by Tanmay Shah 10 Jul '20

10 Jul '20

These patches add Display-Port driver on SnapDragon/msm hardware. This series also contains device-tree bindings for msm DP driver. It also contains Makefile and Kconfig changes to compile msm DP driver. The block diagram of DP driver is shown below: +-------------+ |DRM FRAMEWORK| +------+------+ | +----v----+ | DP DRM | +----+----+ | +----v----+ +------------+| DP +----------++------+ + +---+| DISPLAY |+---+ | | | + +-+-----+-+ | | | | | | | | | | | | | | | | | | | | | | | | v v v v v v v +------+ +------+ +---+ +----+ +----+ +---+ +-----+ | DP | | DP | |DP | | DP | | DP | |DP | | DP | |PARSER| | HPD | |AUX| |LINK| |CTRL| |PHY| |POWER| +--+---+ +---+--+ +---+ +----+ +--+-+ +-+-+ +-----+ | | | +--v---+ +v-----v+ |DEVICE| | DP | | TREE | |CATALOG| +------+ +---+---+ | +---v----+ |CTRL/PHY| | HW | +--------+ Changes in v7: - Modify cover letter description and fix title. - Introduce dp-controller.yaml for common bindings across SOC - Rename dp-sc7180.yaml to dp-controller-sc7180.yaml for SC7180 bindings - Rename compatible string to qcom,sc7180-dp - Add assigned-clocks and assigned-clock-parents properties in bindings - Remove redundant code from driver - Extend series to include HPD detection logic Changes in v8: - Add MDSS AHB clock in bindings - Replace mode->vrefresh use with drm_mode_vrefresh API - Remove redundant aux config code from parser and aux module - Assign default max lanes if data-lanes property is not available - Fix use-after-free during DP driver remove - Unregister hardware clocks during driver cleanup This series depends-on: https://patchwork.freedesktop.org/patch/366159/ https://patchwork.freedesktop.org/patch/369859/ Chandan Uddaraju (4): dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon drm: add constant N value in helper file drm/msm/dp: add displayPort driver support drm/msm/dp: add support for DP PLL driver Jeykumar Sankaran (1): drm/msm/dpu: add display port support in DPU Tanmay Shah (1): drm/msm/dp: Add Display Port HPD feature .../display/msm/dp-controller-sc7180.yaml | 144 ++ .../bindings/display/msm/dp-controller.yaml | 61 + .../bindings/display/msm/dpu-sc7180.yaml | 11 + drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/msm/Kconfig | 16 + drivers/gpu/drm/msm/Makefile | 14 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 8 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 83 +- drivers/gpu/drm/msm/dp/dp_aux.c | 510 +++++ drivers/gpu/drm/msm/dp/dp_aux.h | 29 + drivers/gpu/drm/msm/dp/dp_catalog.c | 1060 ++++++++++ drivers/gpu/drm/msm/dp/dp_catalog.h | 104 + drivers/gpu/drm/msm/dp/dp_ctrl.c | 1707 +++++++++++++++++ drivers/gpu/drm/msm/dp/dp_ctrl.h | 35 + drivers/gpu/drm/msm/dp/dp_display.c | 1017 ++++++++++ drivers/gpu/drm/msm/dp/dp_display.h | 31 + drivers/gpu/drm/msm/dp/dp_drm.c | 168 ++ drivers/gpu/drm/msm/dp/dp_drm.h | 18 + drivers/gpu/drm/msm/dp/dp_hpd.c | 69 + drivers/gpu/drm/msm/dp/dp_hpd.h | 79 + drivers/gpu/drm/msm/dp/dp_link.c | 1216 ++++++++++++ drivers/gpu/drm/msm/dp/dp_link.h | 132 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 490 +++++ drivers/gpu/drm/msm/dp/dp_panel.h | 95 + drivers/gpu/drm/msm/dp/dp_parser.c | 267 +++ drivers/gpu/drm/msm/dp/dp_parser.h | 138 ++ drivers/gpu/drm/msm/dp/dp_pll.c | 99 + drivers/gpu/drm/msm/dp/dp_pll.h | 61 + drivers/gpu/drm/msm/dp/dp_pll_10nm.c | 917 +++++++++ drivers/gpu/drm/msm/dp/dp_pll_private.h | 111 ++ drivers/gpu/drm/msm/dp/dp_power.c | 392 ++++ drivers/gpu/drm/msm/dp/dp_power.h | 103 + drivers/gpu/drm/msm/dp/dp_reg.h | 517 +++++ drivers/gpu/drm/msm/msm_drv.c | 2 + drivers/gpu/drm/msm/msm_drv.h | 59 +- include/drm/drm_dp_helper.h | 1 + 37 files changed, 9776 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller.yaml create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.c create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.h create mode 100644 drivers/gpu/drm/msm/dp/dp_catalog.c create mode 100644 drivers/gpu/drm/msm/dp/dp_catalog.h create mode 100644 drivers/gpu/drm/msm/dp/dp_ctrl.c create mode 100644 drivers/gpu/drm/msm/dp/dp_ctrl.h create mode 100644 drivers/gpu/drm/msm/dp/dp_display.c create mode 100644 drivers/gpu/drm/msm/dp/dp_display.h create mode 100644 drivers/gpu/drm/msm/dp/dp_drm.c create mode 100644 drivers/gpu/drm/msm/dp/dp_drm.h create mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.c create mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.h create mode 100644 drivers/gpu/drm/msm/dp/dp_link.c create mode 100644 drivers/gpu/drm/msm/dp/dp_link.h create mode 100644 drivers/gpu/drm/msm/dp/dp_panel.c create mode 100644 drivers/gpu/drm/msm/dp/dp_panel.h create mode 100644 drivers/gpu/drm/msm/dp/dp_parser.c create mode 100644 drivers/gpu/drm/msm/dp/dp_parser.h create mode 100644 drivers/gpu/drm/msm/dp/dp_pll.c create mode 100644 drivers/gpu/drm/msm/dp/dp_pll.h create mode 100644 drivers/gpu/drm/msm/dp/dp_pll_10nm.c create mode 100644 drivers/gpu/drm/msm/dp/dp_pll_private.h create mode 100644 drivers/gpu/drm/msm/dp/dp_power.c create mode 100644 drivers/gpu/drm/msm/dp/dp_power.h create mode 100644 drivers/gpu/drm/msm/dp/dp_reg.h base-commit: 0a19b068acc47d05212f03e494381926dc0381e2 prerequisite-patch-id: 8058026a54241aa728a91dd1685419afb249959e prerequisite-patch-id: ed730eb83f84501579332a0f0ab98f7ef649e868 -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

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[Bug 205815] New: When playing a wine game, got black screen then screen flickers, game crashes and back to normal
by bugzilla-daemon＠bugzilla.kernel.org 10 Jul '20

10 Jul '20

https://bugzilla.kernel.org/show_bug.cgi?id=205815 Bug ID: 205815 Summary: When playing a wine game, got black screen then screen flickers, game crashes and back to normal Product: Drivers Version: 2.5 Kernel Version: 5.4.2-1~exp1 (Debian experimental) Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: ramaspaceship(a)free.fr Regression: No Created attachment 286235 --> https://bugzilla.kernel.org/attachment.cgi?id=286235&action=edit System journal Since I use a Ryzen 5 3400G I have trouble playing the Wine game I use to play. I have tried several kernels, and seen a lot of progress from 4.19 to 5.4. But it still fails after a while. I use Debian Buster with the latest Debian experimental kernel (5.4.2), Xorg and Mesa are from Sid. I attached the system journal of the last try (and failure). -- You are receiving this mail because: You are watching the assignee of the bug.

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[Bug 208513] New: Radeon RX480 graphics freeze with RIP: 0010:amdgpu_dm_atomic_commit_tail+0x273/0x1100 [amdgpu]
by bugzilla-daemon＠bugzilla.kernel.org 10 Jul '20

10 Jul '20

https://bugzilla.kernel.org/show_bug.cgi?id=208513 Bug ID: 208513 Summary: Radeon RX480 graphics freeze with RIP: 0010:amdgpu_dm_atomic_commit_tail+0x273/0x1100 [amdgpu] Product: Drivers Version: 2.5 Kernel Version: 5.7.7 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: blocking Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: jlp.bugs(a)gmail.com Regression: No I get frequent freezes with kernel 5.7, especially when having Firefox 77 open and watching videos. It looks like only graphics freezes as I can still hear stuff going on in the background. This is what I can see using "journalctl --boot=-1 -k" after reboot general protection fault, probably for non-canonical address 0x9ca86a805968f7f1: 0000 [#1] SMP NOPTI CPU: 1 PID: 117 Comm: kworker/u8:3 Not tainted 5.7.7-1-debug #1 openSUSE Tumbleweed (unreleased) Hardware name: System manufacturer System Product Name/H170 PRO GAMING, BIOS 3805 05/16/2018 Workqueue: events_unbound commit_work [drm_kms_helper] RIP: 0010:amdgpu_dm_atomic_commit_tail+0x273/0x1100 [amdgpu] Code: 43 08 8b 90 80 04 00 00 41 83 c6 01 44 39 f2 0f 87 3a ff ff ff 48 83 bd a0 fd ff ff 00 0f 84 03 01 00 00 48 8b bd a0 fd ff ff <80> bf b0 01 00 00 01 0f 86 ac 00 00 00 48 b9 00 00 00> RSP: 0018:ffffb8c40026bbe0 EFLAGS: 00010282 RAX: ffff99c28f74b000 RBX: ffff99c059f6c880 RCX: ffff99c1c32f7c00 RDX: 0000000000000006 RSI: ffffffffc0b6d540 RDI: 9ca86a805968f7f1 RBP: ffffb8c40026be68 R08: 0000000000000001 R09: 0000000000000001 R10: 00000000000003fb R11: 00000000000898df R12: ffff99c037db8400 R13: 0000000000000000 R14: 0000000000000006 R15: ffff99c037db8000 FS: 0000000000000000(0000) GS:ffff99c296c80000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007fb44bc04300 CR3: 000000066a2e4006 CR4: 00000000003606e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: ? ieee80211_sta_rx_queued_mgmt+0x89/0x2f0 [mac80211] ? update_load_avg+0x7e/0x630 ? set_next_entity+0xab/0x200 ? _raw_spin_unlock_irq+0xa/0x20 ? finish_task_switch+0x77/0x280 ? __schedule+0x205/0x560 ? _raw_spin_unlock_irq+0xa/0x20 ? wait_for_completion_timeout+0xcc/0x100 commit_tail+0x94/0x130 [drm_kms_helper] process_one_work+0x1da/0x3a0 worker_thread+0x46/0x320 ? rescuer_thread+0x400/0x400 kthread+0x115/0x140 ? __kthread_bind_mask+0x60/0x60 ret_from_fork+0x1f/0x40 Modules linked in: fuse ccm af_packet dmi_sysfs msr hid_logitech_hidpp joydev intel_rapl_msr intel_rapl_common x86_pkg_temp_thermal hid_logitech_dj intel_powerclamp coretemp crct10dif_pcl> dm_mod scsi_dh_rdac scsi_dh_emc scsi_dh_alua efivarfs ---[ end trace de4993090519763f ]--- RIP: 0010:amdgpu_dm_atomic_commit_tail+0x273/0x1100 [amdgpu] Code: 43 08 8b 90 80 04 00 00 41 83 c6 01 44 39 f2 0f 87 3a ff ff ff 48 83 bd a0 fd ff ff 00 0f 84 03 01 00 00 48 8b bd a0 fd ff ff <80> bf b0 01 00 00 01 0f 86 ac 00 00 00 48 b9 00 00 00> RSP: 0018:ffffb8c40026bbe0 EFLAGS: 00010282 RAX: ffff99c28f74b000 RBX: ffff99c059f6c880 RCX: ffff99c1c32f7c00 RDX: 0000000000000006 RSI: ffffffffc0b6d540 RDI: 9ca86a805968f7f1 RBP: ffffb8c40026be68 R08: 0000000000000001 R09: 0000000000000001 R10: 00000000000003fb R11: 00000000000898df R12: ffff99c037db8400 R13: 0000000000000000 R14: 0000000000000006 R15: ffff99c037db8000 FS: 0000000000000000(0000) GS:ffff99c296c80000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007fb44bc04300 CR3: 000000066a2e4006 CR4: 00000000003606e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Mesa is 20.1.2 name of display: :0 display: :0 screen: 0 direct rendering: Yes Extended renderer info (GLX_MESA_query_renderer): Vendor: X.Org (0x1002) Device: AMD Radeon (TM) RX 480 Graphics (POLARIS10, DRM 3.37.0, 5.7.7-1-debug, LLVM 10.0.0) (0x67df) Version: 20.1.2 Accelerated: yes Video memory: 8192MB Unified memory: no Preferred profile: core (0x1) Max core profile version: 4.6 Max compat profile version: 4.6 Max GLES1 profile version: 1.1 Max GLES[23] profile version: 3.2 Memory info (GL_ATI_meminfo): VBO free memory - total: 7001 MB, largest block: 7001 MB VBO free aux. memory - total: 7976 MB, largest block: 7976 MB Texture free memory - total: 7001 MB, largest block: 7001 MB Texture free aux. memory - total: 7976 MB, largest block: 7976 MB Renderbuffer free memory - total: 7001 MB, largest block: 7001 MB Renderbuffer free aux. memory - total: 7976 MB, largest block: 7976 MB Memory info (GL_NVX_gpu_memory_info): Dedicated video memory: 8192 MB Total available memory: 16384 MB Currently available dedicated video memory: 7001 MB OpenGL vendor string: X.Org OpenGL renderer string: AMD Radeon (TM) RX 480 Graphics (POLARIS10, DRM 3.37.0, 5.7.7-1-debug, LLVM 10.0.0) OpenGL core profile version string: 4.6 (Core Profile) Mesa 20.1.2 OpenGL core profile shading language version string: 4.60 OpenGL core profile context flags: (none) OpenGL core profile profile mask: core profile OpenGL version string: 4.6 (Compatibility Profile) Mesa 20.1.2 OpenGL shading language version string: 4.60 OpenGL context flags: (none) OpenGL profile mask: compatibility profile OpenGL ES profile version string: OpenGL ES 3.2 Mesa 20.1.2 OpenGL ES profile shading language version string: OpenGL ES GLSL ES 3.20 libdrm 2.4.102, xf86-video-amdgpu 19.1.0 -- You are receiving this mail because: You are watching the assignee of the bug.

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[PATCH v7 0/4] driver core: add probe error check helper
by Andrzej Hajda 10 Jul '20

10 Jul '20

Hi All, Thanks for comments. Changes since v6: - removed leftovers from old naming scheme in commit descritions, - added R-Bs. Changes since v5: - removed patch adding macro, dev_err_probe(dev, PTR_ERR(ptr), ...) should be used instead, - added dev_dbg logging in case of -EPROBE_DEFER, - renamed functions and vars according to comments, - extended docs, - cosmetics. Original message (with small adjustments): Recently I took some time to re-check error handling in drivers probe code, and I have noticed that number of incorrect resource acquisition error handling increased and there are no other propositions which can cure the situation. So I have decided to resend my old proposition of probe_err helper which should simplify resource acquisition error handling, it also extend it with adding defer probe reason to devices_deferred debugfs property, which should improve debugging experience for developers/testers. I have also added two patches showing usage and benefits of the helper. My dirty/ad-hoc cocci scripts shows that this helper can be used in at least 2700 places saving about 3500 lines of code. Regards Andrzej Andrzej Hajda (4): driver core: add device probe log helper driver core: add deferring probe reason to devices_deferred property drm/bridge/sii8620: fix resource acquisition error handling drm/bridge: lvds-codec: simplify error handling drivers/base/base.h | 3 ++ drivers/base/core.c | 46 ++++++++++++++++++++++++++++ drivers/base/dd.c | 23 +++++++++++++- drivers/gpu/drm/bridge/lvds-codec.c | 10 ++---- drivers/gpu/drm/bridge/sil-sii8620.c | 21 ++++++------- include/linux/device.h | 3 ++ 6 files changed, 86 insertions(+), 20 deletions(-) -- 2.17.1

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dri-devel July 2020