dri-devel September 2020

dri-devel@lists.freedesktop.org

359 participants
868 discussions

[PATCH] drm/bridge/synopsys: dsi: allow sending longer LP commands
by Yannick Fertre 07 Sep '20

07 Sep '20

From: Antonio Borneo <antonio.borneo(a)st.com> Current code does not properly computes the max length of LP commands that can be send during H or V sync, and rely on static values. Limiting the max LP length to 4 byte during the V-sync is overly conservative. Relax the limit and allows longer LP commands (16 bytes) to be sent during V-sync. Signed-off-by: Antonio Borneo <antonio.borneo(a)st.com> --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 17 +++++++++-------- 1 file … [View More]

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[PATCH v2] drm/bridge/synopsys: dsi: allow LP commands in video mode
by Yannick Fertre 07 Sep '20

07 Sep '20

From: Antonio Borneo <antonio.borneo(a)st.com> Current code only sends LP commands in command mode. Allows sending LP commands also in video mode by setting the proper flag in DSI_VID_MODE_CFG. Signed-off-by: Antonio Borneo <antonio.borneo(a)st.com> --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 1a24ea648ef8..… [View More]

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[PATCH v2 0/2] drm: fix virtio-gpu + sev
by Gerd Hoffmann 07 Sep '20

07 Sep '20

virtio-gpu must make sure scatter list segments are not too big. Gerd Hoffmann (2): drm: allow limiting the scatter list size. drm/virtio: set max_segment include/drm/drm_device.h | 8 ++++++++ include/drm/drm_prime.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 3 ++- drivers/gpu/drm/drm_gem_shmem_helper.c | 3 ++- drivers/gpu/drm/drm_prime.c | 10 +++++++--- drivers/gpu/drm/etnaviv/etnaviv_gem.c | 3 ++- … [View More]

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[PATCH] udmabuf: Add missing compact_ioctl
by Kristian H. Kristensen 07 Sep '20

07 Sep '20

Make sure we can use this on mixed systems. Signed-off-by: Kristian H. Kristensen <hoegsberg(a)google.com> --- drivers/dma-buf/udmabuf.c | 3 +++ 1 file changed, 3 insertions(+) Sorry Gerd for all the spam. Once I finally got git send-email working, I ended up sending a version with all ChromeOS decorations, of course. Here's a normal upstream version. Email based workflow - the barrier is real. Kristian diff --git a/drivers/dma-buf/udmabuf.c b/drivers/dma-buf/udmabuf.c index … [View More]

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[Bug 209179] New: nouveau 0000:01:00.0: can't change power state from D3cold to D0 (config space inaccessible)
by bugzilla-daemon＠bugzilla.kernel.org 07 Sep '20

07 Sep '20

https://bugzilla.kernel.org/show_bug.cgi?id=209179 Bug ID: 209179 Summary: nouveau 0000:01:00.0: can't change power state from D3cold to D0 (config space inaccessible) Product: Drivers Version: 2.5 Kernel Version: 5.8.7 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) … [View More]Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: kernel(a)mattmcadoo.com Regression: No Created attachment 292387 --> https://bugzilla.kernel.org/attachment.cgi?id=292387&action=edit full dmesg output Lenovo ThinkPad W540, with hybrid video (Intel/Nvidia) 01:00.0 VGA compatible controller: NVIDIA Corporation GK107GLM [Quadro K1100M] (rev ff) (prog-if ff) !!! Unknown header type 7f Kernel driver in use: nouveau Dmesg has numerous errors like the following (full dmesg output in attachment): [ 16.243256] nouveau 0000:01:00.0: can't change power state from D3cold to D0 (config space inaccessible) [ 16.243265] nouveau 0000:01:00.0: can't change power state from D3cold to D0 (config space inaccessible) [ 16.303637] nouveau 0000:01:00.0: can't change power state from D3cold to D0 (config space inaccessible) [ 16.303659] nouveau 0000:01:00.0: tmr: stalled at ffffffffffffffff [ 16.303659] ------------[ cut here ]------------ [ 16.303660] nouveau 0000:01:00.0: timeout [ 16.303679] WARNING: CPU: 6 PID: 87 at drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c:107 nvkm_pmu_reset+0x275/0x2d0 [ 16.303680] Modules linked in: [ 16.303683] CPU: 6 PID: 87 Comm: kworker/6:1 Not tainted 5.8.7-gentoo #5 [ 16.303684] Hardware name: LENOVO 20BG0014US/20BG0014US, BIOS GNET91WW (2.39 ) 05/29/2019 [ 16.303688] Workqueue: pm pm_runtime_work [ 16.303691] RIP: 0010:nvkm_pmu_reset+0x275/0x2d0 [ 16.303693] Code: e4 74 57 e8 dd 09 10 00 4c 89 e2 48 c7 c7 66 d0 33 84 48 83 05 8b f5 5e 04 01 48 89 c6 e8 62 19 1c ff 48 83 05 83 f5 5e 04 01 <0f> 0b 48 83 05 81 f5 5e 04 01 48 8b 45 00 48 83 05 7d f5 5e 04 01 [ 16.303694] RSP: 0018:ffffc900002c7a80 EFLAGS: 00010202 [ 16.303695] RAX: 0000000000000000 RBX: ffff88885338e800 RCX: 0000000000000000 [ 16.303696] RDX: 0000000000000001 RSI: 0000000000000002 RDI: 0000000000000001 [ 16.303697] RBP: ffff88885337da00 R08: 0000000000000491 R09: 0000000000000000 [ 16.303699] R10: 0000000000000002 R11: 000000000007aee4 R12: ffff8888591c95a0 [ 16.303700] R13: 00000003caea9731 R14: 00000003caea956f R15: ffff88885921b0b0 [ 16.303701] FS: 0000000000000000(0000) GS:ffff88885d780000(0000) knlGS:0000000000000000 [ 16.303702] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 16.303703] CR2: 000055a07a344f14 CR3: 000000083ea48006 CR4: 00000000001606e0 [ 16.303704] Call Trace: [ 16.303710] nvkm_pmu_preinit+0x1a/0x30 [ 16.303712] nvkm_subdev_preinit+0x44/0xa0 [ 16.303716] ? nvkm_device_pci_preinit+0x5e/0x80 [ 16.303717] nvkm_device_init+0x76/0x2e0 [ 16.303720] nvkm_udevice_init+0x64/0x90 [ 16.303721] nvkm_object_init+0x52/0x190 [ 16.303723] nvkm_object_init+0x8b/0x190 [ 16.303724] nvkm_object_init+0x8b/0x190 [ 16.303727] ? new_id_store+0x2a0/0x2a0 [ 16.303729] nvkm_client_resume+0x19/0x30 [ 16.303732] nvif_client_resume+0x22/0x30 [ 16.303734] nouveau_do_resume+0x32/0x120 [ 16.303736] nouveau_pmops_runtime_resume+0xa4/0x1d0 [ 16.303738] pci_pm_runtime_resume+0xba/0x120 [ 16.303740] ? new_id_store+0x2a0/0x2a0 [ 16.303741] __rpm_callback+0xd6/0x1f0 [ 16.303743] ? new_id_store+0x2a0/0x2a0 [ 16.303744] ? new_id_store+0x2a0/0x2a0 [ 16.303745] rpm_callback+0x36/0xc0 [ 16.303746] ? new_id_store+0x2a0/0x2a0 [ 16.303748] rpm_resume+0x7d0/0x9f0 [ 16.303750] __pm_runtime_resume+0x5c/0x90 [ 16.303751] ? new_id_store+0x2a0/0x2a0 [ 16.303752] rpm_get_suppliers+0x4c/0x1a0 [ 16.303754] ? new_id_store+0x2a0/0x2a0 [ 16.303755] __rpm_callback+0x198/0x1f0 [ 16.303756] ? new_id_store+0x2a0/0x2a0 [ 16.303757] ? new_id_store+0x2a0/0x2a0 [ 16.303759] rpm_callback+0x36/0xc0 [ 16.303760] ? new_id_store+0x2a0/0x2a0 [ 16.303761] rpm_resume+0x7d0/0x9f0 [ 16.303763] pm_runtime_work+0x99/0xf0 [ 16.303765] process_one_work+0x203/0x620 [ 16.303767] worker_thread+0x257/0x5f0 [ 16.303769] ? rescuer_thread+0x4a0/0x4a0 [ 16.303770] kthread+0x1d0/0x220 [ 16.303772] ? kthread_create_worker+0xa0/0xa0 [ 16.303774] ret_from_fork+0x22/0x30 [ 16.303777] ---[ end trace 084955cbd974989c ]--- -- You are receiving this mail because: You are watching the assignee of the bug. [View Less]

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[PATCH] drm/panel: s6e63m0: Fix up DRM_DEV* regression
by Linus Walleij 06 Sep '20

06 Sep '20

Ooops the panel drivers stopped to use DRM_DEV* messages and we predictably create errors by merging code that still use it. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- .../gpu/drm/panel/panel-samsung-s6e63m0-dsi.c | 28 +++++++++---------- .../gpu/drm/panel/panel-samsung-s6e63m0-spi.c | 8 +++--- drivers/gpu/drm/panel/panel-samsung-s6e63m0.c | 18 ++++++------ 3 files changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e63m0-… [View More]dsi.c b/drivers/gpu/drm/panel/panel-samsung-s6e63m0-dsi.c index 2ec9e7900791..6eca6f4c0e99 100644 --- a/drivers/gpu/drm/panel/panel-samsung-s6e63m0-dsi.c +++ b/drivers/gpu/drm/panel/panel-samsung-s6e63m0-dsi.c @@ -23,11 +23,11 @@ static int s6e63m0_dsi_dcs_read(struct device *dev, const u8 cmd, u8 *data) ret = mipi_dsi_dcs_read(dsi, cmd, data, 1); if (ret < 0) { - DRM_DEV_ERROR(dev, "could not read DCS CMD %02x\n", cmd); + dev_err(dev, "could not read DCS CMD %02x\n", cmd); return ret; } - DRM_DEV_INFO(dev, "DSI read CMD %02x = %02x\n", cmd, *data); + dev_info(dev, "DSI read CMD %02x = %02x\n", cmd, *data); return 0; } @@ -42,7 +42,7 @@ static int s6e63m0_dsi_dcs_write(struct device *dev, const u8 *data, size_t len) int chunk; int ret; - DRM_DEV_INFO(dev, "DSI writing dcs seq: %*ph\n", (int)len, data); + dev_info(dev, "DSI writing dcs seq: %*ph\n", (int)len, data); /* Pick out and skip past the DCS command */ cmd = *seqp; @@ -56,9 +56,9 @@ static int s6e63m0_dsi_dcs_write(struct device *dev, const u8 *data, size_t len) chunk = S6E63M0_DSI_MAX_CHUNK; ret = mipi_dsi_dcs_write(dsi, cmd, seqp, chunk); if (ret < 0) { - DRM_DEV_ERROR(dev, - "error sending DCS command seq cmd %02x\n", - cmd); + dev_err(dev, + "error sending DCS command seq cmd %02x\n", + cmd); return ret; } cmdwritten += chunk; @@ -70,23 +70,23 @@ static int s6e63m0_dsi_dcs_write(struct device *dev, const u8 *data, size_t len) chunk = S6E63M0_DSI_MAX_CHUNK; ret = mipi_dsi_dcs_write(dsi, MCS_GLOBAL_PARAM, &cmdwritten, 1); if (ret < 0) { - DRM_DEV_ERROR(dev, - "error sending CMD %02x global param %02x\n", - cmd, cmdwritten); + dev_err(dev, + "error sending CMD %02x global param %02x\n", + cmd, cmdwritten); return ret; } ret = mipi_dsi_dcs_write(dsi, cmd, seqp, chunk); if (ret < 0) { - DRM_DEV_ERROR(dev, - "error sending CMD %02x chunk\n", - cmd); + dev_err(dev, + "error sending CMD %02x chunk\n", + cmd); return ret; } cmdwritten += chunk; seqp += chunk; } - DRM_DEV_INFO(dev, "sent command %02x %02x bytes\n", - cmd, cmdwritten); + dev_info(dev, "sent command %02x %02x bytes\n", + cmd, cmdwritten); usleep_range(8000, 9000); diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e63m0-spi.c b/drivers/gpu/drm/panel/panel-samsung-s6e63m0-spi.c index 3b1a2a3a44ea..d298d780220d 100644 --- a/drivers/gpu/drm/panel/panel-samsung-s6e63m0-spi.c +++ b/drivers/gpu/drm/panel/panel-samsung-s6e63m0-spi.c @@ -41,7 +41,7 @@ static int s6e63m0_spi_dcs_write(struct device *dev, const u8 *data, size_t len) { int ret = 0; - DRM_DEV_DEBUG(dev, "SPI writing dcs seq: %*ph\n", (int)len, data); + dev_dbg(dev, "SPI writing dcs seq: %*ph\n", (int)len, data); ret = s6e63m0_spi_write_word(dev, *data); while (!ret && --len) { @@ -50,8 +50,8 @@ static int s6e63m0_spi_dcs_write(struct device *dev, const u8 *data, size_t len) } if (ret) { - DRM_DEV_ERROR(dev, "SPI error %d writing dcs seq: %*ph\n", ret, - (int)len, data); + dev_err(dev, "SPI error %d writing dcs seq: %*ph\n", ret, + (int)len, data); } usleep_range(300, 310); @@ -68,7 +68,7 @@ static int s6e63m0_spi_probe(struct spi_device *spi) spi->mode = SPI_MODE_3; ret = spi_setup(spi); if (ret < 0) { - DRM_DEV_ERROR(dev, "spi setup failed.\n"); + dev_err(dev, "spi setup failed.\n"); return ret; } return s6e63m0_probe(dev, s6e63m0_spi_dcs_read, s6e63m0_spi_dcs_write, diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c b/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c index c9472b2ae0cd..7f2fd5516958 100644 --- a/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c +++ b/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c @@ -179,28 +179,28 @@ static int s6e63m0_check_lcd_type(struct s6e63m0 *ctx) ret = s6e63m0_clear_error(ctx); if (ret) { - DRM_DEV_ERROR(ctx->dev, "error checking LCD type (%d)\n", - ret); + dev_err(ctx->dev, "error checking LCD type (%d)\n", + ret); ctx->lcd_type = 0x00; return ret; } - DRM_DEV_INFO(ctx->dev, "MTP ID: %02x %02x %02x\n", id1, id2, id3); + dev_info(ctx->dev, "MTP ID: %02x %02x %02x\n", id1, id2, id3); /* We attempt to detect what panel is mounted on the controller */ switch (id2) { case S6E63M0_LCD_ID_VALUE_M2: - DRM_DEV_INFO(ctx->dev, - "detected LCD panel AMS397GE MIPI M2\n"); + dev_info(ctx->dev, + "detected LCD panel AMS397GE MIPI M2\n"); break; case S6E63M0_LCD_ID_VALUE_SM2: case S6E63M0_LCD_ID_VALUE_SM2_1: - DRM_DEV_INFO(ctx->dev, - "detected LCD panel AMS397GE MIPI SM2\n"); + dev_info(ctx->dev, + "detected LCD panel AMS397GE MIPI SM2\n"); break; default: - DRM_DEV_INFO(ctx->dev, - "unknown LCD panel type %02x\n", id2); + dev_info(ctx->dev, + "unknown LCD panel type %02x\n", id2); break; } -- 2.26.2 [View Less]

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[Bug 209159] New: AMD Vega 20 framebuffer switch fails on 5.9rc2+
by bugzilla-daemon＠bugzilla.kernel.org 06 Sep '20

06 Sep '20

https://bugzilla.kernel.org/show_bug.cgi?id=209159 Bug ID: 209159 Summary: AMD Vega 20 framebuffer switch fails on 5.9rc2+ Product: Drivers Version: 2.5 Kernel Version: 5.9-rc2/3 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org … [View More]

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[GIT PULL FOR v5.9] Fix Kconfig dependency issue with DMAENGINES selection
by Laurent Pinchart 05 Sep '20

05 Sep '20

Hi Dave and Daniel, This small pull request fixes a Kconfig dependency issue introduced in v5.9-rc1. Among the three patches required to fix the issue, the ASoC fix has been merged in Linus' tree already. I haven't been able to get the RapidIO patch reviewed by the subsystem maintainers, so I've included it here as it's a dependency for the DRM patch. The following changes since commit f75aef392f869018f78cfedf3c320a6b3fcfda6b: Linux 5.9-rc3 (2020-08-30 16:01:54 -0700) are available in the … [View More]

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[PATCH v16 00/20] iommu/arm-smmu + drm/msm: per-process GPU pgtables
by Rob Clark 05 Sep '20

05 Sep '20

From: Rob Clark <robdclark(a)chromium.org> NOTE: I have re-ordered the series, and propose that we could merge this series in the following order: 1) 01-11 - merge via drm / msm-next 2) 12-15 - merge via iommu, no dependency on msm-next pull req 3) 16-18 - patch 16 has a dependency on 02 and 04, so it would need to come post -rc1 or on following cycle, but I think it would be unlikely to conflict with other … [View More]arm-smmu patches (other than Bjorn's smmu handover series?) 4) 19-20 - dt bits should be safe to land in any order without breaking anything ---- This series adds an Adreno SMMU implementation to arm-smmu to allow GPU hardware pagetable switching. The Adreno GPU has built in capabilities to switch the TTBR0 pagetable during runtime to allow each individual instance or application to have its own pagetable. In order to take advantage of the HW capabilities there are certain requirements needed of the SMMU hardware. This series adds support for an Adreno specific arm-smmu implementation. The new implementation 1) ensures that the GPU domain is always assigned context bank 0, 2) enables split pagetable support (TTBR1) so that the instance specific pagetable can be swapped while the global memory remains in place and 3) shares the current pagetable configuration with the GPU driver to allow it to create its own io-pgtable instances. The series then adds the drm/msm code to enable these features. For targets that support it allocate new pagetables using the io-pgtable configuration shared by the arm-smmu driver and swap them in during runtime. This version of the series merges the previous patchset(s) [1] and [2] with the following improvements: v16: (Respin by Rob) - Fix indentation - Re-order series to split drm and iommu parts v15: (Respin by Rob) - Adjust dt bindings to keep SoC specific compatible (Doug) - Add dts workaround for cheza fw limitation - Add missing 'select IOMMU_IO_PGTABLE' (Guenter) v14: (Respin by Rob) - Minor update to 16/20 (only force ASID to zero in one place) - Addition of sc7180 dtsi patch. v13: (Respin by Rob) - Switch to a private interface between adreno-smmu and GPU driver, dropping the custom domain attr (Will Deacon) - Rework the SCTLR.HUPCF patch to add new fields in smmu_domain->cfg rather than adding new impl hook (Will Deacon) - Drop for_each_cfg_sme() in favor of plain for() loop (Will Deacon) - Fix context refcnt'ing issue which was causing problems with GPU crash recover stress testing. - Spiff up $debugfs/gem to show process information associated with VMAs v12: - Nitpick cleanups in gpu/drm/msm/msm_iommu.c (Rob Clark) - Reorg in gpu/drm/msm/msm_gpu.c (Rob Clark) - Use the default asid for the context bank so that iommu_tlb_flush_all works - Flush the UCHE after a page switch - Add the SCTLR.HUPCF patch at the end of the series v11: - Add implementation specific get_attr/set_attr functions (per Rob Clark) - Fix context bank allocation (per Bjorn Andersson) v10: - arm-smmu: add implementation hook to allocate context banks - arm-smmu: Match the GPU domain by stream ID instead of compatible string - arm-smmu: Make DOMAIN_ATTR_PGTABLE_CFG bi-directional. The leaf driver queries the configuration to create a pagetable and then sends the newly created configuration back to the smmu-driver to enable TTBR0 - drm/msm: Add context reference counting for submissions - drm/msm: Use dummy functions to skip TLB operations on per-instance pagetables [1] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045653.html [2] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045659.html Jordan Crouse (12): drm/msm: Add a context pointer to the submitqueue drm/msm: Drop context arg to gpu->submit() drm/msm: Set the global virtual address range from the IOMMU domain drm/msm: Add support to create a local pagetable drm/msm: Add support for private address space instances drm/msm/a6xx: Add support for per-instance pagetables iommu/arm-smmu: Pass io-pgtable config to implementation specific function iommu/arm-smmu: Add support for split pagetables iommu/arm-smmu: Prepare for the adreno-smmu implementation iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU Rob Clark (8): drm/msm: Remove dangling submitqueue references drm/msm: Add private interface for adreno-smmu drm/msm/gpu: Add dev_to_gpu() helper drm/msm: Set adreno_smmu as gpu's drvdata drm/msm: Show process names in gem_describe iommu/arm-smmu: Constify some helpers iommu/arm-smmu: Add a way for implementations to influence SCTLR arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMU .../devicetree/bindings/iommu/arm,smmu.yaml | 9 +- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 9 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 68 +++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/adreno_device.c | 12 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 18 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +- drivers/gpu/drm/msm/msm_drv.c | 16 +- drivers/gpu/drm/msm/msm_drv.h | 25 +++ drivers/gpu/drm/msm/msm_gem.c | 25 ++- drivers/gpu/drm/msm/msm_gem.h | 6 + drivers/gpu/drm/msm/msm_gem_submit.c | 8 +- drivers/gpu/drm/msm/msm_gem_vma.c | 10 + drivers/gpu/drm/msm/msm_gpu.c | 41 +++- drivers/gpu/drm/msm/msm_gpu.h | 21 +- drivers/gpu/drm/msm/msm_gpummu.c | 2 +- drivers/gpu/drm/msm/msm_iommu.c | 206 +++++++++++++++++- drivers/gpu/drm/msm/msm_mmu.h | 16 +- drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + drivers/gpu/drm/msm/msm_submitqueue.c | 7 +- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 6 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 155 ++++++++++++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 100 ++++----- drivers/iommu/arm/arm-smmu/arm-smmu.h | 87 +++++++- include/linux/adreno-smmu-priv.h | 36 +++ 29 files changed, 771 insertions(+), 134 deletions(-) create mode 100644 include/linux/adreno-smmu-priv.h -- 2.26.2 [View Less]

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[PATCH v6 0/3] drm/vkms: Introduces writeback support
by Rodrigo Siqueira 04 Sep '20

04 Sep '20

This is the V5 version of a series that introduces the writeback support to VKMS. The first two patches of this series are a pre-work for the latest patch that adds the writeback connector, this patchset can be seen in two parts: * A pre-work that aims to make vkms composer operations a little bit more generic; these patches try to centralize the vkms framebuffer operations. * The final patch enables the support for writeback in vkms. In the previous review, Emil suggested multiple changes … [View More]

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dri-devel September 2020